41 lines
1.5 KiB
Diff
41 lines
1.5 KiB
Diff
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From 2f60eb2f03b9c3d0a31592c55a88ef62b1403b5d Mon Sep 17 00:00:00 2001
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From: Matthias Kaehlcke <mka@chromium.org>
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Date: Wed, 10 Apr 2019 11:30:10 -0700
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Subject: [PATCH 19/54] ARM: dts: rockchip: Remove unnecessary setting of UART0
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SCLK rate on veyron
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Some veyron devices have a Bluetooth controller connected on UART0.
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The UART needs to operate at a high speed, however setting the clock
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rate at initialization has no practical effect. During initialization
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user space adjusts the UART baudrate multiple times, which ends up
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changing the SCLK rate. After a successful initiatalization the clk
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is running at the desired speed (48MHz).
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Remove the unnecessary clock rate configuration from the DT.
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Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
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Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ----
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1 file changed, 4 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
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index 5181d9435fda..fa38eb967f12 100644
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--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
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+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
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@@ -395,10 +395,6 @@
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&uart0 {
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status = "okay";
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- /* We need to go faster than 24MHz, so adjust clock parents / rates */
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- assigned-clocks = <&cru SCLK_UART0>;
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- assigned-clock-rates = <48000000>;
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-
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/* Pins don't include flow control by default; add that in */
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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--
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2.11.0
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