63 lines
1.9 KiB
Diff
63 lines
1.9 KiB
Diff
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From 8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d Mon Sep 17 00:00:00 2001
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From: Douglas Anderson <dianders@chromium.org>
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Date: Thu, 11 Apr 2019 16:21:55 -0700
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Subject: [PATCH 23/54] ARM: dts: rockchip: Add DDR retention/poweroff to
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rk3288-veyron hogs
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Even though upstream Linux doesn't yet go into deep enough suspend to
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get DDR into self refresh, there is no harm in setting these pins up.
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They'll only actually do something if we go into a deeper suspend but
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leaving them configed always is fine.
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Signed-off-by: Douglas Anderson <dianders@chromium.org>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 4 ++++
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arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++
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2 files changed, 8 insertions(+)
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diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
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index 72c4754032e9..b9cc90f0f25c 100644
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--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
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+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
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@@ -229,6 +229,8 @@
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&pinctrl {
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pinctrl-0 = <
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/* Common for sleep and wake, but no owners */
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+ &ddr0_retention
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+ &ddrio_pwroff
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&global_pwroff
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/* Wake only */
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@@ -236,6 +238,8 @@
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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+ &ddr0_retention
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+ &ddrio_pwroff
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&global_pwroff
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/* Sleep only */
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diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
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index e4f0c00011f2..35755870bf66 100644
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--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
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+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
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@@ -453,10 +453,14 @@
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <
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/* Common for sleep and wake, but no owners */
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+ &ddr0_retention
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+ &ddrio_pwroff
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&global_pwroff
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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+ &ddr0_retention
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+ &ddrio_pwroff
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&global_pwroff
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>;
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--
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2.11.0
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