238 lines
3.9 KiB
Diff
238 lines
3.9 KiB
Diff
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From 0ca87bd5baa62e5734800ee63e3a6301c90e8613 Mon Sep 17 00:00:00 2001
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From: Douglas Anderson <dianders@chromium.org>
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Date: Tue, 21 May 2019 13:32:15 -0700
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Subject: [PATCH 36/54] ARM: dts: rockchip: Add pin names for
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rk3288-veyron-jerry
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This is like the same change for rk3288-veyron-minnie. See that patch
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for more details.
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Signed-off-by: Douglas Anderson <dianders@chromium.org>
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Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm/boot/dts/rk3288-veyron-jerry.dts | 207 ++++++++++++++++++++++++++++++
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1 file changed, 207 insertions(+)
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diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
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index b1613af83d5d..164561f04c1d 100644
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--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
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+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
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@@ -103,6 +103,213 @@
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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+&gpio0 {
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+ gpio-line-names = "PMIC_SLEEP_AP",
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+ "DDRIO_PWROFF",
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+ "DDRIO_RETEN",
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+ "TS3A227E_INT_L",
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+ "PMIC_INT_L",
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+ "PWR_KEY_L",
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+ "AP_LID_INT_L",
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+ "EC_IN_RW",
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+
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+ "AC_PRESENT_AP",
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+ /*
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+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
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+ * it REC_MODE_L.
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+ */
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+ "RECOVERY_SW_L",
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+ "OTP_OUT",
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+ "HOST1_PWR_EN",
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+ "USBOTG_PWREN_H",
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+ "AP_WARM_RESET_H",
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+ "nFAULT2",
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+ "I2C0_SDA_PMIC",
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+
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+ "I2C0_SCL_PMIC",
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+ "SUSPEND_L",
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+ "USB_INT";
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+};
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+
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+&gpio2 {
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+ gpio-line-names = "CONFIG0",
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+ "CONFIG1",
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+ "CONFIG2",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "CONFIG3",
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+
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+ "",
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+ "EMMC_RST_L",
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+ "",
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+ "",
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+ "BL_PWR_EN",
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+ "AVDD_1V8_DISP_EN";
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+};
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+
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+&gpio3 {
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+ gpio-line-names = "FLASH0_D0",
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+ "FLASH0_D1",
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+ "FLASH0_D2",
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+ "FLASH0_D3",
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+ "FLASH0_D4",
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+ "FLASH0_D5",
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+ "FLASH0_D6",
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+ "FLASH0_D7",
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+
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ "FLASH0_CS2/EMMC_CMD",
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+ "",
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+ "FLASH0_DQS/EMMC_CLKO";
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+};
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+
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+&gpio4 {
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+ gpio-line-names = "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ "UART0_RXD",
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+ "UART0_TXD",
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+ "UART0_CTS",
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+ "UART0_RTS",
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+ "SDIO0_D0",
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+ "SDIO0_D1",
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+ "SDIO0_D2",
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+ "SDIO0_D3",
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+
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+ "SDIO0_CMD",
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+ "SDIO0_CLK",
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+ "BT_DEV_WAKE",
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+ "",
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+ "WIFI_ENABLE_H",
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+ "BT_ENABLE_L",
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+ "WIFI_HOST_WAKE",
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+ "BT_HOST_WAKE";
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+};
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+
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+&gpio5 {
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+ gpio-line-names = "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ "",
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+ "",
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+ "",
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+ "",
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+ "SPI0_CLK",
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+ "SPI0_CS0",
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+ "SPI0_TXD",
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+ "SPI0_RXD",
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+
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+ "",
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+ "",
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+ "",
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+ "VCC50_HDMI_EN";
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+};
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+
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+&gpio6 {
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+ gpio-line-names = "I2S0_SCLK",
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+ "I2S0_LRCK_RX",
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+ "I2S0_LRCK_TX",
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+ "I2S0_SDI",
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+ "I2S0_SDO0",
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+ "HP_DET_H",
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+ "",
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+ "INT_CODEC",
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+
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+ "I2S0_CLK",
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+ "I2C2_SDA",
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+ "I2C2_SCL",
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+ "MICDET",
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+ "",
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+ "",
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+ "",
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+ "",
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+
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+ "SDMMC_D0",
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+ "SDMMC_D1",
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+ "SDMMC_D2",
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+ "SDMMC_D3",
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+ "SDMMC_CLK",
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+ "SDMMC_CMD";
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+};
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+
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+&gpio7 {
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+ gpio-line-names = "LCDC_BL",
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+ "PWM_LOG",
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+ "BL_EN",
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+ "TRACKPAD_INT",
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+ "TPM_INT_H",
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+ "SDMMC_DET_L",
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+ /*
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+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
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+ * it FW_WP_AP.
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+ */
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+ "AP_FLASH_WP_L",
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+ "EC_INT",
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+
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+ "CPU_NMI",
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+ "DVSOK",
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+ "",
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+ "EDP_HPD",
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+ "DVS1",
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+ "nFAULT1",
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+ "LCD_EN",
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+ "DVS2",
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+
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+ "VCC5V_GOOD_H",
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+ "I2C4_SDA_TP",
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+ "I2C4_SCL_TP",
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+ "I2C5_SDA_HDMI",
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+ "I2C5_SCL_HDMI",
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+ "5V_DRV",
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+ "UART2_RXD",
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+ "UART2_TXD";
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+};
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+
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+&gpio8 {
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+ gpio-line-names = "RAM_ID0",
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+ "RAM_ID1",
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+ "RAM_ID2",
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+ "RAM_ID3",
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+ "I2C1_SDA_TPM",
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+ "I2C1_SCL_TPM",
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+ "SPI2_CLK",
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+ "SPI2_CS0",
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+
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+ "SPI2_RXD",
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+ "SPI2_TXD";
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+};
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+
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&pinctrl {
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backlight {
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bl_pwr_en: bl_pwr_en {
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--
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2.11.0
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