108 lines
3.0 KiB
Diff
108 lines
3.0 KiB
Diff
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From f4480cb8198085607c15e523b49aa21bc38cf62c Mon Sep 17 00:00:00 2001
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From: Myy Miouyouyou <myy@miouyouyou.fr>
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Date: Tue, 21 Nov 2017 21:47:33 +0100
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Subject: [PATCH 1/5] ARM: DTSI: rk3288.dtsi: Define the VPU services
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Still, you will need appropriate drivers to use them.
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Contrary to the previous versions of this patch, these services are :
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* NOT enabled by default;
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* MUST be activated in each individual DTS;
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I currently do not own enough RK3288 boards to ensure that the
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VPU and HEVC MMU + services can be activated without issues.
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Still this patch does not generate issues like the previous one AND
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still enable these services on boot, when activated properly in
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individual DTS files.
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Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
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---
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arch/arm/boot/dts/rk3288.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 63 insertions(+)
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index 30b04257..bc3601ac 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -1182,6 +1182,27 @@
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status = "disabled";
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};
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+ vpu_service: vpu-service@ff9a0000 {
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+ compatible = "rockchip,vpu_service";
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+ reg = <0x0 0xff9a0000 0x0 0x800>;
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+ interrupts =
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+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_enc", "irq_dec";
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+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
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+ clock-names = "aclk_vcodec", "hclk_vcodec";
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+ power-domains = <&power RK3288_PD_VIDEO>;
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+ rockchip,grf = <&grf>;
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+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
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+ reset-names = "video_a", "video_h";
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+ iommus = <&vpu_mmu>;
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+ iommu_enabled = <1>;
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+ dev_mode = <0>;
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+ status = "disabled";
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+ /* 0 means ion, 1 means drm */
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+ allocator = <1>;
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+ };
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+
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hevc_mmu: iommu@ff9c0440 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
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@@ -1191,6 +1212,48 @@
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status = "disabled";
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};
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+ hevc_service: hevc-service@ff9c0000 {
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+ compatible = "rockchip,hevc_service";
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+ reg = <0x0 0xff9c0000 0x0 0x400>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_dec";
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+ clocks =
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+ <&cru ACLK_HEVC>,
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+ <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ clock-names =
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+ "aclk_vcodec",
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+ "hclk_vcodec",
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+ "clk_core",
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+ "clk_cabac";
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+ /*
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+ * The 4K hevc would also work well with 500/125/300/300,
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+ * no more err irq and reset request.
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+ */
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+ assigned-clocks =
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+ <&cru ACLK_HEVC>,
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+ <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ assigned-clock-rates =
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+ <400000000>,
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+ <100000000>,
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+ <300000000>,
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+ <300000000>;
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+
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+ resets = <&cru SRST_HEVC>;
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+ reset-names = "video";
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+ power-domains = <&power RK3288_PD_HEVC>;
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+ rockchip,grf = <&grf>;
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+ dev_mode = <1>;
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+ iommus = <&hevc_mmu>;
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+ iommu_enabled = <1>;
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+ status = "disabled";
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+ /* 0 means ion, 1 means drm */
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+ allocator = <1>;
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+ };
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+
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gpu: gpu@ffa30000 {
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compatible = "rockchip,rk3288-mali", "arm,mali-t760";
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reg = <0x0 0xffa30000 0x0 0x10000>;
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--
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2.14.1
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