From 01368ff288ddaf7ebc4170be084bb00588936a38 Mon Sep 17 00:00:00 2001 From: Hal Emmerich Date: Wed, 22 May 2019 10:37:57 -0500 Subject: [PATCH] Add patches to fix emmc yelling, and get clock properly fixes issue #26 --- .../dont-yell-about-bad-mmc-phases.patch | 46 +++++++++++++++++++ ...hw_get_rate-in-MMC-phase-calculation.patch | 36 +++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 resources/BuildResources/patches-tested/kernel/dont-yell-about-bad-mmc-phases.patch create mode 100644 resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch diff --git a/resources/BuildResources/patches-tested/kernel/dont-yell-about-bad-mmc-phases.patch b/resources/BuildResources/patches-tested/kernel/dont-yell-about-bad-mmc-phases.patch new file mode 100644 index 0000000..5085d05 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/dont-yell-about-bad-mmc-phases.patch @@ -0,0 +1,46 @@ +From: Douglas Anderson +Subject: [PATCH] clk: rockchip: Don't yell about bad mmc phases when getting +Date: Fri, 3 May 2019 14:22:08 -0700 + +At boot time, my rk3288-veyron devices yell with 8 lines that look +like this: + [ 0.000000] rockchip_mmc_get_phase: invalid clk rate + +This is because the clock framework at clk_register() time tries to +get the phase but we don't have a parent yet. + +While the errors appear to be harmless they are still ugly and, in +general, we don't want yells like this in the log unless they are +important. + +There's no real reason to be yelling here. We can still return +-EINVAL to indicate that the phase makes no sense without a parent. +If someone really tries to do tuning and the clock is reported as 0 +then we'll see the yells in rockchip_mmc_set_phase(). + +Fixes: 4bf59902b500 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") +Signed-off-by: Douglas Anderson +--- + + drivers/clk/rockchip/clk-mmc-phase.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c +index 026a26bb702d..dbec84238ecd 100644 +--- a/drivers/clk/rockchip/clk-mmc-phase.c ++++ b/drivers/clk/rockchip/clk-mmc-phase.c +@@ -61,10 +61,8 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) + u32 delay_num = 0; + + /* See the comment for rockchip_mmc_set_phase below */ +- if (!rate) { +- pr_err("%s: invalid clk rate\n", __func__); ++ if (!rate) + return -EINVAL; +- } + + raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); + +-- +2.21.0.1020.gf2820cf01a-goog + diff --git a/resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch b/resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch new file mode 100644 index 0000000..fe0aaf7 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch @@ -0,0 +1,36 @@ +From: Douglas Anderson +Date: Tue, 07 May 2019 13:49:58 -0700 (PDT) + +When calculating the MMC phase we can just use clk_hw_get_rate() +instead of clk_get_rate(). This avoids recalculating the rate. + +Suggested-by: Stephen Boyd +Signed-off-by: Douglas Anderson +--- + + drivers/clk/rockchip/clk-mmc-phase.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c +index 026a26bb702d..07526f64dbfd 100644 +--- a/drivers/clk/rockchip/clk-mmc-phase.c ++++ b/drivers/clk/rockchip/clk-mmc-phase.c +@@ -55,7 +55,7 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, + static int rockchip_mmc_get_phase(struct clk_hw *hw) + { + struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); +- unsigned long rate = clk_get_rate(hw->clk); ++ unsigned long rate = clk_hw_get_rate(hw); + u32 raw_value; + u16 degrees; + u32 delay_num = 0; +@@ -86,7 +86,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) + static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) + { + struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); +- unsigned long rate = clk_get_rate(hw->clk); ++ unsigned long rate = clk_hw_get_rate(hw); + u8 nineties, remainder; + u8 delay_num; + u32 raw_value; +