diff --git a/makefile b/makefile index 84ec0de..2dc3bb7 100644 --- a/makefile +++ b/makefile @@ -13,7 +13,7 @@ # You should have received a copy of the GNU General Public License # along with PrawnOS. If not, see . -KVER=4.19.53 +KVER=4.19.67 ifeq ($(PRAWNOS_SUITE),) PRAWNOS_SUITE=buster endif diff --git a/resources/BuildResources/cmdline b/resources/BuildResources/cmdline index d42a517..03de9f1 100644 --- a/resources/BuildResources/cmdline +++ b/resources/BuildResources/cmdline @@ -1 +1 @@ -console=tty1 init=/sbin/init root=PARTUUID=%U/PARTNROFF=1 rootfstype=ext4 rootwait ro net.ifnames=0 \ No newline at end of file +console=tty1 init=/sbin/init root=PARTUUID=%U/PARTNROFF=1 rootfstype=ext4 rootwait ro net.ifnames=0 console=ttyS2,115200n8 earlyprintk=ttyS2,115200n8 \ No newline at end of file diff --git a/resources/BuildResources/config b/resources/BuildResources/config index 37ca4d4..0c1db66 100644 --- a/resources/BuildResources/config +++ b/resources/BuildResources/config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 4.19.53-gnu Kernel Configuration +# Linux/arm 4.19.67-gnu Kernel Configuration # # @@ -1441,7 +1441,7 @@ CONFIG_SWPHY=y # # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set -# CONFIG_ASIX_PHY is not set +# CONFIG_AX88796B_PHY is not set # CONFIG_AT803X_PHY is not set # CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM87XX_PHY is not set @@ -1525,15 +1525,18 @@ CONFIG_WLAN=y # CONFIG_WLAN_VENDOR_ADMTEK is not set CONFIG_ATH_COMMON=y CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set +CONFIG_ATH_DEBUG=y +# CONFIG_ATH_TRACEPOINTS is not set # CONFIG_ATH5K is not set # CONFIG_ATH5K_PCI is not set CONFIG_ATH9K_HW=y CONFIG_ATH9K_COMMON=y +CONFIG_ATH9K_COMMON_DEBUG=y CONFIG_ATH9K_BTCOEX_SUPPORT=y # CONFIG_ATH9K is not set CONFIG_ATH9K_HTC=y -# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HTC_DEBUGFS=y +# CONFIG_ATH9K_COMMON_SPECTRAL is not set CONFIG_CARL9170=y CONFIG_CARL9170_LEDS=y CONFIG_CARL9170_WPC=y diff --git a/resources/BuildResources/patches-tested/DTS/0006-ARM-DTSI-rk3288-Missing-GRF-handles.patch b/resources/BuildResources/patches-tested/DTS/0006-ARM-DTSI-rk3288-Missing-GRF-handles.patch deleted file mode 100644 index 1014485..0000000 --- a/resources/BuildResources/patches-tested/DTS/0006-ARM-DTSI-rk3288-Missing-GRF-handles.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 771bcfe1735e42650b763e52a042a9fd98b2fa5b Mon Sep 17 00:00:00 2001 -From: Myy Miouyouyou -Date: Thu, 19 Oct 2017 21:20:43 +0200 -Subject: [PATCH 09/28] ARM: DTSI: rk3288.dtsi: Missing GRF handles - -Add missing GRF handles. - -This patch is taken from the patches provided by the ARMbian team. - -Signed-off-by: Myy Miouyouyou ---- - arch/arm/boot/dts/rk3288.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 356ed1e6..5b789528 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -547,6 +547,7 @@ - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; -+ rockchip,grf = <&grf>; - status = "disabled"; - }; - -@@ -655,6 +656,7 @@ - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; -+ rockchip,grf = <&grf>; - status = "disabled"; - }; - -@@ -666,6 +668,7 @@ - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; -+ rockchip,grf = <&grf>; - status = "disabled"; - }; - -@@ -677,6 +680,7 @@ - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; -+ rockchip,grf = <&grf>; - status = "disabled"; - }; - -@@ -688,6 +692,7 @@ - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; -+ rockchip,grf = <&grf>; - status = "disabled"; - }; - --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0001-ARM-dts-rockchip-Fix-rk3288-rock2-vcc_flash-name.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0001-ARM-dts-rockchip-Fix-rk3288-rock2-vcc_flash-name.patch new file mode 100644 index 0000000..a0e9556 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0001-ARM-dts-rockchip-Fix-rk3288-rock2-vcc_flash-name.patch @@ -0,0 +1,31 @@ +From 03d9f8fa2bfdc791865624d3adc29070cf67814e Mon Sep 17 00:00:00 2001 +From: John Keeping +Date: Tue, 13 Nov 2018 15:24:13 +0000 +Subject: [PATCH 01/54] ARM: dts: rockchip: Fix rk3288-rock2 vcc_flash name + +There is no functional change from this, but it is confusing to find two +copies of vcc_sys and no vcc_flash when looking in +/sys/class/regulator/*/name. + +Signed-off-by: John Keeping +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-rock2-som.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi +index 50325489c0ce..32e1ab336662 100644 +--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi ++++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi +@@ -25,7 +25,7 @@ + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; ++ regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <150>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0002-ARM-dts-rockchip-Add-all-CPUs-in-cooling-maps.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0002-ARM-dts-rockchip-Add-all-CPUs-in-cooling-maps.patch new file mode 100644 index 0000000..a2a56aa --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0002-ARM-dts-rockchip-Add-all-CPUs-in-cooling-maps.patch @@ -0,0 +1,143 @@ +From 99935bd4b5b4558beb069222e6d6143fe5830d64 Mon Sep 17 00:00:00 2001 +From: Viresh Kumar +Date: Fri, 16 Nov 2018 15:31:13 +0530 +Subject: [PATCH 02/54] ARM: dts: rockchip: Add all CPUs in cooling maps + +Each CPU can (and does) participate in cooling down the system but the +DT only captures a handful of them, normally CPU0, in the cooling maps. +Things work by chance currently as under normal circumstances its the +first CPU of each cluster which is used by the operating systems to +probe the cooling devices. But as soon as this CPU ordering changes and +any other CPU is used to bring up the cooling device, we will start +seeing failures. + +Also the DT is rather incomplete when we list only one CPU in the +cooling maps, as the hardware doesn't have any such limitations. + +Update cooling maps to include all devices affected by individual trip +points. + +Signed-off-by: Viresh Kumar +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk322x.dtsi | 10 ++++++++-- + arch/arm/boot/dts/rk3288-veyron-mickey.dts | 24 ++++++++++++++---------- + arch/arm/boot/dts/rk3288.dtsi | 15 ++++++++++++--- + 3 files changed, 34 insertions(+), 15 deletions(-) + +diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi +index cd8f2a3b0e91..29f19076dceb 100644 +--- a/arch/arm/boot/dts/rk322x.dtsi ++++ b/arch/arm/boot/dts/rk322x.dtsi +@@ -493,12 +493,18 @@ + map0 { + trip = <&cpu_alert0>; + cooling-device = +- <&cpu0 THERMAL_NO_LIMIT 6>; ++ <&cpu0 THERMAL_NO_LIMIT 6>, ++ <&cpu1 THERMAL_NO_LIMIT 6>, ++ <&cpu2 THERMAL_NO_LIMIT 6>, ++ <&cpu3 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +index 1e0158acf895..d889ab3c8235 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +@@ -81,8 +81,10 @@ + */ + cpu_warm_limit_cpu { + trip = <&cpu_alert_warm>; +- cooling-device = +- <&cpu0 THERMAL_NO_LIMIT 4>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, ++ <&cpu1 THERMAL_NO_LIMIT 4>, ++ <&cpu2 THERMAL_NO_LIMIT 4>, ++ <&cpu3 THERMAL_NO_LIMIT 4>; + }; + + /* +@@ -103,23 +105,25 @@ + */ + cpu_almost_hot_limit_cpu { + trip = <&cpu_alert_almost_hot>; +- cooling-device = +- <&cpu0 5 6>; ++ cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, ++ <&cpu3 5 6>; + }; + cpu_hot_limit_cpu { + trip = <&cpu_alert_hot>; +- cooling-device = +- <&cpu0 7 7>; ++ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, ++ <&cpu3 7 7>; + }; + cpu_hotter_limit_cpu { + trip = <&cpu_alert_hotter>; +- cooling-device = +- <&cpu0 7 8>; ++ cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, ++ <&cpu3 7 8>; + }; + cpu_very_hot_limit_cpu { + trip = <&cpu_alert_very_hot>; +- cooling-device = +- <&cpu0 8 THERMAL_NO_LIMIT>; ++ cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, ++ <&cpu1 8 THERMAL_NO_LIMIT>, ++ <&cpu2 8 THERMAL_NO_LIMIT>, ++ <&cpu3 8 THERMAL_NO_LIMIT>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 0840ffb3205c..1da86e82bb57 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -508,12 +508,18 @@ + map0 { + trip = <&cpu_alert0>; + cooling-device = +- <&cpu0 THERMAL_NO_LIMIT 6>; ++ <&cpu0 THERMAL_NO_LIMIT 6>, ++ <&cpu1 THERMAL_NO_LIMIT 6>, ++ <&cpu2 THERMAL_NO_LIMIT 6>, ++ <&cpu3 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +@@ -541,7 +547,10 @@ + map0 { + trip = <&gpu_alert0>; + cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0003-ARM-dts-rockchip-add-VPU-device-node-for-RK3288.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0003-ARM-dts-rockchip-add-VPU-device-node-for-RK3288.patch new file mode 100644 index 0000000..9244927 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0003-ARM-dts-rockchip-add-VPU-device-node-for-RK3288.patch @@ -0,0 +1,52 @@ +From ad5399d12ca4f68fdb9e58e4b9a556eb997a9639 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Fri, 30 Nov 2018 14:34:31 -0300 +Subject: [PATCH 03/54] ARM: dts: rockchip: add VPU device node for RK3288 + +Add the Video Processing Unit node for RK3288 SoC. + +Fix the VPU IOMMU node, which was disabled and lacking +its power domain property. + +Reviewed-by: Tomasz Figa +Signed-off-by: Ezequiel Garcia +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 1da86e82bb57..ca7d52daa8fb 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1232,6 +1232,18 @@ + }; + }; + ++ vpu: video-codec@ff9a0000 { ++ compatible = "rockchip,rk3288-vpu"; ++ reg = <0x0 0xff9a0000 0x0 0x800>; ++ interrupts = , ++ ; ++ interrupt-names = "vepu", "vdpu"; ++ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vpu_mmu>; ++ power-domains = <&power RK3288_PD_VIDEO>; ++ }; ++ + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0800 0x0 0x100>; +@@ -1240,7 +1252,7 @@ + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +- status = "disabled"; ++ power-domains = <&power RK3288_PD_VIDEO>; + }; + + hevc_mmu: iommu@ff9c0440 { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0005-ARM-dts-rockchip-add-chosen-node-on-veyron-devices.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0005-ARM-dts-rockchip-add-chosen-node-on-veyron-devices.patch new file mode 100644 index 0000000..991f0d5 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0005-ARM-dts-rockchip-add-chosen-node-on-veyron-devices.patch @@ -0,0 +1,33 @@ +From 5aed37a5cdef6453eb3bf307574e19e547ca0432 Mon Sep 17 00:00:00 2001 +From: Enric Balletbo i Serra +Date: Fri, 15 Feb 2019 12:51:50 +0100 +Subject: [PATCH 05/54] ARM: dts: rockchip: add chosen node on veyron devices + +In order to use earlycon, the stdout-path property needs to be set +in the chosen node. All veyron devices use uart2 for debugging, so +add it to the core veyron dtsi. + +Signed-off-by: Enric Balletbo i Serra +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index d8bf939a3aff..0bc2409f6903 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -10,6 +10,10 @@ + #include "rk3288.dtsi" + + / { ++ chosen { ++ stdout-path = "serial2:115200n8"; ++ }; ++ + /* + * The default coreboot on veyron devices ignores memory@0 nodes + * and would instead create another memory node. +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0009-ARM-dts-rockchip-add-grf-reference-in-rk3288-tsadc-n.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0009-ARM-dts-rockchip-add-grf-reference-in-rk3288-tsadc-n.patch new file mode 100644 index 0000000..e18928e --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0009-ARM-dts-rockchip-add-grf-reference-in-rk3288-tsadc-n.patch @@ -0,0 +1,37 @@ +From 494da92d56e45c88966fab4db2bed1a2f300c5f8 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 24 Feb 2019 21:52:00 +0000 +Subject: [PATCH 09/54] ARM: dts: rockchip: add grf reference in rk3288 tsadc + node + +The following message can be seen during boot: + + rockchip-thermal ff280000.tsadc: Missing rockchip,grf property + +Fix this by adding rockchip,grf property to tsadc node. + +The warning itself is not relevant on rk3288 right now, as the +tsadc doesn't need to set GRF-values at this point and only newer +variants do. + +Signed-off-by: Jonas Karlman +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index ca7d52daa8fb..b577f3e41811 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -569,6 +569,7 @@ + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <1>; ++ rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0011-ARM-dts-rockchip-Fix-gic-efuse-sort-ordering-for-rk3.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0011-ARM-dts-rockchip-Fix-gic-efuse-sort-ordering-for-rk3.patch new file mode 100644 index 0000000..316df0f --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0011-ARM-dts-rockchip-Fix-gic-efuse-sort-ordering-for-rk3.patch @@ -0,0 +1,61 @@ +From a2b2012eab25aad00a7dd587d1754115491e59eb Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 20 Mar 2019 13:13:59 -0700 +Subject: [PATCH 11/54] ARM: dts: rockchip: Fix gic/efuse sort ordering for + rk3288 + +It can be seen that 0xffb40000 < 0xffc01000, thus efuse comes first. + +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 26 +++++++++++++------------- + 1 file changed, 13 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index b577f3e41811..743a7d85daf7 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1379,19 +1379,6 @@ + reg = <0x0 0xffaf0080 0x0 0x20>; + }; + +- gic: interrupt-controller@ffc01000 { +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x0 0xffc01000 0x0 0x1000>, +- <0x0 0xffc02000 0x0 0x2000>, +- <0x0 0xffc04000 0x0 0x2000>, +- <0x0 0xffc06000 0x0 0x2000>; +- interrupts = ; +- }; +- + efuse: efuse@ffb40000 { + compatible = "rockchip,rk3288-efuse"; + reg = <0x0 0xffb40000 0x0 0x20>; +@@ -1405,6 +1392,19 @@ + }; + }; + ++ gic: interrupt-controller@ffc01000 { ++ compatible = "arm,gic-400"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ ++ reg = <0x0 0xffc01000 0x0 0x1000>, ++ <0x0 0xffc02000 0x0 0x2000>, ++ <0x0 0xffc04000 0x0 0x2000>, ++ <0x0 0xffc06000 0x0 0x2000>; ++ interrupts = ; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3288-pinctrl"; + rockchip,grf = <&grf>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0012-ARM-dts-rockchip-Add-rk3288-veyron-jerry-rev-10-15.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0012-ARM-dts-rockchip-Add-rk3288-veyron-jerry-rev-10-15.patch new file mode 100644 index 0000000..22bb92c --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0012-ARM-dts-rockchip-Add-rk3288-veyron-jerry-rev-10-15.patch @@ -0,0 +1,44 @@ +From 0c4cac5e8f0313a8777055c0c66a2216f78c6054 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Fri, 22 Mar 2019 12:59:24 -0700 +Subject: [PATCH 12/54] ARM: dts: rockchip: Add rk3288-veyron-jerry rev 10-15 + +As far as I can tell/remember rev10 was originally created to support +making a SKU of jerry that had a different LCD. rev11-rev15 were +added to give some wiggle room for future builds. Downstream has a +separate device tree for rev10-rev15 (compared to rev3-rev7) with the +expectation that differences relating to the LCD would be accounted +for there but nothing was ever added to the rev10-rev15 making it +identical to the rev3-rev7 one. + +It's likely nothing actually shipped with rev10-rev15 but they are +listed in the downstream kernel's device tree and it seems like it +should add a little safety if we match them here just in case +something actually shipped with one of these revisions and that device +will break if we don't claim support. + +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-jerry.dts | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +index 2ba89895c33a..517c6999a978 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +@@ -11,7 +11,10 @@ + + / { + model = "Google Jerry"; +- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", ++ compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", ++ "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", ++ "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", ++ "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", + "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", + "google,veyron-jerry-rev3", "google,veyron-jerry", + "google,veyron", "rockchip,rk3288"; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0013-ARM-dts-rockchip-Add-dvs-gpios-to-rk3288-veyron-jerr.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0013-ARM-dts-rockchip-Add-dvs-gpios-to-rk3288-veyron-jerr.patch new file mode 100644 index 0000000..9e9063b --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0013-ARM-dts-rockchip-Add-dvs-gpios-to-rk3288-veyron-jerr.patch @@ -0,0 +1,44 @@ +From 21f843ff948b4283c5d1f309651e90f978f5494e Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Fri, 22 Mar 2019 09:52:09 -0700 +Subject: [PATCH 13/54] ARM: dts: rockchip: Add dvs-gpios to + rk3288-veyron-jerry + +When the rk3288-jerry device tree was first submitted we left out the +dvs-gpios because I pointed out that the property "dvs-gpios" wasn't +yet supported upstream [1]. Soon after that the property was added in +commit bad47ad2eef3 ("regulator: rk808: fixed the overshoot when +adjust voltage"). ...but we forgot to go back and add the property to +the jerry device tree file. Let's do so now. + +NOTE: without this patch, jerry is likely still stable (thanks to the +fallback of making many small jumps in the rk808 regulator code) but +it'll take quite a bit longer to make voltage transitions. + +[1] https://lore.kernel.org/linux-arm-kernel/CAD=FV=WwFgjzbk9xF5TU_ie6UnHQMyrZ176D4+jJTWWOoaKC2Q@mail.gmail.com/ + +Fixes: f3ee390e4ef2 ("ARM: dts: rockchip: add veyron-jerry board") +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-jerry.dts | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +index 517c6999a978..3e8f700a0d64 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +@@ -64,7 +64,9 @@ + + &rk808 { + pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; ++ pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; ++ dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, ++ <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; + + regulators { + mic_vcc: LDO_REG2 { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0014-ARM-dts-rockchip-Add-vdd_logic-to-rk3288-veyron.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0014-ARM-dts-rockchip-Add-vdd_logic-to-rk3288-veyron.patch new file mode 100644 index 0000000..92f8917 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0014-ARM-dts-rockchip-Add-vdd_logic-to-rk3288-veyron.patch @@ -0,0 +1,125 @@ +From 864c2fee4ee93f53a8efed206c01ebce546df4e9 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 21 Mar 2019 13:19:44 -0700 +Subject: [PATCH 14/54] ARM: dts: rockchip: Add vdd_logic to rk3288-veyron + +The vdd_logic rail controls the voltage supplied to misc logic on +rk3288, including the voltage supplied to the memory controller. The +vcc logic is implemented by a PWM regulator. + +Right now there are no consumers of vdd_logic on veyron but if anyone +ever wants to try to add DDR Freq they'd need it. + +Note that in the downstream Chrome OS kernel the PWM regulator has +a voltage table with these points: + 1350000 0% + 1300000 10% + 1250000 20% + 1200000 31% + 1150000 41% + 1125000 46% + 1100000 52% + 1050000 62% + 1000000 72% + 950000 83% + +The DDR Freq driver in the downstream kernel only uses some of those +points, namely: + DDR3: 1200000, 1150000, 1100000, 1050000 + LPDDR: 1150000, 1100000, 1050000 + +When adapting the downstream kernel to upstream I have opted to switch +to using the "continuous" mode of the PWM regulator driver. This was +the only way I could get the upstream driver to achieve _exactly_ the +same voltages as the downstream driver could. Specifically note that +the old driver in downstream Chrome OS 3.14 _didn't_ have the +DIV_ROUND_CLOSEST_ULL() in the Rockchip PLL driver. That means if I +use the same (downstream) table I might end up with a duty cycle +that's 1 larger than was used downstream, leading to a slightly +different voltage. Due to the way the rounding worked I couldn't even +just adjust the "percent" by 1 for a given voltage level--certain duty +cycles just aren't achievable with the upstream math for voltage +tables. + +Using continuous mode you can achieve the exact same duty cycle by +simply adjusting the voltage you use by a tad bit. The voltages that +are equivalent to the ones used in the downstream kernel's table are: + 1350000, 1304472, 1255691, 1200407, 1154878, + 1128862, 1099593, 1050813, 1005285, 950000 + +Note that the top/bottom voltage is exactly the same just due to the +way that continuous mode is calculated and the fact that I used those +as anchors. I didn't make any attempt to do the resistor math (as was +done on rk3399-gru). + +If anyone ever gets DDRFreq working on veyron upstream they should +thus adjust the voltage specified in the DDRFreq operating points +slightly (as per the above) to obtain the existing/tested values. AKA +you'd use: + DDR3: 1200407, 1154878, 1099593, 1050813 + LPDDR: 1154878, 1099593, 1050813 + +A few other notes: +- The "period" here (1994) is different than the "period" downstream + (2000) for similar reasons: there's a DIV_ROUND_CLOSEST_ULL() that + wasn't downstream. With 1994 upstream comes up with the same value + (0x94) to program into the hardware that downstream put there. As + far as I can tell 0x94 actually means 1993.27. +- The duty cycle unit of 0x94 was picked by just matching the period + which nicely allows us to insert 0x7b as that value to program into + the hardware for 950mV. The 0x7b was found by observing what the + downstream kernel calculated (not that the system can actually run + with vdd_log at 950 mV). +- The downstream kernel can also be seen to program a different value + into the CTRL field. Upstream achieves 0x0b and downstream 0x1b. + This is because the upstream commit bc834d7b07b4 ("pwm: rockchip: + Move the configuration of polarity") fixed a bug by adding "ctrl &= + ~PWM_POLARITY_MASK". Downstream accidentally left bit 4 set. + Luckily this bit doesn't matter--it's only used when the PWM goes + inactive (AKA if it's in oneshot mode or is disabled) and we don't + do that for the PWM regulator. + +I measured the voltage of vdd_log while adjusting it and found that +with the upstream kernel voltage difference between requested and +actual was 9.2 mV at 950 mV and 13.4 mV at 1350 mV with in-between +voltages consistently showing ~1% error. This error is likely +expected as voltage can be seen to sag a bit when more load is put on +the rail. + +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 0bc2409f6903..5181d9435fda 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -95,6 +95,23 @@ + regulator-boot-on; + vin-supply = <&vcc_5v>; + }; ++ ++ vdd_logic: vdd-logic { ++ compatible = "pwm-regulator"; ++ regulator-name = "vdd_logic"; ++ ++ pwms = <&pwm1 0 1994 0>; ++ pwm-supply = <&vcc33_sys>; ++ ++ pwm-dutycycle-range = <0x7b 0>; ++ pwm-dutycycle-unit = <0x94>; ++ ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <4000>; ++ }; + }; + + &cpu0 { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0016-ARM-dts-rockchip-Remove-address-size-cells-from-rk32.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0016-ARM-dts-rockchip-Remove-address-size-cells-from-rk32.patch new file mode 100644 index 0000000..8c13856 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0016-ARM-dts-rockchip-Remove-address-size-cells-from-rk32.patch @@ -0,0 +1,36 @@ +From 282e2e078ba5338c72150477b743794bc7523917 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 20 Mar 2019 13:14:01 -0700 +Subject: [PATCH 16/54] ARM: dts: rockchip: Remove #address/#size-cells from + rk3288 mipi_dsi + +They are pointless. As dtc points out: + Warning (avoid_unnecessary_addr_size): + /mipi@ff960000: + unnecessary #address-cells/#size-cells without "ranges" or child "reg" property + +Let's remove them. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index df0c5456c94f..a024d1e7e74c 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1119,8 +1119,6 @@ + clock-names = "ref", "pclk"; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; +- #address-cells = <1>; +- #size-cells = <0>; + status = "disabled"; + + ports { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0017-ARM-dts-rockchip-Remove-address-size-cells-from-rk32.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0017-ARM-dts-rockchip-Remove-address-size-cells-from-rk32.patch new file mode 100644 index 0000000..29f4d09 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0017-ARM-dts-rockchip-Remove-address-size-cells-from-rk32.patch @@ -0,0 +1,36 @@ +From 1a96665143c355b1019ed13b927266185d2a1e4f Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 20 Mar 2019 13:14:02 -0700 +Subject: [PATCH 17/54] ARM: dts: rockchip: Remove #address/#size-cells from + rk3288-veyron gpio-keys + +They are pointless. As dtc points out: + Warning (avoid_unnecessary_addr_size): + /gpio-keys: + unnecessary #address-cells/#size-cells without "ranges" or child "reg" property + +Let's remove them. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 0bc2409f6903..192dbc089ade 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -25,8 +25,6 @@ + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; +- #address-cells = <1>; +- #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0018-ARM-dts-rockchip-Add-device-tree-for-rk3288-veyron-m.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0018-ARM-dts-rockchip-Add-device-tree-for-rk3288-veyron-m.patch new file mode 100644 index 0000000..dabdd02 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0018-ARM-dts-rockchip-Add-device-tree-for-rk3288-veyron-m.patch @@ -0,0 +1,65 @@ +From 01b2a2d52169372d73ec3639620b2b3255d5eb53 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Mon, 25 Mar 2019 09:20:05 -0700 +Subject: [PATCH 18/54] ARM: dts: rockchip: Add device tree for + rk3288-veyron-mighty + +Mighty is basically the same Chromebook as Jaq but it has a full-sized +SD slot and some different (slightly more rugged) plastics around it. +Like Jaq, Mighty may show up with various different brandings but all +of them have the same board inside. + +In the downstream kernel Mighty and Jaq share a "dtsi" and Mighty just +adds the SD write protect (needed for a full-sized SD slot). We'll do +this upstream by just including the Jaq dts and make the changes. + +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-mighty.dts | 34 ++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + create mode 100644 arch/arm/boot/dts/rk3288-veyron-mighty.dts + +diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts +new file mode 100644 +index 000000000000..f640857cbdae +--- /dev/null ++++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts +@@ -0,0 +1,34 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Google Veyron Mighty Rev 1+ board device tree source ++ * ++ * Copyright 2015 Google, Inc ++ */ ++ ++/dts-v1/; ++ ++#include "rk3288-veyron-jaq.dts" ++ ++/ { ++ model = "Google Mighty"; ++ compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4", ++ "google,veyron-mighty-rev3", "google,veyron-mighty-rev2", ++ "google,veyron-mighty-rev1", "google,veyron-mighty", ++ "google,veyron", "rockchip,rk3288"; ++}; ++ ++&sdmmc { ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio ++ &sdmmc_wp_gpio &sdmmc_bus4>; ++ wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; ++ ++ /delete-property/ disable-wp; ++}; ++ ++&pinctrl { ++ sdmmc { ++ sdmmc_wp_gpio: sdmmc-wp-gpio { ++ rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0019-ARM-dts-rockchip-Remove-unnecessary-setting-of-UART0.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0019-ARM-dts-rockchip-Remove-unnecessary-setting-of-UART0.patch new file mode 100644 index 0000000..eb18d40 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0019-ARM-dts-rockchip-Remove-unnecessary-setting-of-UART0.patch @@ -0,0 +1,40 @@ +From 2f60eb2f03b9c3d0a31592c55a88ef62b1403b5d Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Wed, 10 Apr 2019 11:30:10 -0700 +Subject: [PATCH 19/54] ARM: dts: rockchip: Remove unnecessary setting of UART0 + SCLK rate on veyron + +Some veyron devices have a Bluetooth controller connected on UART0. +The UART needs to operate at a high speed, however setting the clock +rate at initialization has no practical effect. During initialization +user space adjusts the UART baudrate multiple times, which ends up +changing the SCLK rate. After a successful initiatalization the clk +is running at the desired speed (48MHz). + +Remove the unnecessary clock rate configuration from the DT. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 5181d9435fda..fa38eb967f12 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -395,10 +395,6 @@ + &uart0 { + status = "okay"; + +- /* We need to go faster than 24MHz, so adjust clock parents / rates */ +- assigned-clocks = <&cru SCLK_UART0>; +- assigned-clock-rates = <48000000>; +- + /* Pins don't include flow control by default; add that in */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0020-ARM-dts-rockchip-Add-BT_EN-to-the-power-sequence-for.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0020-ARM-dts-rockchip-Add-BT_EN-to-the-power-sequence-for.patch new file mode 100644 index 0000000..56ec594 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0020-ARM-dts-rockchip-Add-BT_EN-to-the-power-sequence-for.patch @@ -0,0 +1,50 @@ +From 280fa349757bb240c650882feee5a861150ccc2d Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Tue, 9 Apr 2019 16:14:05 -0700 +Subject: [PATCH 20/54] ARM: dts: rockchip: Add BT_EN to the power sequence for + veyron + +Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the +Bluetooth/WiFi module. On devices with a Broadcom module the signal +needs to be asserted to use Bluetooth. + +Note that BT_ENABLE_L is a misnomer in the schematics, the signal +actually is active-high. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index fa38eb967f12..efa7b425c9ed 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -62,12 +62,19 @@ + pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; + + /* +- * On the module itself this is one of these (depending +- * on the actual card populated): ++ * Depending on the actual card populated GPIO4 D4 and D5 ++ * correspond to one of these signals on the module: ++ * ++ * D4: + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) ++ * ++ * D5: ++ * - BT_I2S_WS_BT_RFDISABLE_L ++ * - No connect + */ +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; ++ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, ++ <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + vcc_5v: vcc-5v { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0021-ARM-dts-rockchip-bulk-convert-gpios-to-their-constan.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0021-ARM-dts-rockchip-bulk-convert-gpios-to-their-constan.patch new file mode 100644 index 0000000..d977045 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0021-ARM-dts-rockchip-bulk-convert-gpios-to-their-constan.patch @@ -0,0 +1,2425 @@ +From 07f08d9cee459b4d91d79becb7628c7ddeea0a59 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 2 Apr 2019 14:08:57 +0200 +Subject: [PATCH 21/54] ARM: dts: rockchip: bulk convert gpios to their + constant counterparts + +Rockchip SoCs use 2 different numbering schemes. Where the gpio- +controllers just count 0-31 for their 32 gpios, the underlying +iomux controller splits these into 4 separate entities A-D. + +Device-schematics always use these iomux-values to identify pins, +so to make mapping schematics to devicetree easier Andy Yan introduced +named constants for the pins but so far we only used them on new +additions. + +Using a sed-script created by Emil Renner Berthing bulk-convert +the remaining raw gpio numbers into their descriptive counterparts +and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x +mappings: + +/rockchip,pins *=/bcheck +b # to end of script +:append-next-line +N +:check +/^[^;]*$/bappend-next-line +s/ +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk322x.dtsi | 170 ++++++------- + arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 +- + arch/arm/boot/dts/rk3288-evb.dtsi | 26 +- + arch/arm/boot/dts/rk3288-fennec.dts | 10 +- + arch/arm/boot/dts/rk3288-firefly-beta.dts | 4 +- + arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 10 +- + arch/arm/boot/dts/rk3288-firefly-reload.dts | 36 +-- + arch/arm/boot/dts/rk3288-firefly.dts | 4 +- + arch/arm/boot/dts/rk3288-firefly.dtsi | 38 +-- + arch/arm/boot/dts/rk3288-miqi.dts | 28 +-- + arch/arm/boot/dts/rk3288-phycore-rdk.dts | 28 +-- + arch/arm/boot/dts/rk3288-phycore-som.dtsi | 30 +-- + arch/arm/boot/dts/rk3288-r89.dts | 14 +- + arch/arm/boot/dts/rk3288-rock2-som.dtsi | 4 +- + arch/arm/boot/dts/rk3288-rock2-square.dts | 18 +- + arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 8 +- + arch/arm/boot/dts/rk3288-veyron-brain.dts | 8 +- + arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 18 +- + arch/arm/boot/dts/rk3288-veyron-jaq.dts | 14 +- + arch/arm/boot/dts/rk3288-veyron-jerry.dts | 14 +- + arch/arm/boot/dts/rk3288-veyron-mickey.dts | 6 +- + arch/arm/boot/dts/rk3288-veyron-mighty.dts | 2 +- + arch/arm/boot/dts/rk3288-veyron-minnie.dts | 24 +- + arch/arm/boot/dts/rk3288-veyron-pinky.dts | 6 +- + arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 16 +- + arch/arm/boot/dts/rk3288-veyron-speedy.dts | 14 +- + arch/arm/boot/dts/rk3288-veyron.dtsi | 50 ++-- + arch/arm/boot/dts/rk3288-vyasa.dts | 6 +- + arch/arm/boot/dts/rk3288.dtsi | 286 +++++++++++----------- + 30 files changed, 463 insertions(+), 463 deletions(-) + +diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi +index 29f19076dceb..da102fff96a2 100644 +--- a/arch/arm/boot/dts/rk322x.dtsi ++++ b/arch/arm/boot/dts/rk322x.dtsi +@@ -865,228 +865,228 @@ + + emmc { + emmc_clk: emmc-clk { +- rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { +- rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { +- rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, +- <1 25 RK_FUNC_2 &pcfg_pull_none>, +- <1 26 RK_FUNC_2 &pcfg_pull_none>, +- <1 27 RK_FUNC_2 &pcfg_pull_none>, +- <1 28 RK_FUNC_2 &pcfg_pull_none>, +- <1 29 RK_FUNC_2 &pcfg_pull_none>, +- <1 30 RK_FUNC_2 &pcfg_pull_none>, +- <1 31 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, ++ <1 RK_PD1 2 &pcfg_pull_none>, ++ <1 RK_PD2 2 &pcfg_pull_none>, ++ <1 RK_PD3 2 &pcfg_pull_none>, ++ <1 RK_PD4 2 &pcfg_pull_none>, ++ <1 RK_PD5 2 &pcfg_pull_none>, ++ <1 RK_PD6 2 &pcfg_pull_none>, ++ <1 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { +- rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, +- <2 12 RK_FUNC_1 &pcfg_pull_none>, +- <2 25 RK_FUNC_1 &pcfg_pull_none>, +- <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 17 RK_FUNC_1 &pcfg_pull_none>, +- <2 16 RK_FUNC_1 &pcfg_pull_none>, +- <2 21 RK_FUNC_2 &pcfg_pull_none>, +- <2 20 RK_FUNC_2 &pcfg_pull_none>, +- <2 11 RK_FUNC_1 &pcfg_pull_none>, +- <2 8 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, ++ <2 RK_PB4 1 &pcfg_pull_none>, ++ <2 RK_PD1 1 &pcfg_pull_none>, ++ <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PC1 1 &pcfg_pull_none>, ++ <2 RK_PC0 1 &pcfg_pull_none>, ++ <2 RK_PC5 2 &pcfg_pull_none>, ++ <2 RK_PC4 2 &pcfg_pull_none>, ++ <2 RK_PB3 1 &pcfg_pull_none>, ++ <2 RK_PB0 1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { +- rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, +- <2 12 RK_FUNC_1 &pcfg_pull_none>, +- <2 25 RK_FUNC_1 &pcfg_pull_none>, +- <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, +- <2 17 RK_FUNC_1 &pcfg_pull_none>, +- <2 16 RK_FUNC_1 &pcfg_pull_none>, +- <2 8 RK_FUNC_1 &pcfg_pull_none>, +- <2 15 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, ++ <2 RK_PB4 1 &pcfg_pull_none>, ++ <2 RK_PD1 1 &pcfg_pull_none>, ++ <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, ++ <2 RK_PC1 1 &pcfg_pull_none>, ++ <2 RK_PC0 1 &pcfg_pull_none>, ++ <2 RK_PB0 1 &pcfg_pull_none>, ++ <2 RK_PB7 1 &pcfg_pull_none>; + }; + + phy_pins: phy-pins { +- rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, +- <2 8 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, ++ <2 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, +- <0 1 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, ++ <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { +- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, +- <0 3 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, ++ <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { +- rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, +- <2 21 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, ++ <2 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { +- rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, +- <0 7 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, ++ <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + spi-0 { + spi0_clk: spi0-clk { +- rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { +- rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { +- rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { +- rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { +- rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; + }; + }; + + spi-1 { + spi1_clk: spi1-clk { +- rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { +- rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { +- rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { +- rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { +- rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { +- rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, +- <0 9 RK_FUNC_1 &pcfg_pull_none>, +- <0 11 RK_FUNC_1 &pcfg_pull_none>, +- <0 12 RK_FUNC_1 &pcfg_pull_none>, +- <0 13 RK_FUNC_1 &pcfg_pull_none>, +- <0 14 RK_FUNC_1 &pcfg_pull_none>, +- <1 2 RK_FUNC_2 &pcfg_pull_none>, +- <1 4 RK_FUNC_2 &pcfg_pull_none>, +- <1 5 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, ++ <0 RK_PB1 1 &pcfg_pull_none>, ++ <0 RK_PB3 1 &pcfg_pull_none>, ++ <0 RK_PB4 1 &pcfg_pull_none>, ++ <0 RK_PB5 1 &pcfg_pull_none>, ++ <0 RK_PB6 1 &pcfg_pull_none>, ++ <1 RK_PA2 2 &pcfg_pull_none>, ++ <1 RK_PA4 2 &pcfg_pull_none>, ++ <1 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { +- rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { +- rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { +- rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { +- rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { +- rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { +- rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { +- rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { +- rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, +- <2 27 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, ++ <2 RK_PD3 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { +- rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { +- rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { +- rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, +- <1 10 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, ++ <1 RK_PB2 1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { +- rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { +- rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { +- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, +- <1 19 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, ++ <1 RK_PC3 2 &pcfg_pull_none>; + }; + + uart21_xfer: uart21-xfer { +- rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, +- <1 9 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, ++ <1 RK_PB1 2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { +- rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { +- rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts +index 6592c809e2a5..80080767c365 100644 +--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts ++++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts +@@ -175,13 +175,13 @@ + &pinctrl { + lcd { + lcd_en: lcd-en { +- rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_pwr: wifi-pwr { +- rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi +index 97e4d552ff0f..820440715302 100644 +--- a/arch/arm/boot/dts/rk3288-evb.dtsi ++++ b/arch/arm/boot/dts/rk3288-evb.dtsi +@@ -314,25 +314,25 @@ + + backlight { + bl_en: bl-en { +- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_cs: lcd-cs { +- rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +@@ -342,34 +342,34 @@ + * high-speed mode on EVB board so bump up to 8ma. + */ + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, +- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, +- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, +- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, ++ <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, ++ <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, ++ <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_pwr: eth-phy-pwr { +- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts +index 29af26e6d442..4847cf902a15 100644 +--- a/arch/arm/boot/dts/rk3288-fennec.dts ++++ b/arch/arm/boot/dts/rk3288-fennec.dts +@@ -278,27 +278,27 @@ + + gmac { + phy_int: phy-int { +- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { +- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { +- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usbphy { + host_drv: host-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rk3288-firefly-beta.dts +index 0f3c29d7fbab..135e8832141f 100644 +--- a/arch/arm/boot/dts/rk3288-firefly-beta.dts ++++ b/arch/arm/boot/dts/rk3288-firefly-beta.dts +@@ -18,13 +18,13 @@ + &pinctrl { + act8846 { + pmic_vsel: pmic-vsel { +- rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + ir { + ir_int: ir-int { +- rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +index f57f286a93c3..61435d8ee37b 100644 +--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi ++++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +@@ -224,25 +224,25 @@ + + act8846 { + pwr_hold: pwr-hold { +- rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + pmic_vsel: pmic-vsel { +- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { +- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { +- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { +- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts +index 3a646c5f4fcf..1574383fd2dc 100644 +--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts ++++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts +@@ -306,39 +306,39 @@ + &pinctrl { + ir { + ir_int: ir-int { +- rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { +- rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif_pwr: cif-pwr { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { +- rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + power_led: power-led { +- rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { +- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +@@ -348,44 +348,44 @@ + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { +- rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbhub_rst: usbhub-rst { +- rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rk3288-firefly.dts +index 556ab42dd81c..313459dab2e4 100644 +--- a/arch/arm/boot/dts/rk3288-firefly.dts ++++ b/arch/arm/boot/dts/rk3288-firefly.dts +@@ -18,13 +18,13 @@ + &pinctrl { + act8846 { + pmic_vsel: pmic-vsel { +- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + ir { + ir_int: ir-int { +- rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi +index a6ff7eac4aa8..5e0a19004e46 100644 +--- a/arch/arm/boot/dts/rk3288-firefly.dtsi ++++ b/arch/arm/boot/dts/rk3288-firefly.dtsi +@@ -392,49 +392,49 @@ + + act8846 { + pwr_hold: pwr-hold { +- rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { +- rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_int: phy-int { +- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { +- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { +- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hym8563 { + rtc_int: rtc-int { +- rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + power_led: power-led { +- rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { +- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +@@ -444,38 +444,38 @@ + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbhub_rst: usbhub-rst { +- rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts +index fb7365b604bb..c41d012c8850 100644 +--- a/arch/arm/boot/dts/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rk3288-miqi.dts +@@ -296,29 +296,29 @@ + + act8846 { + pmic_int: pmic-int { +- rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { +- rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_vsel: pmic-vsel { +- rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { +- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { +- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { +- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + +@@ -328,28 +328,28 @@ + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts +index 7077c3403483..1e33859de484 100644 +--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts ++++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts +@@ -160,15 +160,15 @@ + buttons { + user_button_pins: user-button-pins { + /* button 1 */ +- rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>, ++ rockchip,pins = <8 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* button 2 */ +- <8 0 RK_FUNC_GPIO &pcfg_pull_up>; ++ <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rv4162 { + i2c_rtc_int: i2c-rtc-int { +- rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +@@ -178,44 +178,44 @@ + * high-speed mode on pcm-947 board so bump up to 12 mA. + */ + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, +- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, ++ <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + ts_irq_pin: ts-irq-pin { +- rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host0_vbus_drv: host0-vbus-drv { +- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host1_vbus_drv: host1-vbus-drv { +- rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi +index c218dd54c9b5..77a47b9b756d 100644 +--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi ++++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi +@@ -342,49 +342,49 @@ + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { +- rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; ++ rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { +- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; ++ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_12ma>; + }; + + emmc_bus8: emmc-bus8 { +- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, +- <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; ++ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA1 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA2 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA3 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA4 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA5 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA6 2 &pcfg_pull_none_12ma>, ++ <3 RK_PA7 2 &pcfg_pull_none_12ma>; + }; + }; + + gmac { + phy_int: phy-int { +- rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { +- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + leds { + user_led: user-led { +- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* Pin for switching state between sleep and non-sleep state */ + pmic_sleep: pmic-sleep { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts +index 28972fb4e221..a6ffc381abaa 100644 +--- a/arch/arm/boot/dts/rk3288-r89.dts ++++ b/arch/arm/boot/dts/rk3288-r89.dts +@@ -265,39 +265,39 @@ + + act8846 { + pmic_vsel: pmic-vsel { +- rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pwr_hold: pwr-hold { +- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + buttons { + pwrbtn: pwrbtn { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_int: ir-int { +- rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi +index 32e1ab336662..9f9e2bfd1295 100644 +--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi ++++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi +@@ -231,13 +231,13 @@ + + emmc { + emmc_reset: emmc-reset { +- rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_rst: phy-rst { +- rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts +index 5b7e1c9e92e1..cdcdc921ee09 100644 +--- a/arch/arm/boot/dts/rk3288-rock2-square.dts ++++ b/arch/arm/boot/dts/rk3288-rock2-square.dts +@@ -204,53 +204,53 @@ + &pinctrl { + ir { + ir_int: ir-int { +- rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { +- rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { +- rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + phone_ctl: phone-ctl { +- rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { +- rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + sata_pwr_en: sata-pwr-en { +- rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { +- rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +index eaf921694e68..445270aa136e 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi +@@ -73,7 +73,7 @@ + &pinctrl { + codec { + hp_det: hp-det { +- rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* +@@ -82,17 +82,17 @@ + * we've got a ts3a227e chip but the driver requires it. + */ + int_codec: int-codec { +- rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + mic_det: mic-det { +- rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headset { + ts3a227e_int_l: ts3a227e-int-l { +- rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts +index 5c94a33d695d..406146cbff29 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-brain.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts +@@ -42,23 +42,23 @@ + &pinctrl { + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { +- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb-host { + usb2_pwr_en: usb2-pwr-en { +- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +index b54746df3661..72c4754032e9 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +@@ -244,51 +244,51 @@ + + backlight { + bl_en: bl-en { +- rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + ap_lid_int_l: ap-lid-int-l { +- rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + charger { + ac_present_ap: ac-present-ap { +- rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + cros-ec { + ec_int: ec-int { +- rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + suspend { + suspend_l_wake: suspend-l-wake { +- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>; ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + suspend_l_sleep: suspend-l-sleep { +- rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>; ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + trackpad { + trackpad_int: trackpad-int { +- rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-host { + host1_pwr_en: host1-pwr-en { +- rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbotg_pwren_h: usbotg-pwren-h { +- rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts +index 9d6814c7f285..e248f55ee8d2 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts +@@ -138,39 +138,39 @@ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { +- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { +- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { +- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { +- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +index 3e8f700a0d64..b1613af83d5d 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +@@ -106,39 +106,39 @@ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { +- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { +- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { +- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { +- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +index d889ab3c8235..e852594417b5 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +@@ -186,17 +186,17 @@ + &pinctrl { + hdmi { + power_hdmi_on: power-hdmi-on { +- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { +- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts +index f640857cbdae..27fbc07476d2 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts +@@ -28,7 +28,7 @@ + &pinctrl { + sdmmc { + sdmmc_wp_gpio: sdmmc-wp-gpio { +- rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +index f95d0c5fcf71..468a1818545d 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +@@ -191,65 +191,65 @@ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { +- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + volum_down_l: volum-down-l { +- rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + volum_up_l: volum-up-l { +- rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { +- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { +- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { +- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + prochot { + gpio_prochot: gpio-prochot { +- rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { +- rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { +- rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts +index 2950aadf49f0..9645be7b3d8c 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts +@@ -55,19 +55,19 @@ + &pinctrl { + buttons { + pwr_key_h: pwr-key-h { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_reset: emmc-reset { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_wp_gpio: sdmmc-wp-gpio { +- rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +index a4570444cc79..fe950f9863e8 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +@@ -16,18 +16,18 @@ + * We also have external pulls, so disable the internal ones. + */ + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, +- <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, +- <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, +- <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>, ++ <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>, ++ <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>, ++ <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>; + }; + + /* +@@ -37,12 +37,12 @@ + * think there's a card inserted + */ + sdmmc_cd_disabled: sdmmc-cd-disabled { +- rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* This is where we actually hook up CD */ + sdmmc_cd_gpio: sdmmc-cd-gpio { +- rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +index e16421d80d22..2ac8748a3a0c 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +@@ -104,39 +104,39 @@ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +- rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { +- rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { +- rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { +- rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { +- rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { +- rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { +- rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index efa7b425c9ed..e4f0c00011f2 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -480,13 +480,13 @@ + + buttons { + pwr_key_l: pwr-key-l { +- rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + emmc { + emmc_reset: emmc-reset { +- rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* +@@ -494,51 +494,51 @@ + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { +- rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { +- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc_bus8: emmc-bus8 { +- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, +- <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>, ++ <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + reboot { + ap_warm_reset_h: ap-warm-reset-h { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + recovery-switch { + rec_mode_l: rec-mode-l { +- rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio0 { + wifi_enable_h: wifienable-h { +- rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* NOTE: mislabelled on schematic; should be bt_enable_h */ + bt_enable_l: bt-enable-l { +- rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* +@@ -546,30 +546,30 @@ + * We also have external pulls, so disable the internal ones. + */ + sdio0_bus4: sdio0-bus4 { +- rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, +- <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, +- <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, +- <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>, ++ <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>, ++ <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>, ++ <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>; + }; + + sdio0_cmd: sdio0-cmd { +- rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>; + }; + + sdio0_clk: sdio0-clk { +- rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; ++ rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; + }; + }; + + tpm { + tpm_int_h: tpm-int-h { +- rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + write-protect { + fw_wp_ap: fw-wp-ap { +- rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts +index 40b232eb5011..ba06e9f97ddc 100644 +--- a/arch/arm/boot/dts/rk3288-vyasa.dts ++++ b/arch/arm/boot/dts/rk3288-vyasa.dts +@@ -448,13 +448,13 @@ + + pmic { + pmic_int: pmic-int { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb_host { + phy_pwr_en: phy-pwr-en { +- rockchip,pins = ; ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + usb2_pwr_en: usb2-pwr-en { +@@ -464,7 +464,7 @@ + + usb_otg { + otg_vbus_drv: otg-vbus-drv { +- rockchip,pins = ; ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + }; +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 743a7d85daf7..23e9c5253019 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1532,16 +1532,16 @@ + + hdmi { + hdmi_cec_c0: hdmi-cec-c0 { +- rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; + }; + + hdmi_cec_c7: hdmi-cec-c7 { +- rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; + }; + + hdmi_ddc: hdmi-ddc { +- rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, +- <7 20 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, ++ <7 RK_PC4 2 &pcfg_pull_none>; + }; + }; + +@@ -1564,421 +1564,421 @@ + + sleep { + global_pwroff: global-pwroff { +- rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; + }; + + ddrio_pwroff: ddrio-pwroff { +- rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; + }; + + ddr0_retention: ddr0-retention { +- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; + }; + + ddr1_retention: ddr1-retention { +- rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; + }; + }; + + edp { + edp_hpd: edp-hpd { +- rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; ++ rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { +- rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, +- <0 16 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, ++ <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { +- rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, +- <8 5 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, ++ <8 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { +- rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, +- <6 10 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, ++ <6 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { +- rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, +- <2 17 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, ++ <2 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { +- rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, +- <7 18 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, ++ <7 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { +- rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, +- <7 20 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, ++ <7 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { +- rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, +- <6 1 RK_FUNC_1 &pcfg_pull_none>, +- <6 2 RK_FUNC_1 &pcfg_pull_none>, +- <6 3 RK_FUNC_1 &pcfg_pull_none>, +- <6 4 RK_FUNC_1 &pcfg_pull_none>, +- <6 8 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, ++ <6 RK_PA1 1 &pcfg_pull_none>, ++ <6 RK_PA2 1 &pcfg_pull_none>, ++ <6 RK_PA3 1 &pcfg_pull_none>, ++ <6 RK_PA4 1 &pcfg_pull_none>, ++ <6 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + lcdc { + lcdc_ctl: lcdc-ctl { +- rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, +- <1 25 RK_FUNC_1 &pcfg_pull_none>, +- <1 26 RK_FUNC_1 &pcfg_pull_none>, +- <1 27 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, ++ <1 RK_PD1 1 &pcfg_pull_none>, ++ <1 RK_PD2 1 &pcfg_pull_none>, ++ <1 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { +- rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { +- rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmmc-cd { +- rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; + }; + + sdmmc_bus1: sdmmc-bus1 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { +- rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, +- <6 17 RK_FUNC_1 &pcfg_pull_up>, +- <6 18 RK_FUNC_1 &pcfg_pull_up>, +- <6 19 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, ++ <6 RK_PC1 1 &pcfg_pull_up>, ++ <6 RK_PC2 1 &pcfg_pull_up>, ++ <6 RK_PC3 1 &pcfg_pull_up>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { +- rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { +- rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, +- <4 21 RK_FUNC_1 &pcfg_pull_up>, +- <4 22 RK_FUNC_1 &pcfg_pull_up>, +- <4 23 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, ++ <4 RK_PC5 1 &pcfg_pull_up>, ++ <4 RK_PC6 1 &pcfg_pull_up>, ++ <4 RK_PC7 1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { +- rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { +- rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { +- rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { +- rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { +- rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { +- rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { +- rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; + }; + }; + + sdio1 { + sdio1_bus1: sdio1-bus1 { +- rockchip,pins = <3 24 4 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; + }; + + sdio1_bus4: sdio1-bus4 { +- rockchip,pins = <3 24 4 &pcfg_pull_up>, +- <3 25 4 &pcfg_pull_up>, +- <3 26 4 &pcfg_pull_up>, +- <3 27 4 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, ++ <3 RK_PD1 4 &pcfg_pull_up>, ++ <3 RK_PD2 4 &pcfg_pull_up>, ++ <3 RK_PD3 4 &pcfg_pull_up>; + }; + + sdio1_cd: sdio1-cd { +- rockchip,pins = <3 28 4 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; + }; + + sdio1_wp: sdio1-wp { +- rockchip,pins = <3 29 4 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; + }; + + sdio1_bkpwr: sdio1-bkpwr { +- rockchip,pins = <3 30 4 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; + }; + + sdio1_int: sdio1-int { +- rockchip,pins = <3 31 4 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; + }; + + sdio1_cmd: sdio1-cmd { +- rockchip,pins = <4 6 4 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; + }; + + sdio1_clk: sdio1-clk { +- rockchip,pins = <4 7 4 &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; + }; + + sdio1_pwr: sdio1-pwr { +- rockchip,pins = <4 9 4 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; + }; + }; + + emmc { + emmc_clk: emmc-clk { +- rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; ++ rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { +- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; + }; + + emmc_pwr: emmc-pwr { +- rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; + }; + + emmc_bus1: emmc-bus1 { +- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; + }; + + emmc_bus4: emmc-bus4 { +- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, +- <3 1 RK_FUNC_2 &pcfg_pull_up>, +- <3 2 RK_FUNC_2 &pcfg_pull_up>, +- <3 3 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, ++ <3 RK_PA1 2 &pcfg_pull_up>, ++ <3 RK_PA2 2 &pcfg_pull_up>, ++ <3 RK_PA3 2 &pcfg_pull_up>; + }; + + emmc_bus8: emmc-bus8 { +- rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, +- <3 1 RK_FUNC_2 &pcfg_pull_up>, +- <3 2 RK_FUNC_2 &pcfg_pull_up>, +- <3 3 RK_FUNC_2 &pcfg_pull_up>, +- <3 4 RK_FUNC_2 &pcfg_pull_up>, +- <3 5 RK_FUNC_2 &pcfg_pull_up>, +- <3 6 RK_FUNC_2 &pcfg_pull_up>, +- <3 7 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, ++ <3 RK_PA1 2 &pcfg_pull_up>, ++ <3 RK_PA2 2 &pcfg_pull_up>, ++ <3 RK_PA3 2 &pcfg_pull_up>, ++ <3 RK_PA4 2 &pcfg_pull_up>, ++ <3 RK_PA5 2 &pcfg_pull_up>, ++ <3 RK_PA6 2 &pcfg_pull_up>, ++ <3 RK_PA7 2 &pcfg_pull_up>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { +- rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { +- rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { +- rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { +- rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { +- rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; + }; + }; + spi1 { + spi1_clk: spi1-clk { +- rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { +- rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { +- rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { +- rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_cs1: spi2-cs1 { +- rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; + }; + spi2_clk: spi2-clk { +- rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { +- rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { +- rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { +- rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { +- rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, +- <4 17 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, ++ <4 RK_PC1 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { +- rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; + }; + + uart0_rts: uart0-rts { +- rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { +- rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, +- <5 9 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, ++ <5 RK_PB1 1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { +- rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; + }; + + uart1_rts: uart1-rts { +- rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { +- rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, +- <7 23 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, ++ <7 RK_PC7 1 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { +- rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, +- <7 8 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, ++ <7 RK_PB0 1 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { +- rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>; ++ rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; + }; + + uart3_rts: uart3-rts { +- rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { +- rockchip,pins = <5 15 3 &pcfg_pull_up>, +- <5 14 3 &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, ++ <5 RK_PB6 3 &pcfg_pull_none>; + }; + + uart4_cts: uart4-cts { +- rockchip,pins = <5 12 3 &pcfg_pull_up>; ++ rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; + }; + + uart4_rts: uart4-rts { +- rockchip,pins = <5 13 3 &pcfg_pull_none>; ++ rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { +- rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { +- rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { +- rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { +- rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { +- rockchip,pins = <7 22 3 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { +- rockchip,pins = <7 23 3 &pcfg_pull_none>; ++ rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { +- rockchip,pins = <3 30 3 &pcfg_pull_none>, +- <3 31 3 &pcfg_pull_none>, +- <3 26 3 &pcfg_pull_none>, +- <3 27 3 &pcfg_pull_none>, +- <3 28 3 &pcfg_pull_none_12ma>, +- <3 29 3 &pcfg_pull_none_12ma>, +- <3 24 3 &pcfg_pull_none_12ma>, +- <3 25 3 &pcfg_pull_none_12ma>, +- <4 0 3 &pcfg_pull_none>, +- <4 5 3 &pcfg_pull_none>, +- <4 6 3 &pcfg_pull_none>, +- <4 9 3 &pcfg_pull_none_12ma>, +- <4 4 3 &pcfg_pull_none_12ma>, +- <4 1 3 &pcfg_pull_none>, +- <4 3 3 &pcfg_pull_none>; ++ rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, ++ <3 RK_PD7 3 &pcfg_pull_none>, ++ <3 RK_PD2 3 &pcfg_pull_none>, ++ <3 RK_PD3 3 &pcfg_pull_none>, ++ <3 RK_PD4 3 &pcfg_pull_none_12ma>, ++ <3 RK_PD5 3 &pcfg_pull_none_12ma>, ++ <3 RK_PD0 3 &pcfg_pull_none_12ma>, ++ <3 RK_PD1 3 &pcfg_pull_none_12ma>, ++ <4 RK_PA0 3 &pcfg_pull_none>, ++ <4 RK_PA5 3 &pcfg_pull_none>, ++ <4 RK_PA6 3 &pcfg_pull_none>, ++ <4 RK_PB1 3 &pcfg_pull_none_12ma>, ++ <4 RK_PA4 3 &pcfg_pull_none_12ma>, ++ <4 RK_PA1 3 &pcfg_pull_none>, ++ <4 RK_PA3 3 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { +- rockchip,pins = <3 30 3 &pcfg_pull_none>, +- <3 31 3 &pcfg_pull_none>, +- <3 28 3 &pcfg_pull_none>, +- <3 29 3 &pcfg_pull_none>, +- <4 0 3 &pcfg_pull_none>, +- <4 5 3 &pcfg_pull_none>, +- <4 4 3 &pcfg_pull_none>, +- <4 1 3 &pcfg_pull_none>, +- <4 2 3 &pcfg_pull_none>, +- <4 3 3 &pcfg_pull_none>; ++ rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, ++ <3 RK_PD7 3 &pcfg_pull_none>, ++ <3 RK_PD4 3 &pcfg_pull_none>, ++ <3 RK_PD5 3 &pcfg_pull_none>, ++ <4 RK_PA0 3 &pcfg_pull_none>, ++ <4 RK_PA5 3 &pcfg_pull_none>, ++ <4 RK_PA4 3 &pcfg_pull_none>, ++ <4 RK_PA1 3 &pcfg_pull_none>, ++ <4 RK_PA2 3 &pcfg_pull_none>, ++ <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { +- rockchip,pins = ; ++ rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; + }; + }; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0022-ARM-dts-rockchip-Add-dynamic-power-coefficient-for-r.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0022-ARM-dts-rockchip-Add-dynamic-power-coefficient-for-r.patch new file mode 100644 index 0000000..8d08512 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0022-ARM-dts-rockchip-Add-dynamic-power-coefficient-for-r.patch @@ -0,0 +1,87 @@ +From ac60c5e33df4ec2b69c7e3ebbc0ccf1557e7bd5e Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Thu, 11 Apr 2019 17:01:58 -0700 +Subject: [PATCH 22/54] ARM: dts: rockchip: Add dynamic-power-coefficient for + rk3288 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The value was determined with the following method: + +- take CPUs 1-3 offline +- for each OPP + - set cpufreq min and max freq to OPP freq + - start dhrystone benchmark + - measure CPU power consumption during 10s + - calculate Cx for OPPx + - Cx = (Px - P1) / (Vx²fx - V1²f1) [1] + using the following units: mW / Ghz / V [2] +- C = avg(C2, ..., Cn) + +[1] see commit 4daa001a1773 ("arm64: dts: juno: Add cpu + dynamic-power-coefficient information") +[2] https://patchwork.kernel.org/patch/10493615/#22158551 + +FTR, these are the values for the different OPPs: + +freq (kHz) mV Px (mW) Cx + +126000 900 39 +216000 900 66 370 +312000 900 95 372 +408000 900 122 363 +600000 900 177 359 +696000 950 230 363 +816000 1000 297 361 +1008000 1050 404 362 +1200000 1100 528 362 +1416000 1200 770 377 +1512000 1300 984 385 +1608000 1350 1156 394 + +Signed-off-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 23e9c5253019..884957da8700 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -64,6 +64,7 @@ + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <370>; + }; + cpu1: cpu@501 { + device_type = "cpu"; +@@ -74,6 +75,7 @@ + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <370>; + }; + cpu2: cpu@502 { + device_type = "cpu"; +@@ -84,6 +86,7 @@ + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <370>; + }; + cpu3: cpu@503 { + device_type = "cpu"; +@@ -94,6 +97,7 @@ + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; ++ dynamic-power-coefficient = <370>; + }; + }; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0023-ARM-dts-rockchip-Add-DDR-retention-poweroff-to-rk328.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0023-ARM-dts-rockchip-Add-DDR-retention-poweroff-to-rk328.patch new file mode 100644 index 0000000..1ff514e --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0023-ARM-dts-rockchip-Add-DDR-retention-poweroff-to-rk328.patch @@ -0,0 +1,62 @@ +From 8a5deb4e316a5469f137e62eb1bbf6147ddbfd3d Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 11 Apr 2019 16:21:55 -0700 +Subject: [PATCH 23/54] ARM: dts: rockchip: Add DDR retention/poweroff to + rk3288-veyron hogs + +Even though upstream Linux doesn't yet go into deep enough suspend to +get DDR into self refresh, there is no harm in setting these pins up. +They'll only actually do something if we go into a deeper suspend but +leaving them configed always is fine. + +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 4 ++++ + arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++ + 2 files changed, 8 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +index 72c4754032e9..b9cc90f0f25c 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +@@ -229,6 +229,8 @@ + &pinctrl { + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ ++ &ddr0_retention ++ &ddrio_pwroff + &global_pwroff + + /* Wake only */ +@@ -236,6 +238,8 @@ + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ ++ &ddr0_retention ++ &ddrio_pwroff + &global_pwroff + + /* Sleep only */ +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index e4f0c00011f2..35755870bf66 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -453,10 +453,14 @@ + pinctrl-names = "default", "sleep"; + pinctrl-0 = < + /* Common for sleep and wake, but no owners */ ++ &ddr0_retention ++ &ddrio_pwroff + &global_pwroff + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ ++ &ddr0_retention ++ &ddrio_pwroff + &global_pwroff + >; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0024-ARM-dts-rockchip-vcc33_ccd-off-in-suspend-for-rk3288.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0024-ARM-dts-rockchip-vcc33_ccd-off-in-suspend-for-rk3288.patch new file mode 100644 index 0000000..3becfcd --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0024-ARM-dts-rockchip-vcc33_ccd-off-in-suspend-for-rk3288.patch @@ -0,0 +1,44 @@ +From ed27ae71bf610004d04cb956d0a7687342006a1f Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 11 Apr 2019 16:21:56 -0700 +Subject: [PATCH 24/54] ARM: dts: rockchip: vcc33_ccd off in suspend for + rk3288-veyron-chromebook + +As per my comments when the device tree for rk3288-veyron-chromebook +first landed: + +> Technically I think vcc33_ccd can be off since we have +> 'needs-reset-on-resume' down in the EHCI port (this regulator is for +> the USB webcam that's connected to the EHCI port). +> +> ...but leaving it on for now seems fine until we get suspend/resume +> more solid. + +It's probably about time to do it right. + +[1] https://lore.kernel.org/linux-arm-kernel/CAD=FV=U37Yx8Mqk75_x05zxonvdc3qRMhqp8TyTDPWGHqSuRqg@mail.gmail.com/ + +Signed-off-by: Douglas Anderson +Reviewed-by: Elaine Zhang +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +index b9cc90f0f25c..fbef34578100 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +@@ -176,8 +176,7 @@ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <3300000>; ++ regulator-off-in-suspend; + }; + }; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0025-ARM-dts-rockchip-vdd_gpu-off-in-suspend-for-rk3288-v.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0025-ARM-dts-rockchip-vdd_gpu-off-in-suspend-for-rk3288-v.patch new file mode 100644 index 0000000..3e7d4f3 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0025-ARM-dts-rockchip-vdd_gpu-off-in-suspend-for-rk3288-v.patch @@ -0,0 +1,41 @@ +From 356150e86d75653d1f679c6ef583144b26d0a686 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 11 Apr 2019 16:21:57 -0700 +Subject: [PATCH 25/54] ARM: dts: rockchip: vdd_gpu off in suspend for + rk3288-veyron + +At some point long long ago the downstream GPU driver would crash if +we turned the GPU off during suspend. For some context you can see: + +https://chromium-review.googlesource.com/#/c/215780/5..6/arch/arm/boot/dts/rk3288-pinky-rev2.dts + +At some point in time not too long after that got fixed. + +It's unclear why the GPU is left enabled during suspend on the +mainline kernel. Everything seems fine if I turn this off, so let's +do it. + +Signed-off-by: Douglas Anderson +Reviewed-by: Elaine Zhang +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 35755870bf66..758fe225c702 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -219,8 +219,7 @@ + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { +- regulator-on-in-suspend; +- regulator-suspend-microvolt = <1000000>; ++ regulator-off-in-suspend; + }; + }; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0026-ARM-dts-rockchip-Hook-resets-up-to-USB-PHYs-on-rk328.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0026-ARM-dts-rockchip-Hook-resets-up-to-USB-PHYs-on-rk328.patch new file mode 100644 index 0000000..032de51 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0026-ARM-dts-rockchip-Hook-resets-up-to-USB-PHYs-on-rk328.patch @@ -0,0 +1,50 @@ +From d17aa2d262e8574a8c6befb5b6470d1c32875cf8 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Tue, 16 Apr 2019 14:53:50 -0700 +Subject: [PATCH 26/54] ARM: dts: rockchip: Hook resets up to USB PHYs on + rk3288. + +Let's hook up the resets to the three USB PHYs on rk3288 as per the +bindings. This is in preparation for a future patch that will set the +"snps,reset-phy-on-wake" on the host port. + +Signed-off-by: Douglas Anderson +Signed-off-by: Felipe Balbi +--- + arch/arm/boot/dts/rk3288.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index a024d1e7e74c..3f361fad4684 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -904,6 +904,8 @@ + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; ++ resets = <&cru SRST_USBOTG_PHY>; ++ reset-names = "phy-reset"; + }; + + usbphy1: usb-phy@334 { +@@ -912,6 +914,8 @@ + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; ++ resets = <&cru SRST_USBHOST0_PHY>; ++ reset-names = "phy-reset"; + }; + + usbphy2: usb-phy@348 { +@@ -920,6 +924,8 @@ + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; ++ resets = <&cru SRST_USBHOST1_PHY>; ++ reset-names = "phy-reset"; + }; + }; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0027-ARM-dts-rockchip-Add-quirk-for-resetting-rk3288-s-dw.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0027-ARM-dts-rockchip-Add-quirk-for-resetting-rk3288-s-dw.patch new file mode 100644 index 0000000..8ff2856 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0027-ARM-dts-rockchip-Add-quirk-for-resetting-rk3288-s-dw.patch @@ -0,0 +1,32 @@ +From 5bdd614d65e314ac1530f9462c3ab955f3d3302b Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Tue, 16 Apr 2019 14:53:51 -0700 +Subject: [PATCH 27/54] ARM: dts: rockchip: Add quirk for resetting rk3288's + dwc2 host on wakeup + +The "host" USB port on rk3288 has a hardware errata where we've got to +assert a PHY reset whenever we see a remote wakeup. Add that quirk +property to the device tree. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Felipe Balbi +--- + arch/arm/boot/dts/rk3288.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 3f361fad4684..8ce3dd2264b1 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -616,6 +616,7 @@ + dr_mode = "host"; + phys = <&usbphy2>; + phy-names = "usb2-phy"; ++ snps,reset-phy-on-wake; + status = "disabled"; + }; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch new file mode 100644 index 0000000..2f9e178 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch @@ -0,0 +1,57 @@ +From 6773af2684b7bc1b7b2d9ef874599cccaba2559e Mon Sep 17 00:00:00 2001 +From: Caesar Wang +Date: Tue, 9 Apr 2019 13:47:07 -0700 +Subject: [PATCH 28/54] ARM: dts: rockchip: fix PWM clock found on RK3288 Socs + +We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect. + +Signed-off-by: Caesar Wang +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index aa017abf4f42..171231a0cd9b 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -682,7 +682,7 @@ + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; +- clocks = <&cru PCLK_PWM>; ++ clocks = <&cru PCLK_RKPWM>; + clock-names = "pwm"; + status = "disabled"; + }; +@@ -693,7 +693,7 @@ + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; +- clocks = <&cru PCLK_PWM>; ++ clocks = <&cru PCLK_RKPWM>; + clock-names = "pwm"; + status = "disabled"; + }; +@@ -704,7 +704,7 @@ + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; +- clocks = <&cru PCLK_PWM>; ++ clocks = <&cru PCLK_RKPWM>; + clock-names = "pwm"; + status = "disabled"; + }; +@@ -715,7 +715,7 @@ + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; +- clocks = <&cru PCLK_PWM>; ++ clocks = <&cru PCLK_RKPWM>; + clock-names = "pwm"; + status = "disabled"; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch new file mode 100644 index 0000000..5656c1e --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch @@ -0,0 +1,42 @@ +From d190bfaaa2a1575e7998d8487ed26cdf9e74b42b Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Fri, 3 May 2019 16:48:14 -0700 +Subject: [PATCH 29/54] ARM: dts: rockchip: Remove bogus 'i2s_clk_out' from + rk3288-veyron-mickey + +The rk3288-veyron-mickey device tree overrides the default "i2s" clock +settings to add the clock for "i2s_clk_out". + +That clock is only present in the bindings downstream Chrome OS 3.14 +tree. Upstream the i2s port bindings doesn't specify that as a +possible clock. + +Let's remove it. + +NOTE: for other rk3288-veyron devices this clock is consumed by +'maxim,max98090'. Presumably if this clock is needed for mickey it'll +need to be consumed by something similar. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-mickey.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +index e852594417b5..f9c4ece3c0d3 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +@@ -142,8 +142,6 @@ + + &i2s { + status = "okay"; +- clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; +- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; + }; + + &rk808 { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch new file mode 100644 index 0000000..e2bdc07 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch @@ -0,0 +1,66 @@ +From 83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Thu, 16 May 2019 09:29:40 -0700 +Subject: [PATCH 32/54] ARM: dts: rockchip: raise CPU trip point temperature + for veyron to 100 degC +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This value matches what is used by the downstream Chrome OS 3.14 +kernel, the 'official' kernel for veyron devices. Keep the temperature +for 'speedy' at 90°C, as in the downstream kernel. + +Increase the temperature for a hardware shutdown to 125°C, which +matches the downstream configuration and gives the system a chance +to shut down orderly at the criticial trip point. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++ + arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ + 2 files changed, 9 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +index 2ac8748a3a0c..b07a07e81551 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +@@ -64,6 +64,10 @@ + temperature = <70000>; + }; + ++&cpu_crit { ++ temperature = <90000>; ++}; ++ + &edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 1252522392c7..e81f1a0cac83 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -123,6 +123,10 @@ + cpu0-supply = <&vdd_cpu>; + }; + ++&cpu_crit { ++ temperature = <100000>; ++}; ++ + /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ + &cpu_opp_table { + /delete-node/ opp-312000000; +@@ -394,6 +398,7 @@ + + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-temp = <125000>; + }; + + &uart0 { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0033-ARM-dts-rockchip-raise-GPU-trip-point-temperatures-f.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0033-ARM-dts-rockchip-raise-GPU-trip-point-temperatures-f.patch new file mode 100644 index 0000000..650c1e8 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0033-ARM-dts-rockchip-raise-GPU-trip-point-temperatures-f.patch @@ -0,0 +1,58 @@ +From 0f637e2565d175eeff664991be9a6d0753d0e484 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Thu, 16 May 2019 09:29:41 -0700 +Subject: [PATCH 33/54] ARM: dts: rockchip: raise GPU trip point temperatures + for veyron +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The values match those used by the downstream Chrome OS 3.14 +kernel, the 'official' kernel for veyron devices. Keep the critical +trip point for speedy at 90°C as in the downstream configuration. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++ + arch/arm/boot/dts/rk3288-veyron.dtsi | 8 ++++++++ + 2 files changed, 12 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +index b07a07e81551..aae37c535444 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +@@ -75,6 +75,10 @@ + force-hpd; + }; + ++&gpu_crit { ++ temperature = <90000>; ++}; ++ + &panel { + power-supply= <&panel_regulator>; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index e81f1a0cac83..90c8312d01ff 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -166,6 +166,14 @@ + status = "okay"; + }; + ++&gpu_alert0 { ++ temperature = <72500>; ++}; ++ ++&gpu_crit { ++ temperature = <100000>; ++}; ++ + &hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0034-ARM-dts-raise-GPU-trip-point-temperature-for-speedy-.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0034-ARM-dts-raise-GPU-trip-point-temperature-for-speedy-.patch new file mode 100644 index 0000000..91ab5d7 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0034-ARM-dts-raise-GPU-trip-point-temperature-for-speedy-.patch @@ -0,0 +1,38 @@ +From fa31ba8f1719149658f3cfc1e230c04b12c72efa Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Thu, 16 May 2019 09:29:42 -0700 +Subject: [PATCH 34/54] ARM: dts: raise GPU trip point temperature for speedy + to 80 degC +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Raise the temperature of the GPU thermal trip point for speedy +to 80°C. This is the value used by the downstream Chrome OS 3.14 +kernel, the 'official' kernel for speedy. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +index aae37c535444..9a87017347ea 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +@@ -75,6 +75,10 @@ + force-hpd; + }; + ++&gpu_alert0 { ++ temperature = <80000>; ++}; ++ + &gpu_crit { + temperature = <90000>; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0035-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-min.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0035-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-min.patch new file mode 100644 index 0000000..fef0c4e --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0035-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-min.patch @@ -0,0 +1,260 @@ +From ca3516b32cd9e483685f6de5c9433d4913879f7e Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Tue, 21 May 2019 13:32:14 -0700 +Subject: [PATCH 35/54] ARM: dts: rockchip: Add pin names for + rk3288-veyron-minnie + +We can now use the "gpio-line-names" property to provide the names for +all the pins on a board. Let's use this to provide the names for all +the pins on rk3288-veyron-minnie. + +In general the names here come straight from the schematic. That +means even if the schematic name is weird / doesn't have consistent +naming conventions / has typos I still haven't made any changes. + +The exception here is for two pins: the recovery switch and the write +protect detection pin. These two pins need to have standardized names +since crossystem (a Chrome OS tool) uses these names to query the +pins. In downstream kernels crossystem used an out-of-tree driver to +do this but it has now been moved to the gpiod API and needs the +standardized names. + +It's expected that other rk3288-veyron boards will get similar patches +shortly. + +NOTE: I have sorted the "gpio" section to be next to the "pinctrl" +section since it seems to logically make the most sense there. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-minnie.dts | 212 +++++++++++++++++++++++++++++ + 1 file changed, 212 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +index ce57881625ec..a65099b4aef1 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +@@ -184,6 +184,218 @@ + pinctrl-0 = <&vcc50_hdmi_en>; + }; + ++&gpio0 { ++ gpio-line-names = "PMIC_SLEEP_AP", ++ "DDRIO_PWROFF", ++ "DDRIO_RETEN", ++ "TS3A227E_INT_L", ++ "PMIC_INT_L", ++ "PWR_KEY_L", ++ "AP_LID_INT_L", ++ "EC_IN_RW", ++ ++ "AC_PRESENT_AP", ++ /* ++ * RECOVERY_SW_L is Chrome OS ABI. Schematics call ++ * it REC_MODE_L. ++ */ ++ "RECOVERY_SW_L", ++ "OTP_OUT", ++ "HOST1_PWR_EN", ++ "USBOTG_PWREN_H", ++ "AP_WARM_RESET_H", ++ "nFALUT2", ++ "I2C0_SDA_PMIC", ++ ++ "I2C0_SCL_PMIC", ++ "SUSPEND_L", ++ "USB_INT"; ++}; ++ ++&gpio2 { ++ gpio-line-names = "CONFIG0", ++ "CONFIG1", ++ "CONFIG2", ++ "", ++ "", ++ "", ++ "", ++ "CONFIG3", ++ ++ "PROCHOT#", ++ "EMMC_RST_L", ++ "", ++ "", ++ "BL_PWR_EN", ++ "AVDD_1V8_DISP_EN", ++ "TOUCH_INT", ++ "TOUCH_RST", ++ ++ "I2C3_SCL_TP", ++ "I2C3_SDA_TP"; ++}; ++ ++&gpio3 { ++ gpio-line-names = "FLASH0_D0", ++ "FLASH0_D1", ++ "FLASH0_D2", ++ "FLASH0_D3", ++ "FLASH0_D4", ++ "FLASH0_D5", ++ "FLASH0_D6", ++ "FLASH0_D7", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "FLASH0_CS2/EMMC_CMD", ++ "", ++ "FLASH0_DQS/EMMC_CLKO"; ++}; ++ ++&gpio4 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "UART0_RXD", ++ "UART0_TXD", ++ "UART0_CTS", ++ "UART0_RTS", ++ "SDIO0_D0", ++ "SDIO0_D1", ++ "SDIO0_D2", ++ "SDIO0_D3", ++ ++ "SDIO0_CMD", ++ "SDIO0_CLK", ++ "dev_wake", ++ "", ++ "WIFI_ENABLE_H", ++ "BT_ENABLE_L", ++ "WIFI_HOST_WAKE", ++ "BT_HOST_WAKE"; ++}; ++ ++&gpio5 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "Volum_Up#", ++ "Volum_Down#", ++ "SPI0_CLK", ++ "SPI0_CS0", ++ "SPI0_TXD", ++ "SPI0_RXD", ++ ++ "", ++ "", ++ "", ++ "VCC50_HDMI_EN"; ++}; ++ ++&gpio6 { ++ gpio-line-names = "I2S0_SCLK", ++ "I2S0_LRCK_RX", ++ "I2S0_LRCK_TX", ++ "I2S0_SDI", ++ "I2S0_SDO0", ++ "HP_DET_H", ++ "", ++ "INT_CODEC", ++ ++ "I2S0_CLK", ++ "I2C2_SDA", ++ "I2C2_SCL", ++ "MICDET", ++ "", ++ "", ++ "", ++ "", ++ ++ "SDMMC_D0", ++ "SDMMC_D1", ++ "SDMMC_D2", ++ "SDMMC_D3", ++ "SDMMC_CLK", ++ "SDMMC_CMD"; ++}; ++ ++&gpio7 { ++ gpio-line-names = "LCDC_BL", ++ "PWM_LOG", ++ "BL_EN", ++ "TRACKPAD_INT", ++ "TPM_INT_H", ++ "SDMMC_DET_L", ++ /* ++ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call ++ * it FW_WP_AP. ++ */ ++ "AP_FLASH_WP_L", ++ "EC_INT", ++ ++ "CPU_NMI", ++ "DVS_OK", ++ "SDMMC_WP", ++ "EDP_HPD", ++ "DVS1", ++ "nFALUT1", ++ "LCD_EN", ++ "DVS2", ++ ++ "VCC5V_GOOD_H", ++ "I2C4_SDA_TP", ++ "I2C4_SCL_TP", ++ "I2C5_SDA_HDMI", ++ "I2C5_SCL_HDMI", ++ "5V_DRV", ++ "UART2_RXD", ++ "UART2_TXD"; ++}; ++ ++&gpio8 { ++ gpio-line-names = "RAM_ID0", ++ "RAM_ID1", ++ "RAM_ID2", ++ "RAM_ID3", ++ "I2C1_SDA_TPM", ++ "I2C1_SCL_TPM", ++ "SPI2_CLK", ++ "SPI2_CS0", ++ ++ "SPI2_RXD", ++ "SPI2_TXD"; ++}; ++ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0036-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jer.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0036-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jer.patch new file mode 100644 index 0000000..e1136fe --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0036-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jer.patch @@ -0,0 +1,237 @@ +From 0ca87bd5baa62e5734800ee63e3a6301c90e8613 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Tue, 21 May 2019 13:32:15 -0700 +Subject: [PATCH 36/54] ARM: dts: rockchip: Add pin names for + rk3288-veyron-jerry + +This is like the same change for rk3288-veyron-minnie. See that patch +for more details. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-jerry.dts | 207 ++++++++++++++++++++++++++++++ + 1 file changed, 207 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +index b1613af83d5d..164561f04c1d 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts +@@ -103,6 +103,213 @@ + pinctrl-0 = <&vcc50_hdmi_en>; + }; + ++&gpio0 { ++ gpio-line-names = "PMIC_SLEEP_AP", ++ "DDRIO_PWROFF", ++ "DDRIO_RETEN", ++ "TS3A227E_INT_L", ++ "PMIC_INT_L", ++ "PWR_KEY_L", ++ "AP_LID_INT_L", ++ "EC_IN_RW", ++ ++ "AC_PRESENT_AP", ++ /* ++ * RECOVERY_SW_L is Chrome OS ABI. Schematics call ++ * it REC_MODE_L. ++ */ ++ "RECOVERY_SW_L", ++ "OTP_OUT", ++ "HOST1_PWR_EN", ++ "USBOTG_PWREN_H", ++ "AP_WARM_RESET_H", ++ "nFAULT2", ++ "I2C0_SDA_PMIC", ++ ++ "I2C0_SCL_PMIC", ++ "SUSPEND_L", ++ "USB_INT"; ++}; ++ ++&gpio2 { ++ gpio-line-names = "CONFIG0", ++ "CONFIG1", ++ "CONFIG2", ++ "", ++ "", ++ "", ++ "", ++ "CONFIG3", ++ ++ "", ++ "EMMC_RST_L", ++ "", ++ "", ++ "BL_PWR_EN", ++ "AVDD_1V8_DISP_EN"; ++}; ++ ++&gpio3 { ++ gpio-line-names = "FLASH0_D0", ++ "FLASH0_D1", ++ "FLASH0_D2", ++ "FLASH0_D3", ++ "FLASH0_D4", ++ "FLASH0_D5", ++ "FLASH0_D6", ++ "FLASH0_D7", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "FLASH0_CS2/EMMC_CMD", ++ "", ++ "FLASH0_DQS/EMMC_CLKO"; ++}; ++ ++&gpio4 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "UART0_RXD", ++ "UART0_TXD", ++ "UART0_CTS", ++ "UART0_RTS", ++ "SDIO0_D0", ++ "SDIO0_D1", ++ "SDIO0_D2", ++ "SDIO0_D3", ++ ++ "SDIO0_CMD", ++ "SDIO0_CLK", ++ "BT_DEV_WAKE", ++ "", ++ "WIFI_ENABLE_H", ++ "BT_ENABLE_L", ++ "WIFI_HOST_WAKE", ++ "BT_HOST_WAKE"; ++}; ++ ++&gpio5 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "SPI0_CLK", ++ "SPI0_CS0", ++ "SPI0_TXD", ++ "SPI0_RXD", ++ ++ "", ++ "", ++ "", ++ "VCC50_HDMI_EN"; ++}; ++ ++&gpio6 { ++ gpio-line-names = "I2S0_SCLK", ++ "I2S0_LRCK_RX", ++ "I2S0_LRCK_TX", ++ "I2S0_SDI", ++ "I2S0_SDO0", ++ "HP_DET_H", ++ "", ++ "INT_CODEC", ++ ++ "I2S0_CLK", ++ "I2C2_SDA", ++ "I2C2_SCL", ++ "MICDET", ++ "", ++ "", ++ "", ++ "", ++ ++ "SDMMC_D0", ++ "SDMMC_D1", ++ "SDMMC_D2", ++ "SDMMC_D3", ++ "SDMMC_CLK", ++ "SDMMC_CMD"; ++}; ++ ++&gpio7 { ++ gpio-line-names = "LCDC_BL", ++ "PWM_LOG", ++ "BL_EN", ++ "TRACKPAD_INT", ++ "TPM_INT_H", ++ "SDMMC_DET_L", ++ /* ++ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call ++ * it FW_WP_AP. ++ */ ++ "AP_FLASH_WP_L", ++ "EC_INT", ++ ++ "CPU_NMI", ++ "DVSOK", ++ "", ++ "EDP_HPD", ++ "DVS1", ++ "nFAULT1", ++ "LCD_EN", ++ "DVS2", ++ ++ "VCC5V_GOOD_H", ++ "I2C4_SDA_TP", ++ "I2C4_SCL_TP", ++ "I2C5_SDA_HDMI", ++ "I2C5_SCL_HDMI", ++ "5V_DRV", ++ "UART2_RXD", ++ "UART2_TXD"; ++}; ++ ++&gpio8 { ++ gpio-line-names = "RAM_ID0", ++ "RAM_ID1", ++ "RAM_ID2", ++ "RAM_ID3", ++ "I2C1_SDA_TPM", ++ "I2C1_SCL_TPM", ++ "SPI2_CLK", ++ "SPI2_CS0", ++ ++ "SPI2_RXD", ++ "SPI2_TXD"; ++}; ++ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch new file mode 100644 index 0000000..dc182c6 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch @@ -0,0 +1,31 @@ +From f6dcbb3ad5ce927adbdcc04bde312387f3b68035 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Thu, 16 May 2019 10:25:09 -0700 +Subject: [PATCH 38/54] ARM: dts: rockchip: Add #cooling-cells entry for rk3288 + GPU + +The Mali GPU of the rk3288 can be used as cooling device, add +a #cooling-cells entry for it. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 1e5260b556b7..7e9b8c7f6ab7 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1286,6 +1286,7 @@ + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; ++ #cooling-cells = <2>; /* min followed by max */ + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch new file mode 100644 index 0000000..7e3539d --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch @@ -0,0 +1,40 @@ +From ae2b6ba865d8bb59493aaf50cb3d19312a6ff5a4 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Thu, 16 May 2019 10:25:10 -0700 +Subject: [PATCH 39/54] ARM: dts: rockchip: Use GPU as cooling device for the + GPU thermal zone of the rk3288 + +Currently the CPUs are used as cooling devices of the rk3288 GPU +thermal zone. The CPUs are also configured as cooling devices in the +CPU thermal zone, which indirectly helps with cooling the GPU thermal +zone, since the CPU and GPU temperatures are correlated on the rk3288. + +Configure the ARM Mali Midgard GPU as cooling device for the GPU +thermal zone instead of the CPUs. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 7e9b8c7f6ab7..fd188bb4fd48 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -552,10 +552,7 @@ + map0 { + trip = <&gpu_alert0>; + cooling-device = +- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, +- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch new file mode 100644 index 0000000..9a6453b --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch @@ -0,0 +1,41 @@ +From 75481833c6dbab4c29d15452f6b4337c16f5407b Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Mon, 20 May 2019 15:00:49 -0700 +Subject: [PATCH 40/54] ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288 + +The NPLL is the only safe way to generate 500 MHz for the GPU. The +downstream Chrome OS 3.14 kernel ('official' kernel for veyron +devices) re-purposes NPLL to HDMI and hence disables the OPP for +the GPU (see https://crrev.com/c/1574579). Disable it here as well +to keep in sync and avoid problems in case someone decides to +re-purpose NPLL. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +[moved from veyron to general rk3288, as tying up the NPLL for a + not-that-helpful opp (not really fast but will still generate + quite a bit of heat) doesn't make so much sense when it will + keep us from supporting other display modes in the future] +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index fd188bb4fd48..159d91180cee 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1307,10 +1307,6 @@ + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; +- opp-500000000 { +- opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <1200000>; +- }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0041-ARM-dts-rockchip-Use-the-GPU-to-cool-CPU-thermal-zon.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0041-ARM-dts-rockchip-Use-the-GPU-to-cool-CPU-thermal-zon.patch new file mode 100644 index 0000000..3f032b9 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0041-ARM-dts-rockchip-Use-the-GPU-to-cool-CPU-thermal-zon.patch @@ -0,0 +1,65 @@ +From 11983d8530e3d4e9cdd9e5cb7c23611adaf67c73 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Mon, 20 May 2019 15:00:50 -0700 +Subject: [PATCH 41/54] ARM: dts: rockchip: Use the GPU to cool CPU thermal + zone of veyron mickey +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On rk3288 the CPU and GPU temperatures are correlated. Limit the GPU +frequency on veyron mickey to 400 MHz for CPU temperatures >= 65°C +and to 300 MHz for CPU temperatures >= 85°C. + +This matches the configuration of the downstream Chrome OS 3.14 kernel, +the 'official' kernel for mickey. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-mickey.dts | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +index 52f6abc22291..34797abe3403 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +@@ -75,9 +75,7 @@ + cooling-maps { + /* + * After 1st level, throttle the CPU down to as low as 1.4 GHz +- * and don't let the GPU go faster than 400 MHz. Note that we +- * won't throttle the GPU lower than 400 MHz due to CPU +- * heat--we'll let the GPU do the rest itself. ++ * and don't let the GPU go faster than 400 MHz. + */ + cpu_warm_limit_cpu { + trip = <&cpu_alert_warm>; +@@ -86,6 +84,10 @@ + <&cpu2 THERMAL_NO_LIMIT 4>, + <&cpu3 THERMAL_NO_LIMIT 4>; + }; ++ cpu_warm_limit_gpu { ++ trip = <&cpu_alert_warm>; ++ cooling-device = <&gpu 1 1>; ++ }; + + /* + * Add some discrete steps to help throttling system deal +@@ -125,6 +127,12 @@ + <&cpu2 8 THERMAL_NO_LIMIT>, + <&cpu3 8 THERMAL_NO_LIMIT>; + }; ++ ++ /* At very hot, don't let GPU go over 300 MHz */ ++ cpu_very_hot_limit_gpu { ++ trip = <&cpu_alert_very_hot>; ++ cooling-device = <&gpu 2 2>; ++ }; + }; + }; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0042-ARM-dts-rockchip-Configure-the-GPU-thermal-zone-for-.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0042-ARM-dts-rockchip-Configure-the-GPU-thermal-zone-for-.patch new file mode 100644 index 0000000..a4d0cfa --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0042-ARM-dts-rockchip-Configure-the-GPU-thermal-zone-for-.patch @@ -0,0 +1,108 @@ +From c87efcc3d1dfdf3f5ecb6558521825a21838dc30 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Mon, 20 May 2019 15:00:51 -0700 +Subject: [PATCH 42/54] ARM: dts: rockchip: Configure the GPU thermal zone for + mickey +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mickey crams a lot of hardware into a tiny package, which requires +more aggressive thermal throttling than for devices with a larger +footprint. Configure the GPU thermal zone to throttle the GPU +progressively at temperatures >= 60°C. Heat dissipated by the +CPUs also affects the GPU temperature, hence we cap the CPU +frequency to 1.4 GHz for temperatures above 65°C. Further throttling +of the CPUs may be performed by the CPU thermal zone. + +The configuration matches that of the downstream Chrome OS 3.14 +kernel, the 'official' kernel for mickey. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-mickey.dts | 67 ++++++++++++++++++++++++++++++ + 1 file changed, 67 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +index 34797abe3403..945e80801292 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +@@ -136,6 +136,73 @@ + }; + }; + ++&gpu_thermal { ++ /delete-node/ trips; ++ /delete-node/ cooling-maps; ++ ++ trips { ++ gpu_alert_warmish: gpu_alert_warmish { ++ temperature = <60000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ gpu_alert_warm: gpu_alert_warm { ++ temperature = <65000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ gpu_alert_hotter: gpu_alert_hotter { ++ temperature = <84000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ gpu_alert_very_very_hot: gpu_alert_very_very_hot { ++ temperature = <86000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "passive"; ++ }; ++ gpu_crit: gpu_crit { ++ temperature = <90000>; /* millicelsius */ ++ hysteresis = <2000>; /* millicelsius */ ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ /* After 1st level throttle the GPU down to as low as 400 MHz */ ++ gpu_warmish_limit_gpu { ++ trip = <&gpu_alert_warmish>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT 1>; ++ }; ++ ++ /* ++ * Slightly after we throttle the GPU, we'll also make sure that ++ * the CPU can't go faster than 1.4 GHz. Note that we won't ++ * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll ++ * let the CPU do the rest itself. ++ */ ++ gpu_warm_limit_cpu { ++ trip = <&gpu_alert_warm>; ++ cooling-device = <&cpu0 4 4>, ++ <&cpu1 4 4>, ++ <&cpu2 4 4>, ++ <&cpu3 4 4>; ++ }; ++ ++ /* When hot, GPU goes down to 300 MHz */ ++ gpu_hotter_limit_gpu { ++ trip = <&gpu_alert_hotter>; ++ cooling-device = <&gpu 2 2>; ++ }; ++ ++ /* When really hot, don't let GPU go _above_ 300 MHz */ ++ gpu_very_very_hot_limit_gpu { ++ trip = <&gpu_alert_very_very_hot>; ++ cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &i2c2 { + status = "disabled"; + }; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch new file mode 100644 index 0000000..11c2a08 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch @@ -0,0 +1,29 @@ +From 9dbf05bd8ae5b436b02c9845a350dec11c788a73 Mon Sep 17 00:00:00 2001 +From: John Keeping +Date: Mon, 3 Jun 2019 15:34:35 +0100 +Subject: [PATCH 43/54] ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3 + +This is the same as the other PWMs on this SoC and uses 3 cells. + +Signed-off-by: John Keeping +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 159d91180cee..766d1cf51a5b 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -710,7 +710,7 @@ + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; +- #pwm-cells = <2>; ++ #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_RKPWM>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch new file mode 100644 index 0000000..155529e --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch @@ -0,0 +1,637 @@ +From d85b2ad35a2ab320b9c0530992ee532f10a6aeb2 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Fri, 24 May 2019 16:33:09 -0700 +Subject: [PATCH 44/54] ARM: dts: rockchip: Add pin names for rk3288-veyron + jaq, mickey, speedy + +This is like commit 0ca87bd5baa6 ("ARM: dts: rockchip: Add pin names +for rk3288-veyron-jerry") and commit ca3516b32cd9 ("ARM: dts: +rockchip: Add pin names for rk3288-veyron-minnie") but for 3 more +veyron boards. + +A few notes: +- While there is most certainly duplication between all the veyron + boards, it still feels like it is sane to just have each board have + a full list of its pin names. The format of "gpio-line-names" does + not lend itself to one-off overriding and besides it seems sane to + more fully match schematic names. Also note that the extra + duplication here is only in source code and is unlikely to ever + change (since these boards are shipped). Duplication in the .dtb + files is unavoidable. +- veyron-jaq and veyron-mighty are very closely related and so I have + shared a single list for them both with comments on how they are + different. This is just a typo fix on one of the boards, a possible + missing signal on one of the boards (or perhaps I was never given + the most recent schematics?) and dealing with the fact that one of + the two boards has full sized SD. + +Signed-off-by: Douglas Anderson +Reviewed-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-jaq.dts | 207 +++++++++++++++++++++++++++++ + arch/arm/boot/dts/rk3288-veyron-mickey.dts | 151 +++++++++++++++++++++ + arch/arm/boot/dts/rk3288-veyron-speedy.dts | 207 +++++++++++++++++++++++++++++ + 3 files changed, 565 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts +index e248f55ee8d2..fcd119168cb6 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts +@@ -135,6 +135,213 @@ + pinctrl-0 = <&vcc50_hdmi_en>; + }; + ++&gpio0 { ++ gpio-line-names = "PMIC_SLEEP_AP", ++ "DDRIO_PWROFF", ++ "DDRIO_RETEN", ++ "TS3A227E_INT_L", ++ "PMIC_INT_L", ++ "PWR_KEY_L", ++ "AP_LID_INT_L", ++ "EC_IN_RW", ++ ++ "AC_PRESENT_AP", ++ /* ++ * RECOVERY_SW_L is Chrome OS ABI. Schematics call ++ * it REC_MODE_L. ++ */ ++ "RECOVERY_SW_L", ++ "OTP_OUT", ++ "HOST1_PWR_EN", ++ "USBOTG_PWREN_H", ++ "AP_WARM_RESET_H", ++ "nFALUT2", ++ "I2C0_SDA_PMIC", ++ ++ "I2C0_SCL_PMIC", ++ "SUSPEND_L", ++ "USB_INT"; ++}; ++ ++&gpio2 { ++ gpio-line-names = "CONFIG0", ++ "CONFIG1", ++ "CONFIG2", ++ "", ++ "", ++ "", ++ "", ++ "CONFIG3", ++ ++ "", ++ "EMMC_RST_L", ++ "", ++ "", ++ "BL_PWR_EN", ++ "AVDD_1V8_DISP_EN"; ++}; ++ ++&gpio3 { ++ gpio-line-names = "FLASH0_D0", ++ "FLASH0_D1", ++ "FLASH0_D2", ++ "FLASH0_D3", ++ "FLASH0_D4", ++ "FLASH0_D5", ++ "FLASH0_D6", ++ "FLASH0_D7", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "FLASH0_CS2/EMMC_CMD", ++ "", ++ "FLASH0_DQS/EMMC_CLKO"; ++}; ++ ++&gpio4 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "UART0_RXD", ++ "UART0_TXD", ++ "UART0_CTS", ++ "UART0_RTS", ++ "SDIO0_D0", ++ "SDIO0_D1", ++ "SDIO0_D2", ++ "SDIO0_D3", ++ ++ "SDIO0_CMD", ++ "SDIO0_CLK", ++ "BT_DEV_WAKE", /* Maybe missing from mighty? */ ++ "", ++ "WIFI_ENABLE_H", ++ "BT_ENABLE_L", ++ "WIFI_HOST_WAKE", ++ "BT_HOST_WAKE"; ++}; ++ ++&gpio5 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "SPI0_CLK", ++ "SPI0_CS0", ++ "SPI0_TXD", ++ "SPI0_RXD", ++ ++ "", ++ "", ++ "", ++ "VCC50_HDMI_EN"; ++}; ++ ++&gpio6 { ++ gpio-line-names = "I2S0_SCLK", ++ "I2S0_LRCK_RX", ++ "I2S0_LRCK_TX", ++ "I2S0_SDI", ++ "I2S0_SDO0", ++ "HP_DET_H", ++ "ALS_INT", ++ "INT_CODEC", ++ ++ "I2S0_CLK", ++ "I2C2_SDA", ++ "I2C2_SCL", ++ "MICDET", ++ "", ++ "", ++ "", ++ "", ++ ++ "SDMMC_D0", ++ "SDMMC_D1", ++ "SDMMC_D2", ++ "SDMMC_D3", ++ "SDMMC_CLK", ++ "SDMMC_CMD"; ++}; ++ ++&gpio7 { ++ gpio-line-names = "LCDC_BL", ++ "PWM_LOG", ++ "BL_EN", ++ "TRACKPAD_INT", ++ "TPM_INT_H", ++ "SDMMC_DET_L", ++ /* ++ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call ++ * it FW_WP_AP. ++ */ ++ "AP_FLASH_WP_L", ++ "EC_INT", ++ ++ "CPU_NMI", ++ "DVSOK", ++ "SDMMC_WP", /* mighty only */ ++ "EDP_HPD", ++ "DVS1", ++ "nFALUT1", /* nFAULT1 on jaq */ ++ "LCD_EN", ++ "DVS2", ++ ++ "VCC5V_GOOD_H", ++ "I2C4_SDA_TP", ++ "I2C4_SCL_TP", ++ "I2C5_SDA_HDMI", ++ "I2C5_SCL_HDMI", ++ "5V_DRV", ++ "UART2_RXD", ++ "UART2_TXD"; ++}; ++ ++&gpio8 { ++ gpio-line-names = "RAM_ID0", ++ "RAM_ID1", ++ "RAM_ID2", ++ "RAM_ID3", ++ "I2C1_SDA_TPM", ++ "I2C1_SCL_TPM", ++ "SPI2_CLK", ++ "SPI2_CS0", ++ ++ "SPI2_RXD", ++ "SPI2_TXD"; ++}; ++ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +index 945e80801292..aa352d40c991 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts +@@ -252,6 +252,157 @@ + }; + }; + ++&gpio0 { ++ gpio-line-names = "PMIC_SLEEP_AP", ++ "", ++ "", ++ "", ++ "PMIC_INT_L", ++ "POWER_BUTTON_L", ++ "", ++ "", ++ ++ "", ++ /* ++ * RECOVERY_SW_L is Chrome OS ABI. Schematics call ++ * it REC_MODE_L. ++ */ ++ "RECOVERY_SW_L", ++ "OT_RESET", ++ "", ++ "", ++ "AP_WARM_RESET_H", ++ "", ++ "I2C0_SDA_PMIC", ++ ++ "I2C0_SCL_PMIC", ++ "", ++ "nFALUT"; ++}; ++ ++&gpio2 { ++ gpio-line-names = "CONFIG0", ++ "CONFIG1", ++ "CONFIG2", ++ "", ++ "", ++ "", ++ "", ++ "CONFIG3", ++ ++ "", ++ "EMMC_RST_L"; ++}; ++ ++&gpio3 { ++ gpio-line-names = "FLASH0_D0", ++ "FLASH0_D1", ++ "FLASH0_D2", ++ "FLASH0_D3", ++ "FLASH0_D4", ++ "FLASH0_D5", ++ "FLASH0_D6", ++ "FLASH0_D7", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "FLASH0_CS2/EMMC_CMD", ++ "", ++ "FLASH0_DQS/EMMC_CLKO"; ++}; ++ ++&gpio4 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "UART0_RXD", ++ "UART0_TXD", ++ "UART0_CTS_L", ++ "UART0_RTS_L", ++ "SDIO0_D0", ++ "SDIO0_D1", ++ "SDIO0_D2", ++ "SDIO0_D3", ++ ++ "SDIO0_CMD", ++ "SDIO0_CLK", ++ "BT_DEV_WAKE", ++ "", ++ "WIFI_ENABLE_H", ++ "BT_ENABLE_L", ++ "WIFI_HOST_WAKE", ++ "BT_HOST_WAKE"; ++}; ++ ++&gpio7 { ++ gpio-line-names = "", ++ "PWM_LOG", ++ "", ++ "", ++ "TPM_INT_H", ++ "SDMMC_DET_L", ++ /* ++ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call ++ * it FW_WP_AP. ++ */ ++ "AP_FLASH_WP_L", ++ "", ++ ++ "CPU_NMI", ++ "DVSOK", ++ "HDMI_WAKE", ++ "POWER_HDMI_ON", ++ "DVS1", ++ "", ++ "", ++ "DVS2", ++ ++ "HDMI_CEC", ++ "", ++ "", ++ "I2C5_SDA_HDMI", ++ "I2C5_SCL_HDMI", ++ "", ++ "UART2_RXD", ++ "UART2_TXD"; ++}; ++ ++&gpio8 { ++ gpio-line-names = "RAM_ID0", ++ "RAM_ID1", ++ "RAM_ID2", ++ "RAM_ID3", ++ "I2C1_SDA_TPM", ++ "I2C1_SCL_TPM", ++ "SPI2_CLK", ++ "SPI2_CS0", ++ ++ "SPI2_RXD", ++ "SPI2_TXD"; ++}; ++ + &pinctrl { + hdmi { + power_hdmi_on: power-hdmi-on { +diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +index 9a87017347ea..9b140db04456 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts +@@ -113,6 +113,213 @@ + pinctrl-0 = <&vcc50_hdmi_en>; + }; + ++&gpio0 { ++ gpio-line-names = "PMIC_SLEEP_AP", ++ "DDRIO_PWROFF", ++ "DDRIO_RETEN", ++ "TS3A227E_INT_L", ++ "PMIC_INT_L", ++ "PWR_KEY_L", ++ "AP_LID_INT_L", ++ "EC_IN_RW", ++ ++ "AC_PRESENT_AP", ++ /* ++ * RECOVERY_SW_L is Chrome OS ABI. Schematics call ++ * it REC_MODE_L. ++ */ ++ "RECOVERY_SW_L", ++ "OTP_OUT", ++ "HOST1_PWR_EN", ++ "USBOTG_PWREN_H", ++ "AP_WARM_RESET_H", ++ "nFALUT2", ++ "I2C0_SDA_PMIC", ++ ++ "I2C0_SCL_PMIC", ++ "SUSPEND_L", ++ "USB_INT"; ++}; ++ ++&gpio2 { ++ gpio-line-names = "CONFIG0", ++ "CONFIG1", ++ "CONFIG2", ++ "", ++ "", ++ "", ++ "", ++ "CONFIG3", ++ ++ "PWRLIMIT#_CPU", ++ "EMMC_RST_L", ++ "", ++ "", ++ "BL_PWR_EN", ++ "AVDD_1V8_DISP_EN"; ++}; ++ ++&gpio3 { ++ gpio-line-names = "FLASH0_D0", ++ "FLASH0_D1", ++ "FLASH0_D2", ++ "FLASH0_D3", ++ "FLASH0_D4", ++ "FLASH0_D5", ++ "FLASH0_D6", ++ "FLASH0_D7", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "FLASH0_CS2/EMMC_CMD", ++ "", ++ "FLASH0_DQS/EMMC_CLKO"; ++}; ++ ++&gpio4 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "UART0_RXD", ++ "UART0_TXD", ++ "UART0_CTS", ++ "UART0_RTS", ++ "SDIO0_D0", ++ "SDIO0_D1", ++ "SDIO0_D2", ++ "SDIO0_D3", ++ ++ "SDIO0_CMD", ++ "SDIO0_CLK", ++ "BT_DEV_WAKE", ++ "", ++ "WIFI_ENABLE_H", ++ "BT_ENABLE_L", ++ "WIFI_HOST_WAKE", ++ "BT_HOST_WAKE"; ++}; ++ ++&gpio5 { ++ gpio-line-names = "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ "", ++ ++ "", ++ "", ++ "", ++ "", ++ "SPI0_CLK", ++ "SPI0_CS0", ++ "SPI0_TXD", ++ "SPI0_RXD", ++ ++ "", ++ "", ++ "", ++ "VCC50_HDMI_EN"; ++}; ++ ++&gpio6 { ++ gpio-line-names = "I2S0_SCLK", ++ "I2S0_LRCK_RX", ++ "I2S0_LRCK_TX", ++ "I2S0_SDI", ++ "I2S0_SDO0", ++ "HP_DET_H", ++ "ALS_INT", /* not connected */ ++ "INT_CODEC", ++ ++ "I2S0_CLK", ++ "I2C2_SDA", ++ "I2C2_SCL", ++ "MICDET", ++ "", ++ "", ++ "", ++ "", ++ ++ "SDMMC_D0", ++ "SDMMC_D1", ++ "SDMMC_D2", ++ "SDMMC_D3", ++ "SDMMC_CLK", ++ "SDMMC_CMD"; ++}; ++ ++&gpio7 { ++ gpio-line-names = "LCDC_BL", ++ "PWM_LOG", ++ "BL_EN", ++ "TRACKPAD_INT", ++ "TPM_INT_H", ++ "SDMMC_DET_L", ++ /* ++ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call ++ * it FW_WP_AP. ++ */ ++ "AP_FLASH_WP_L", ++ "EC_INT", ++ ++ "CPU_NMI", ++ "DVS_OK", ++ "", ++ "EDP_HOTPLUG", ++ "DVS1", ++ "nFALUT1", ++ "LCD_EN", ++ "DVS2", ++ ++ "VCC5V_GOOD_H", ++ "I2C4_SDA_TP", ++ "I2C4_SCL_TP", ++ "I2C5_SDA_HDMI", ++ "I2C5_SCL_HDMI", ++ "5V_DRV", ++ "UART2_RXD", ++ "UART2_TXD"; ++}; ++ ++&gpio8 { ++ gpio-line-names = "RAM_ID0", ++ "RAM_ID1", ++ "RAM_ID2", ++ "RAM_ID3", ++ "I2C1_SDA_TPM", ++ "I2C1_SCL_TPM", ++ "SPI2_CLK", ++ "SPI2_CS0", ++ ++ "SPI2_RXD", ++ "SPI2_TXD"; ++}; ++ + &pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0045-ARM-dts-rockchip-Switch-to-builtin-HDMI-DDC-bus-on-r.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0045-ARM-dts-rockchip-Switch-to-builtin-HDMI-DDC-bus-on-r.patch new file mode 100644 index 0000000..bc1e393 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0045-ARM-dts-rockchip-Switch-to-builtin-HDMI-DDC-bus-on-r.patch @@ -0,0 +1,52 @@ +From bf09924f21767e6bb7cb3aae48c48c2c2ab8261a Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 2 May 2019 15:53:34 -0700 +Subject: [PATCH 45/54] ARM: dts: rockchip: Switch to builtin HDMI DDC bus on + rk3288-veyron + +Downstream Chrome OS kernels use the builtin DDC bus from dw_hdmi on +veyron. This is the only way to get them to negotiate HDCP. + +Although HDCP isn't currently all supported upstream, it still seems +like it makes sense to use dw_hdmi's builtin I2C. Maybe eventually we +can get HDCP negotiation working. + +Signed-off-by: Douglas Anderson +Reviewed-by: Sean Paul +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 11 ++--------- + 1 file changed, 2 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 90c8312d01ff..99e2771d4d31 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -175,7 +175,8 @@ + }; + + &hdmi { +- ddc-i2c-bus = <&i2c5>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_ddc>; + status = "okay"; + }; + +@@ -346,14 +347,6 @@ + i2c-scl-rising-time-ns = <300>; /* 225ns measured */ + }; + +-&i2c5 { +- status = "okay"; +- +- clock-frequency = <100000>; +- i2c-scl-falling-time-ns = <300>; +- i2c-scl-rising-time-ns = <1000>; +-}; +- + &io_domains { + status = "okay"; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch new file mode 100644 index 0000000..cba84ed --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch @@ -0,0 +1,47 @@ +From c077d9d717dc481a6a95f9ef2562ef6bda74fbdf Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 2 May 2019 15:53:35 -0700 +Subject: [PATCH 46/54] ARM: dts: rockchip: Add unwedge pinctrl entries for + dw_hdmi on rk3288 + +This adds the "unwedge" pinctrl entries introduced by a recent dw_hdmi +change that can unwedge the dw_hdmi i2c bus in some cases. It's +expected that any boards using this would add: + + pinctrl-names = "default", "unwedge"; + pinctrl-0 = <&hdmi_ddc>; + pinctrl-1 = <&hdmi_ddc_unwedge>; + +Note that this isn't added by default because some boards may choose +to mux i2c5 for their DDC bus (if that is more tested for them). + +Signed-off-by: Douglas Anderson +Reviewed-by: Sean Paul +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 766d1cf51a5b..cc893e154fe5 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1547,6 +1547,15 @@ + rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, + <7 RK_PC4 2 &pcfg_pull_none>; + }; ++ ++ hdmi_ddc_unwedge: hdmi-ddc-unwedge { ++ rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, ++ <7 RK_PC4 2 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcfg_output_low: pcfg-output-low { ++ output-low; + }; + + pcfg_pull_up: pcfg-pull-up { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0047-ARM-dts-rockchip-Add-HDMI-i2c-unwedging-for-rk3288-v.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0047-ARM-dts-rockchip-Add-HDMI-i2c-unwedging-for-rk3288-v.patch new file mode 100644 index 0000000..cf78a91 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0047-ARM-dts-rockchip-Add-HDMI-i2c-unwedging-for-rk3288-v.patch @@ -0,0 +1,34 @@ +From cd6386087d826b9421ed97b778676f4177ffdfbd Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Thu, 2 May 2019 15:53:36 -0700 +Subject: [PATCH 47/54] ARM: dts: rockchip: Add HDMI i2c unwedging for + rk3288-veyron + +Veyron uses the builtin i2c controller that's part of dw-hdmi. Hook +up the unwedging feature. + +Signed-off-by: Douglas Anderson +Reviewed-by: Sean Paul +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 99e2771d4d31..c574844a6bb2 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -175,8 +175,9 @@ + }; + + &hdmi { +- pinctrl-names = "default"; ++ pinctrl-names = "default", "unwedge"; + pinctrl-0 = <&hdmi_ddc>; ++ pinctrl-1 = <&hdmi_ddc_unwedge>; + status = "okay"; + }; + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch new file mode 100644 index 0000000..e7b03a8 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch @@ -0,0 +1,155 @@ +From b8925b7c2f867df6ce3e20deb4b3e2b9b32b20ff Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Wed, 5 Jun 2019 13:43:19 -0700 +Subject: [PATCH 48/54] ARM: dts: rockchip: Split GPIO keys for veyron into + multiple devices + +With a single device DT overrides can become messy, especially when +keys are added or removed. Multiple devices also allow to +enable/disable wakeup per key/group. + +Signed-off-by: Matthias Kaehlcke +[used actual switch+event constants in new lid-switch entry] +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 27 ++++++++++-------- + arch/arm/boot/dts/rk3288-veyron-minnie.dts | 38 +++++++++++++------------ + arch/arm/boot/dts/rk3288-veyron-pinky.dts | 2 +- + arch/arm/boot/dts/rk3288-veyron.dtsi | 4 +-- + 4 files changed, 38 insertions(+), 33 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +index fbef34578100..5727017f34b2 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +@@ -70,6 +70,21 @@ + pinctrl-0 = <&ac_present_ap>; + }; + ++ lid_switch: lid-switch { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ap_lid_int_l>; ++ ++ lid { ++ label = "Lid"; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; ++ wakeup-source; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <1>; ++ }; ++ }; ++ + panel: panel { + compatible ="innolux,n116bge", "simple-panel"; + status = "okay"; +@@ -149,18 +164,6 @@ + status = "okay"; + }; + +-&gpio_keys { +- pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; +- lid { +- label = "Lid"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +- wakeup-source; +- linux,code = <0>; /* SW_LID */ +- linux,input-type = <5>; /* EV_SW */ +- debounce-interval = <1>; +- }; +-}; +- + &pwm0 { + status = "okay"; + }; +diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +index a65099b4aef1..b2cc70a08554 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +@@ -48,6 +48,26 @@ + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; ++ ++ volume_buttons: volume-buttons { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&volum_down_l &volum_up_l>; ++ ++ volum_down { ++ label = "Volum_down"; ++ gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <100>; ++ }; ++ ++ volum_up { ++ label = "Volum_up"; ++ gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <100>; ++ }; ++ }; + }; + + &backlight { +@@ -90,24 +110,6 @@ + pwm-off-delay-ms = <200>; + }; + +-&gpio_keys { +- pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>; +- +- volum_down { +- label = "Volum_down"; +- gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <100>; +- }; +- +- volum_up { +- label = "Volum_up"; +- gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <100>; +- }; +-}; +- + &i2c_tunnel { + battery: bq27500@55 { + compatible = "ti,bq27500"; +diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts +index 9645be7b3d8c..9b6f4d9b03b6 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts +@@ -35,7 +35,7 @@ + force-hpd; + }; + +-&gpio_keys { ++&lid_switch { + pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; + + power { +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index c574844a6bb2..3257ca90f0e8 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -23,11 +23,11 @@ + reg = <0x0 0x0 0x0 0x80000000>; + }; + +- gpio_keys: gpio-keys { ++ power_button: power-button { + compatible = "gpio-keys"; +- + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; ++ + power { + label = "Power"; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0049-ARM-dts-rockchip-Configure-BT_HOST_WAKE-as-wake-up-s.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0049-ARM-dts-rockchip-Configure-BT_HOST_WAKE-as-wake-up-s.patch new file mode 100644 index 0000000..52c815a --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0049-ARM-dts-rockchip-Configure-BT_HOST_WAKE-as-wake-up-s.patch @@ -0,0 +1,67 @@ +From f497ab6b4bb813aca439b7f3a72a060b58b147c4 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Mon, 10 Jun 2019 16:51:44 -0700 +Subject: [PATCH 49/54] ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up + signal on veyron + +This enables wake up on Bluetooth activity when the device is +suspended. The BT_HOST_WAKE signal is only connected on devices +with BT module that are connected through UART. + +Signed-off-by: Douglas Anderson +Signed-off-by: Matthias Kaehlcke +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 3257ca90f0e8..e2635ad574e7 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -23,6 +23,31 @@ + reg = <0x0 0x0 0x0 0x80000000>; + }; + ++ bt_activity: bt-activity { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake>; ++ ++ /* ++ * HACK: until we have an LPM driver, we'll use an ++ * ugly GPIO key to allow Bluetooth to wake from S3. ++ * This is expected to only be used by BT modules that ++ * use UART for comms. For BT modules that talk over ++ * SDIO we should use a wakeup mechanism related to SDIO. ++ * ++ * Use KEY_RESERVED here since that will work as a wakeup but ++ * doesn't get reported to higher levels (so doesn't confuse ++ * Chrome). ++ */ ++ bt-wake { ++ label = "BT Wakeup"; ++ gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; ++ linux,code = ; ++ wakeup-source; ++ }; ++ ++ }; ++ + power_button: power-button { + compatible = "gpio-keys"; + pinctrl-names = "default"; +@@ -549,6 +574,10 @@ + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + ++ bt_host_wake: bt-host-wake { ++ rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ + /* + * We run sdio0 at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch new file mode 100644 index 0000000..16b24f7 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch @@ -0,0 +1,48 @@ +From 1d390437f605db28596ad4c4bfeca2fed052c025 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Mon, 20 May 2019 10:56:05 -0700 +Subject: [PATCH 50/54] ARM: dts: rockchip: Allow wakeup from rk3288-veyron's + dwc2 USB ports + +We want to be able to wake from USB if a device is plugged in that +wants remote wakeup. Enable it on both dwc2 controllers. + +NOTE: this is added specifically to veyron and not to rk3288 in +general since it's not known whether all rk3288 boards are designed to +support USB wakeup. It is plausible that some boards could shut down +important rails in S3. + +Also note that currently wakeup doesn't seem to happen unless you use +the "deep" suspend mode (where SDRAM is turned off). Presumably the +shallow suspend mode is gating some sort of clock that's important but +I couldn't easily figure out how to get it working. + +Signed-off-by: Douglas Anderson +Signed-off-by: Felipe Balbi +--- + arch/arm/boot/dts/rk3288-veyron.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index 1252522392c7..1d8bfed7830c 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -424,6 +424,7 @@ + + &usb_host1 { + status = "okay"; ++ snps,need-phy-for-wake; + }; + + &usb_otg { +@@ -432,6 +433,7 @@ + assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; + assigned-clock-parents = <&usbphy0>; + dr_mode = "host"; ++ snps,need-phy-for-wake; + }; + + &vopb { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch new file mode 100644 index 0000000..eb33aeb --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch @@ -0,0 +1,95 @@ +From 4db11c378ab1e170c3a197ea3719ffe54cd06637 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 19 Jun 2019 11:34:25 -0700 +Subject: [PATCH 51/54] ARM: dts: rockchip: Configure BT_DEV_WAKE in on + rk3288-veyron + +This is the other half of the hacky solution from commit f497ab6b4bb8 +("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on +veyron"). Specifically the LPM driver that the Broadcom Bluetooth +expects to have (but is missing in mainline) has two halves of the +equation: BT_HOST_WAKE and BT_DEV_WAKE. The BT_HOST_WAKE (which was +handled in the previous commit) is the one that lets the Bluetooth +wake the system up. The BT_DEV_WAKE (this patch) tells the Bluetooth +that it's OK to go into a low power mode. That means we were burning +a bit of extra power in S3 without this patch. Measurements are a bit +noisy, but it appears to be a few mA worth of difference. + +NOTE: Though these pins don't do much on systems with Marvell +Bluetooth, downstream kernels set it on all veyron boards so we'll do +the same. + +Signed-off-by: Douglas Anderson +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 ++ + arch/arm/boot/dts/rk3288-veyron.dtsi | 20 ++++++++++++++++++++ + 2 files changed, 22 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +index 5727017f34b2..1cadb522fd0d 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +@@ -237,6 +237,7 @@ + + /* Wake only */ + &suspend_l_wake ++ &bt_dev_wake_awake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ +@@ -246,6 +247,7 @@ + + /* Sleep only */ + &suspend_l_sleep ++ &bt_dev_wake_sleep + >; + + backlight { +diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi +index e2635ad574e7..53d2f2452868 100644 +--- a/arch/arm/boot/dts/rk3288-veyron.dtsi ++++ b/arch/arm/boot/dts/rk3288-veyron.dtsi +@@ -485,12 +485,18 @@ + &ddr0_retention + &ddrio_pwroff + &global_pwroff ++ ++ /* Wake only */ ++ &bt_dev_wake_awake + >; + pinctrl-1 = < + /* Common for sleep and wake, but no owners */ + &ddr0_retention + &ddrio_pwroff + &global_pwroff ++ ++ /* Sleep only */ ++ &bt_dev_wake_sleep + >; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { +@@ -596,6 +602,20 @@ + sdio0_clk: sdio0-clk { + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; + }; ++ ++ /* ++ * These pins are only present on very new veyron boards; on ++ * older boards bt_dev_wake is simply always high. Note that ++ * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt ++ * to map this pin everywhere ++ */ ++ bt_dev_wake_sleep: bt-dev-wake-sleep { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ ++ bt_dev_wake_awake: bt-dev-wake-awake { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; ++ }; + }; + + tpm { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0052-Revert-ARM-dts-rockchip-set-PWM-delay-backlight-sett.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0052-Revert-ARM-dts-rockchip-set-PWM-delay-backlight-sett.patch new file mode 100644 index 0000000..9ba8ec9 --- /dev/null +++ b/resources/BuildResources/patches-tested/DTS/5.x-dts/0052-Revert-ARM-dts-rockchip-set-PWM-delay-backlight-sett.patch @@ -0,0 +1,35 @@ +From fe32553c8704fe15effd6945afd5de893d417a80 Mon Sep 17 00:00:00 2001 +From: Matthias Kaehlcke +Date: Tue, 18 Jun 2019 11:45:31 -0700 +Subject: [PATCH 52/54] Revert "ARM: dts: rockchip: set PWM delay backlight + settings for Minnie" + +This reverts commit 288ceb85b505c19abe1895df068dda5ed20cf482. + +The commit assumes that the minnie panel is a AUO B101EAN01.1 (LVDS +interface), however it is a AUO B101EAN01.8 (eDP interface). The eDP +panel doesn't need the 200 ms delay. + +Signed-off-by: Matthias Kaehlcke +Reviewed-by: Enric Balletbo i Serra +Signed-off-by: Heiko Stuebner +--- + arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +index b2cc70a08554..9008e703c07e 100644 +--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts ++++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts +@@ -106,8 +106,6 @@ + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +- post-pwm-on-delay-ms = <200>; +- pwm-off-delay-ms = <200>; + }; + + &i2c_tunnel { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/0001-Fix-ath9k-dwc2-init-frame-overruns.patch b/resources/BuildResources/patches-tested/kernel/0001-Fix-ath9k-dwc2-init-frame-overruns.patch new file mode 100644 index 0000000..5dc44a8 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/0001-Fix-ath9k-dwc2-init-frame-overruns.patch @@ -0,0 +1,40 @@ +From 0a4c330869fbdd1a2372609cac13a98492e0e149 Mon Sep 17 00:00:00 2001 +From: Hal Emmerich +Date: Wed, 21 Aug 2019 16:52:41 -0500 +Subject: [PATCH] Fix ath9k dwc2 init frame overruns + +This is a workaround for ar9271 drvices using the open ath9k firmware +With the dwc2 usb driver these endpoints end up throwing piles of +frame overrun errors and prevent the ath9k firmware from communicating +properly with the c201 + +This fix elongates the microframes by 4 so the dwc2 and ath9k devices +communicate properly. In my testing this did not impact network speeds. +--- + drivers/usb/dwc2/hcd_queue.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c +index 68bbac6..8562db7 100644 +--- a/drivers/usb/dwc2/hcd_queue.c ++++ b/drivers/usb/dwc2/hcd_queue.c +@@ -1558,6 +1558,16 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, + device_ns += dwc_tt->usb_tt->think_time; + qh->device_us = NS_TO_US(device_ns); + ++ //Only enable workaround for highspeed devices, since only low and full speed devices so split, we can just check split ++ //The packets that fail right after the firmware is transferred are on an interrupt ep so we can use that to further narrow it down ++ //The ath9k device has issues with ep 3 and ep4 ++ if(!do_split && !ep_is_isoc && ep_is_int && (urb->pipe_info.ep_num == 3 || urb->pipe_info.ep_num == 4)){ ++ if (urb->interval == 1){ ++ urb->interval = 4; ++ dev_err(hsotg->dev, "PRAWNOS Set usb urb interval to %d\n", urb->interval); ++ } ++ } ++ + qh->device_interval = urb->interval; + qh->host_interval = urb->interval * (do_split ? 8 : 1); + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-clk/0001-clk-Tag-clk-core-files-with-SPDX.patch b/resources/BuildResources/patches-tested/kernel/5.x-clk/0001-clk-Tag-clk-core-files-with-SPDX.patch new file mode 100644 index 0000000..cd19a68 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-clk/0001-clk-Tag-clk-core-files-with-SPDX.patch @@ -0,0 +1,31 @@ +From ebafb63dc7759c4cc54065b5aa675080b5f453ce Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Tue, 11 Dec 2018 09:43:03 -0800 +Subject: [PATCH 1/3] clk: Tag clk core files with SPDX + +These are all GPL-2.0 files per the existing license text. Replace the +boiler plate with the tag. + +Signed-off-by: Stephen Boyd +--- + drivers/clk/clk-devres.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c +index 12c87457eca1..c9a86156ced8 100644 +--- a/drivers/clk/clk-devres.c ++++ b/drivers/clk/clk-devres.c +@@ -1,9 +1,4 @@ +-/* +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- */ +- ++// SPDX-License-Identifier: GPL-2.0 + #include + #include + #include +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-clk/0002-clk-Add-devm_-clk_get_optional-functions.patch b/resources/BuildResources/patches-tested/kernel/5.x-clk/0002-clk-Add-devm_-clk_get_optional-functions.patch new file mode 100644 index 0000000..1e00945 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-clk/0002-clk-Add-devm_-clk_get_optional-functions.patch @@ -0,0 +1,48 @@ +From 60b8f0ddf1a927ef02141a6610fd52575134f821 Mon Sep 17 00:00:00 2001 +From: Phil Edworthy +Date: Mon, 3 Dec 2018 11:13:09 +0000 +Subject: [PATCH 2/3] clk: Add (devm_)clk_get_optional() functions + +This adds clk_get_optional() and devm_clk_get_optional() functions to get +optional clocks. + +They behave the same as (devm_)clk_get() except where there is no clock +producer. In this case, instead of returning -ENOENT, the function +returns NULL. This makes error checking simpler and allows +clk_prepare_enable, etc to be called on the returned reference +without additional checks. + +Signed-off-by: Phil Edworthy +Reviewed-by: Andy Shevchenko +Cc: Russell King +[sboyd@kernel.org: Document in devres.txt] +Signed-off-by: Stephen Boyd +--- + drivers/clk/clk-devres.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c +index c9a86156ced8..daa1fc8fba53 100644 +--- a/drivers/clk/clk-devres.c ++++ b/drivers/clk/clk-devres.c +@@ -29,6 +29,17 @@ struct clk *devm_clk_get(struct device *dev, const char *id) + } + EXPORT_SYMBOL(devm_clk_get); + ++struct clk *devm_clk_get_optional(struct device *dev, const char *id) ++{ ++ struct clk *clk = devm_clk_get(dev, id); ++ ++ if (clk == ERR_PTR(-ENOENT)) ++ return NULL; ++ ++ return clk; ++} ++EXPORT_SYMBOL(devm_clk_get_optional); ++ + struct clk_bulk_devres { + struct clk_bulk_data *clks; + int num_clks; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0002-usb-dwc2-get-optional-vbus-supply-regulator-once.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0002-usb-dwc2-get-optional-vbus-supply-regulator-once.patch new file mode 100644 index 0000000..552c0d3 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0002-usb-dwc2-get-optional-vbus-supply-regulator-once.patch @@ -0,0 +1,68 @@ +From e0f681c2c11a25b76626cea77deb819a4754375d Mon Sep 17 00:00:00 2001 +From: Fabrice Gasnier +Date: Wed, 5 Sep 2018 13:40:02 +0200 +Subject: [PATCH 02/53] usb: dwc2: get optional vbus-supply regulator once + +Move devm_regulator_get_optional() call to probe routine. This avoids +'vbus-supply' regulator to be requested lots of times, upon each call +to dwc2_vbus_supply_init(), e.g. like with runtime pm. + +Fixes: 531ef5ebea96 ("usb: dwc2: add support for host mode external +vbus supply") + +Tested-by: Artur Petrosyan +Acked-by: Minas Harutyunyan +Signed-off-by: Fabrice Gasnier +Signed-off-by: Amelie Delaunay +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hcd.c | 12 +++--------- + drivers/usb/dwc2/platform.c | 8 ++++++++ + 2 files changed, 11 insertions(+), 9 deletions(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 5f23b933cafc..24aa5a3acf86 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -358,16 +358,10 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) + + static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) + { +- int ret; +- +- hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); +- if (IS_ERR(hsotg->vbus_supply)) { +- ret = PTR_ERR(hsotg->vbus_supply); +- hsotg->vbus_supply = NULL; +- return ret == -ENODEV ? 0 : ret; +- } ++ if (hsotg->vbus_supply) ++ return regulator_enable(hsotg->vbus_supply); + +- return regulator_enable(hsotg->vbus_supply); ++ return 0; + } + + static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg) +diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c +index 577642895b57..c0b64d483552 100644 +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -432,6 +432,14 @@ static int dwc2_driver_probe(struct platform_device *dev) + if (retval) + return retval; + ++ hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); ++ if (IS_ERR(hsotg->vbus_supply)) { ++ retval = PTR_ERR(hsotg->vbus_supply); ++ hsotg->vbus_supply = NULL; ++ if (retval != -ENODEV) ++ return retval; ++ } ++ + retval = dwc2_lowlevel_hw_enable(hsotg); + if (retval) + return retval; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0005-usb-dwc2-fix-unbalanced-use-of-external-vbus-supply.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0005-usb-dwc2-fix-unbalanced-use-of-external-vbus-supply.patch new file mode 100644 index 0000000..23093a6 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0005-usb-dwc2-fix-unbalanced-use-of-external-vbus-supply.patch @@ -0,0 +1,136 @@ +From cd7cd0e6cedfda8da6668a4af6748f96bbb6fed4 Mon Sep 17 00:00:00 2001 +From: Fabrice Gasnier +Date: Wed, 5 Sep 2018 13:40:05 +0200 +Subject: [PATCH 05/53] usb: dwc2: fix unbalanced use of external vbus-supply + +When using external vbus supply regulator, it should be enabled +synchronously with PWR bit in HPRT register. This also fixes +unbalanced use of this optional regulator (This can be reproduced +easily when unbinding the driver). + +Fixes: 531ef5ebea96 ("usb: dwc2: add support for host mode external +vbus supply") + +Tested-by: Artur Petrosyan +Acked-by: Minas Harutyunyan +Signed-off-by: Fabrice Gasnier +Signed-off-by: Amelie Delaunay +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hcd.c | 33 ++++++++++++++++++++++++++------- + 1 file changed, 26 insertions(+), 7 deletions(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 103a0521466b..dd82fa516f3f 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -3555,6 +3555,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, + u32 port_status; + u32 speed; + u32 pcgctl; ++ u32 pwr; + + switch (typereq) { + case ClearHubFeature: +@@ -3603,8 +3604,11 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); ++ pwr = hprt0 & HPRT0_PWR; + hprt0 &= ~HPRT0_PWR; + dwc2_writel(hsotg, hprt0, HPRT0); ++ if (pwr) ++ dwc2_vbus_supply_exit(hsotg); + break; + + case USB_PORT_FEAT_INDICATOR: +@@ -3814,8 +3818,11 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); ++ pwr = hprt0 & HPRT0_PWR; + hprt0 |= HPRT0_PWR; + dwc2_writel(hsotg, hprt0, HPRT0); ++ if (!pwr) ++ dwc2_vbus_supply_init(hsotg); + break; + + case USB_PORT_FEAT_RESET: +@@ -3832,6 +3839,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, + dwc2_writel(hsotg, 0, PCGCTL); + + hprt0 = dwc2_read_hprt0(hsotg); ++ pwr = hprt0 & HPRT0_PWR; + /* Clear suspend bit if resetting from suspend state */ + hprt0 &= ~HPRT0_SUSP; + +@@ -3845,6 +3853,8 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, + dev_dbg(hsotg->dev, + "In host mode, hprt0=%08x\n", hprt0); + dwc2_writel(hsotg, hprt0, HPRT0); ++ if (!pwr) ++ dwc2_vbus_supply_init(hsotg); + } + + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ +@@ -4384,6 +4394,7 @@ static int _dwc2_hcd_start(struct usb_hcd *hcd) + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + struct usb_bus *bus = hcd_to_bus(hcd); + unsigned long flags; ++ u32 hprt0; + int ret; + + dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); +@@ -4400,12 +4411,16 @@ static int _dwc2_hcd_start(struct usb_hcd *hcd) + + dwc2_hcd_reinit(hsotg); + +- /* enable external vbus supply before resuming root hub */ +- spin_unlock_irqrestore(&hsotg->lock, flags); +- ret = dwc2_vbus_supply_init(hsotg); +- if (ret) +- return ret; +- spin_lock_irqsave(&hsotg->lock, flags); ++ hprt0 = dwc2_read_hprt0(hsotg); ++ /* Has vbus power been turned on in dwc2_core_host_init ? */ ++ if (hprt0 & HPRT0_PWR) { ++ /* Enable external vbus supply before resuming root hub */ ++ spin_unlock_irqrestore(&hsotg->lock, flags); ++ ret = dwc2_vbus_supply_init(hsotg); ++ if (ret) ++ return ret; ++ spin_lock_irqsave(&hsotg->lock, flags); ++ } + + /* Initialize and connect root hub if one is not already attached */ + if (bus->root_hub) { +@@ -4427,6 +4442,7 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd) + { + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + unsigned long flags; ++ u32 hprt0; + + /* Turn off all host-specific interrupts */ + dwc2_disable_host_interrupts(hsotg); +@@ -4435,6 +4451,7 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd) + synchronize_irq(hcd->irq); + + spin_lock_irqsave(&hsotg->lock, flags); ++ hprt0 = dwc2_read_hprt0(hsotg); + /* Ensure hcd is disconnected */ + dwc2_hcd_disconnect(hsotg, true); + dwc2_hcd_stop(hsotg); +@@ -4443,7 +4460,9 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd) + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + spin_unlock_irqrestore(&hsotg->lock, flags); + +- dwc2_vbus_supply_exit(hsotg); ++ /* keep balanced supply init/exit by checking HPRT0_PWR */ ++ if (hprt0 & HPRT0_PWR) ++ dwc2_vbus_supply_exit(hsotg); + + usleep_range(1000, 3000); + } +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0006-usb-dwc2-Update-registers-definitions-to-support-ser.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0006-usb-dwc2-Update-registers-definitions-to-support-ser.patch new file mode 100644 index 0000000..e231c5f --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0006-usb-dwc2-Update-registers-definitions-to-support-ser.patch @@ -0,0 +1,40 @@ +From c464da0bff6ab6fd39b4603d017de940832bc388 Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 20:59:07 +0400 +Subject: [PATCH 06/53] usb: dwc2: Update registers definitions to support + service interval + +Added GHWCFG4_SERVICE_INTERVAL_SUPPORTED and +DCTL_SERVICE_INTERVAL_SUPPORTED bits definitions to support +service interval based scheduling. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hw.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h +index 0ca8e7bc7aaf..524629428439 100644 +--- a/drivers/usb/dwc2/hw.h ++++ b/drivers/usb/dwc2/hw.h +@@ -312,6 +312,7 @@ + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 + #define GHWCFG4_ACG_SUPPORTED BIT(12) + #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) ++#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 +@@ -443,6 +444,7 @@ + #define DCFG_DEVSPD_FS48 3 + + #define DCTL HSOTG_REG(0x804) ++#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19) + #define DCTL_PWRONPRGDONE BIT(11) + #define DCTL_CGOUTNAK BIT(10) + #define DCTL_SGOUTNAK BIT(9) +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0007-usb-dwc2-Add-core-parameter-for-service-interval-sup.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0007-usb-dwc2-Add-core-parameter-for-service-interval-sup.patch new file mode 100644 index 0000000..34f645e --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0007-usb-dwc2-Add-core-parameter-for-service-interval-sup.patch @@ -0,0 +1,118 @@ +From ca531bc2bfa655a1a0acaac4f7a6ea4b2111cc43 Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 20:59:34 +0400 +Subject: [PATCH 07/53] usb: dwc2: Add core parameter for service interval + support + +Added core parameter for service interval based scheduling. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 9 +++++++++ + drivers/usb/dwc2/debugfs.c | 1 + + drivers/usb/dwc2/gadget.c | 4 ++++ + drivers/usb/dwc2/params.c | 4 ++++ + 4 files changed, 18 insertions(+) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index cc9c93affa14..2678dc9d559b 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -416,6 +416,9 @@ enum dwc2_ep0_state { + * back to DWC2_SPEED_PARAM_HIGH while device is gone. + * 0 - No (default) + * 1 - Yes ++ * @service_interval: Enable service interval based scheduling. ++ * 0 - No ++ * 1 - Yes + * + * The following parameters may be specified when starting the module. These + * parameters define how the DWC_otg controller should be configured. A +@@ -461,6 +464,7 @@ struct dwc2_core_params { + bool lpm_clock_gating; + bool besl; + bool hird_threshold_en; ++ bool service_interval; + u8 hird_threshold; + bool activate_stm_fs_transceiver; + bool ipg_isoc_en; +@@ -605,6 +609,10 @@ struct dwc2_core_params { + * FIFO sizing is enabled 16 to 32768 + * Actual maximum value is autodetected and also + * the default. ++ * @service_interval_mode: For enabling service interval based scheduling in the ++ * controller. ++ * 0 - Disable ++ * 1 - Enable + */ + struct dwc2_hw_params { + unsigned op_mode:3; +@@ -635,6 +643,7 @@ struct dwc2_hw_params { + unsigned utmi_phy_data_width:2; + unsigned lpm_mode:1; + unsigned ipg_isoc_en:1; ++ unsigned service_interval_mode:1; + u32 snpsid; + u32 dev_ep_dirs; + u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; +diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c +index 22d015b0424f..7f62f4cdc265 100644 +--- a/drivers/usb/dwc2/debugfs.c ++++ b/drivers/usb/dwc2/debugfs.c +@@ -701,6 +701,7 @@ static int params_show(struct seq_file *seq, void *v) + print_param(seq, p, besl); + print_param(seq, p, hird_threshold_en); + print_param(seq, p, hird_threshold); ++ print_param(seq, p, service_interval); + print_param(seq, p, host_dma); + print_param(seq, p, g_dma); + print_param(seq, p, g_dma_desc); +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 79189db4bf17..12032f0488d8 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -3323,6 +3323,10 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, + dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); + } + ++ /* Enable Service Interval mode if supported */ ++ if (using_desc_dma(hsotg) && hsotg->params.service_interval) ++ dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); ++ + dwc2_writel(hsotg, 0, DAINTMSK); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index bf7052e037d6..dd3c10d537e2 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -299,6 +299,7 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) + p->hird_threshold_en = true; + p->hird_threshold = 4; + p->ipg_isoc_en = false; ++ p->service_interval = false; + p->max_packet_count = hw->max_packet_count; + p->max_transfer_size = hw->max_transfer_size; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; +@@ -592,6 +593,7 @@ static void dwc2_check_params(struct dwc2_hsotg *hsotg) + CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); + CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); + CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); ++ CHECK_BOOL(service_interval, hw->service_interval_mode); + CHECK_RANGE(max_packet_count, + 15, hw->max_packet_count, + hw->max_packet_count); +@@ -780,6 +782,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) + GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; + hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); + hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); ++ hw->service_interval_mode = !!(hwcfg4 & ++ GHWCFG4_SERVICE_INTERVAL_SUPPORTED); + + /* fifo sizes */ + hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0008-usb-dwc2-Add-dwc2_gadget_dec_frame_num_by_one-functi.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0008-usb-dwc2-Add-dwc2_gadget_dec_frame_num_by_one-functi.patch new file mode 100644 index 0000000..4fd4dd6 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0008-usb-dwc2-Add-dwc2_gadget_dec_frame_num_by_one-functi.patch @@ -0,0 +1,50 @@ +From 9d630b9cde28dc261cdfc608ed68ef5487404422 Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:00:03 +0400 +Subject: [PATCH 08/53] usb: dwc2: Add dwc2_gadget_dec_frame_num_by_one() + function + +Added dwc2_gadget_dec_frame_num_by_one() function in gadget.c. +This function will be used to calculate descriptor frame number field +value. For service interval mode frame number in descriptor should point +to last (u)frame in the interval. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 12032f0488d8..71f097d89001 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -123,6 +123,24 @@ static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) + } + + /** ++ * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number ++ * by one. ++ * @hs_ep: The endpoint. ++ * ++ * This function used in service interval based scheduling flow to calculate ++ * descriptor frame number filed value. For service interval mode frame ++ * number in descriptor should point to last (u)frame in the interval. ++ * ++ */ ++static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) ++{ ++ if (hs_ep->target_frame) ++ hs_ep->target_frame -= 1; ++ else ++ hs_ep->target_frame = DSTS_SOFFN_LIMIT; ++} ++ ++/** + * dwc2_hsotg_en_gsint - enable one or more of the general interrupt + * @hsotg: The device state + * @ints: A bitmask of the interrupts to enable +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0009-usb-dwc2-Update-target-u-frame-calculation.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0009-usb-dwc2-Update-target-u-frame-calculation.patch new file mode 100644 index 0000000..707a2cd --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0009-usb-dwc2-Update-target-u-frame-calculation.patch @@ -0,0 +1,46 @@ +From 48dac4e4a5eed3fa478db2c59945b6283281566d Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:00:33 +0400 +Subject: [PATCH 09/53] usb: dwc2: Update target (u)frame calculation + +In service interval based scheduling target (u)frame must be +set as a last frame in this the service interval. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 71f097d89001..9de16453a890 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -2830,6 +2830,23 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) + if (using_desc_dma(hsotg)) { + hs_ep->target_frame = hsotg->frame_number; + dwc2_gadget_incr_frame_num(hs_ep); ++ ++ /* In service interval mode target_frame must ++ * be set to last (u)frame of the service interval. ++ */ ++ if (hsotg->params.service_interval) { ++ /* Set target_frame to the first (u)frame of ++ * the service interval ++ */ ++ hs_ep->target_frame &= ~hs_ep->interval + 1; ++ ++ /* Set target_frame to the last (u)frame of ++ * the service interval ++ */ ++ dwc2_gadget_incr_frame_num(hs_ep); ++ dwc2_gadget_dec_frame_num_by_one(hs_ep); ++ } ++ + dwc2_gadget_start_isoc_ddma(hs_ep); + return; + } +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0010-usb-dwc2-Add-definitions-for-new-registers.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0010-usb-dwc2-Add-definitions-for-new-registers.patch new file mode 100644 index 0000000..c3de60f --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0010-usb-dwc2-Add-definitions-for-new-registers.patch @@ -0,0 +1,47 @@ +From 392af0232640abf7acd12754515f8363c4c0df67 Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:01:01 +0400 +Subject: [PATCH 10/53] usb: dwc2: Add definitions for new registers + +New registers were added to dwc otg core. + +GREFCLK - This register used to control ref_clk parameters. + +GINTSTS2 - New WKUP_ALERT interrupt was added. + +GINTMSK2 - Mask register for GINTSTS2. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hw.h | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h +index 524629428439..2b1ea441b7d4 100644 +--- a/drivers/usb/dwc2/hw.h ++++ b/drivers/usb/dwc2/hw.h +@@ -405,6 +405,19 @@ + #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) + #define ADPCTL_PRB_DSCHRG_SHIFT 0 + ++#define GREFCLK HSOTG_REG(0x0064) ++#define GREFCLK_REFCLKPER_MASK (0x1ffff << 15) ++#define GREFCLK_REFCLKPER_SHIFT 15 ++#define GREFCLK_REF_CLK_MODE BIT(14) ++#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff) ++#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0 ++ ++#define GINTMSK2 HSOTG_REG(0x0068) ++#define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0) ++ ++#define GINTSTS2 HSOTG_REG(0x006c) ++#define GINTSTS2_WKUP_ALERT_INT BIT(0) ++ + #define HPTXFSIZ HSOTG_REG(0x100) + /* Use FIFOSIZE_* constants to access this register */ + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0011-usb-dwc2-gadget-Add-parameters-for-GREFCLK-register.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0011-usb-dwc2-gadget-Add-parameters-for-GREFCLK-register.patch new file mode 100644 index 0000000..c53d618 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0011-usb-dwc2-gadget-Add-parameters-for-GREFCLK-register.patch @@ -0,0 +1,68 @@ +From f3a61e4e033e808e7ac1239b151ec46f833fff4a Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:01:31 +0400 +Subject: [PATCH 11/53] usb: dwc2: gadget: Add parameters for GREFCLK register + +Added ref_clk_per and sof_cnt_wkup_alert parameters in +dwc2_core_params struct and set default values. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 18 ++++++++++++++++++ + drivers/usb/dwc2/params.c | 2 ++ + 2 files changed, 20 insertions(+) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 2678dc9d559b..655f5274e801 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -393,6 +393,20 @@ enum dwc2_ep0_state { + * 0 - No + * 1 - Yes + * @hird_threshold: Value of BESL or HIRD Threshold. ++ * @ref_clk_per: Indicates in terms of pico seconds the period ++ * of ref_clk. ++ * 62500 - 16MHz ++ * 58823 - 17MHz ++ * 52083 - 19.2MHz ++ * 50000 - 20MHz ++ * 41666 - 24MHz ++ * 33333 - 30MHz (default) ++ * 25000 - 40MHz ++ * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which ++ * the controller should generate an interrupt if the ++ * device had been in L1 state until that period. ++ * This is used by SW to initiate Remote WakeUp in the ++ * controller so as to sync to the uF number from the host. + * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO + * register. + * 0 - Deactivate the transceiver (default) +@@ -472,6 +486,10 @@ struct dwc2_core_params { + u32 max_transfer_size; + u32 ahbcfg; + ++ /* GREFCLK parameters */ ++ u32 ref_clk_per; ++ u16 sof_cnt_wkup_alert; ++ + /* Host parameters */ + bool host_dma; + bool dma_desc_enable; +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index dd3c10d537e2..d150984406ee 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -303,6 +303,8 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) + p->max_packet_count = hw->max_packet_count; + p->max_transfer_size = hw->max_transfer_size; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; ++ p->ref_clk_per = 33333; ++ p->sof_cnt_wkup_alert = 100; + + if ((hsotg->dr_mode == USB_DR_MODE_HOST) || + (hsotg->dr_mode == USB_DR_MODE_OTG)) { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0012-usb-dwc2-gadget-Program-GREFCLK-register.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0012-usb-dwc2-gadget-Program-GREFCLK-register.patch new file mode 100644 index 0000000..7dbbb81 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0012-usb-dwc2-gadget-Program-GREFCLK-register.patch @@ -0,0 +1,80 @@ +From 15d9dbf8cbd4fc777a7fc92209903dbb47d0783e Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:01:59 +0400 +Subject: [PATCH 12/53] usb: dwc2: gadget: Program GREFCLK register + +Added dwc2_gadget_program_ref_clk function to program GREFCLK +register in device mode. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 2 ++ + drivers/usb/dwc2/gadget.c | 23 +++++++++++++++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 655f5274e801..30bab8463c96 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -1381,6 +1381,7 @@ int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); + int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); + int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); + void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); ++void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); + #else + static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) + { return 0; } +@@ -1415,6 +1416,7 @@ static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) + static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) + { return 0; } + static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} ++static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} + #endif + + #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 9de16453a890..e8dd6897e2c3 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -3418,6 +3418,10 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, + /* configure the core to support LPM */ + dwc2_gadget_init_lpm(hsotg); + ++ /* program GREFCLK register if needed */ ++ if (using_desc_dma(hsotg) && hsotg->params.service_interval) ++ dwc2_gadget_program_ref_clk(hsotg); ++ + /* must be at-least 3ms to allow bus to see disconnect */ + mdelay(3); + +@@ -5002,6 +5006,25 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) + } + + /** ++ * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode ++ * ++ * @hsotg: Programming view of DWC_otg controller ++ * ++ */ ++void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) ++{ ++ u32 val = 0; ++ ++ val |= GREFCLK_REF_CLK_MODE; ++ val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; ++ val |= hsotg->params.sof_cnt_wkup_alert << ++ GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; ++ ++ dwc2_writel(hsotg, val, GREFCLK); ++ dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); ++} ++ ++/** + * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. + * + * @hsotg: Programming view of the DWC_otg controller +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0013-usb-dwc2-gadget-enable-WKUP_ALERT-interrupt.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0013-usb-dwc2-gadget-enable-WKUP_ALERT-interrupt.patch new file mode 100644 index 0000000..c17318e --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0013-usb-dwc2-gadget-enable-WKUP_ALERT-interrupt.patch @@ -0,0 +1,37 @@ +From 4abe453750db8ada8b0a56c45c89ab18920e9a80 Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:02:28 +0400 +Subject: [PATCH 13/53] usb: dwc2: gadget: enable WKUP_ALERT interrupt + +WKUP_ALERT interrupt should be unmask when lpm mode is enabled. + +This interrupt is asserted when the device is in L1 for the duration +mentioned in GREFCLK.SOF_CNN_WKUP_ALERT. This is used to alert SW to +initiate Remote wake up so that the device resumes in time in order not +to lose sync with the host frame number. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index e8dd6897e2c3..24bd9fdabc67 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -5003,6 +5003,10 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) + val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; + dwc2_writel(hsotg, val, GLPMCFG); + dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); ++ ++ /* Unmask WKUP_ALERT Interrupt */ ++ if (hsotg->params.service_interval) ++ dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); + } + + /** +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0014-usb-dwc2-gadget-Add-handler-for-WkupAlert-interrupt.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0014-usb-dwc2-gadget-Add-handler-for-WkupAlert-interrupt.patch new file mode 100644 index 0000000..9f47c2f --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0014-usb-dwc2-gadget-Add-handler-for-WkupAlert-interrupt.patch @@ -0,0 +1,62 @@ +From 187c5298a12292eab55e3eb09e70e2b145646bcc Mon Sep 17 00:00:00 2001 +From: Grigor Tovmasyan +Date: Wed, 29 Aug 2018 21:02:57 +0400 +Subject: [PATCH 14/53] usb: dwc2: gadget: Add handler for WkupAlert interrupt + +Added interrupt handler for WkupAlert interrupt. + +This interrupt should initiate Remote Wake up. + +Acked-by: Minas Harutyunyan +Signed-off-by: Grigor Tovmasyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 24bd9fdabc67..2d6d2c8244de 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -246,6 +246,27 @@ int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) + } + + /** ++ * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt ++ * ++ * @hsotg: Programming view of the DWC_otg controller ++ * ++ */ ++static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) ++{ ++ u32 gintsts2; ++ u32 gintmsk2; ++ ++ gintsts2 = dwc2_readl(hsotg, GINTSTS2); ++ gintmsk2 = dwc2_readl(hsotg, GINTMSK2); ++ ++ if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { ++ dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); ++ dwc2_clear_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); ++ dwc2_set_bit(hsotg, DCFG, DCTL_RMTWKUPSIG); ++ } ++} ++ ++/** + * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode + * TX FIFOs + * +@@ -3730,6 +3751,10 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) + if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) + goto irq_retry; + ++ /* Check WKUP_ALERT interrupt*/ ++ if (hsotg->params.service_interval) ++ dwc2_gadget_wkup_alert_handler(hsotg); ++ + spin_unlock(&hsotg->lock); + + return IRQ_HANDLED; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0017-usb-dwc2-gadget-Fix-WkupAlert-interrupt-handler.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0017-usb-dwc2-gadget-Fix-WkupAlert-interrupt-handler.patch new file mode 100644 index 0000000..d02306d --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0017-usb-dwc2-gadget-Fix-WkupAlert-interrupt-handler.patch @@ -0,0 +1,36 @@ +From d64bc8ee92856e39b3150d93e244ca8239ae6ada Mon Sep 17 00:00:00 2001 +From: Artur Petrosyan +Date: Fri, 2 Nov 2018 11:29:48 -0400 +Subject: [PATCH 17/53] usb: dwc2: gadget: Fix WkupAlert interrupt handler. + +According to the databook DCTL_RMTWKUPSIG bit +is defined in DCTL register not in DCFG. + +Updated setting DCTL_RMTWKUPSIG bit to DCTL +register. + +Fixes: 187c5298a122 ("usb: dwc2: gadget: Add handler for WkupAlert interrupt") + +Signed-off-by: Artur Petrosyan +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 2d6d2c8244de..6bd4054e894d 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -262,7 +262,7 @@ static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) + if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { + dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); + dwc2_clear_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); +- dwc2_set_bit(hsotg, DCFG, DCTL_RMTWKUPSIG); ++ dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); + } + } + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0018-usb-dwc2-gadget-Accept-LPM-token-when-TxFIFO-is-not-.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0018-usb-dwc2-gadget-Accept-LPM-token-when-TxFIFO-is-not-.patch new file mode 100644 index 0000000..4b28345 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0018-usb-dwc2-gadget-Accept-LPM-token-when-TxFIFO-is-not-.patch @@ -0,0 +1,55 @@ +From 9aed8c08c82d8498769119b73358d070a7cbb54c Mon Sep 17 00:00:00 2001 +From: Artur Petrosyan +Date: Fri, 2 Nov 2018 11:29:55 -0400 +Subject: [PATCH 18/53] usb: dwc2: gadget: Accept LPM token when TxFIFO is not + empty + +Set GLPMCFG_LPM_ACCEPT_CTRL_ISOC bit in GLPMCFG register +to accept LPM token during ISOC transfers when TxFIFO is +not empty. + +- Added two definitions. + #define GLPMCFG_LPM_ACCEPT_CTRL_CONTROL BIT(21) + #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22) + This patch uses GLPMCFG_LPM_ACCEPT_CTRL_ISOC. + GLPMCFG_LPM_ACCEPT_CTRL_CONTROL is defined for further use. + +- Added setting GLPMCFG_LPM_ACCEPT_CTRL_ISOC bit in GLPMCFG + register in dwc2_gadget_init_lpm function. + +Signed-off-by: Artur Petrosyan +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 1 + + drivers/usb/dwc2/hw.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 6bd4054e894d..94f3ba995580 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -5026,6 +5026,7 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) + val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; + val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; + val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; ++ val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; + dwc2_writel(hsotg, val, GLPMCFG); + dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); + +diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h +index 2b1ea441b7d4..98af924a9a5c 100644 +--- a/drivers/usb/dwc2/hw.h ++++ b/drivers/usb/dwc2/hw.h +@@ -333,6 +333,8 @@ + #define GLPMCFG_SNDLPM BIT(24) + #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21) + #define GLPMCFG_RETRY_CNT_SHIFT 21 ++#define GLPMCFG_LPM_ACCEPT_CTRL_CONTROL BIT(21) ++#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22) + #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17) + #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17 + #define GLPMCFG_L1RESUMEOK BIT(16) +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0023-usb-dwc2-gadget-Fix-Remote-Wakeup-interrupt-bit-clea.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0023-usb-dwc2-gadget-Fix-Remote-Wakeup-interrupt-bit-clea.patch new file mode 100644 index 0000000..b1f6090 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0023-usb-dwc2-gadget-Fix-Remote-Wakeup-interrupt-bit-clea.patch @@ -0,0 +1,33 @@ +From 87b6d2c56825c3119a0e64cc208ae6d795810a2e Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Wed, 12 Dec 2018 16:44:32 +0400 +Subject: [PATCH 23/53] usb: dwc2: gadget: Fix Remote Wakeup interrupt bit + clearing + +To clear GINTSTS2_WKUP_ALERT_INT bit in GINTSTS2 register +require to write 1. This bit is implemented as "Write to clear". + +Fixes: 187c5298a122 ("usb: dwc2: gadget: Add handler for WkupAlert interrupt") + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 68ad75a7460d..55ef3cc2701b 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -261,7 +261,7 @@ static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) + + if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { + dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); +- dwc2_clear_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); ++ dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); + dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); + } + } +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0024-USB-add-missing-SPDX-lines-to-Kconfig-and-Makefiles.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0024-USB-add-missing-SPDX-lines-to-Kconfig-and-Makefiles.patch new file mode 100644 index 0000000..c146380 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0024-USB-add-missing-SPDX-lines-to-Kconfig-and-Makefiles.patch @@ -0,0 +1,27 @@ +From cae8dc3b685fb24f61f09b7197c6a383a66cff2c Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Thu, 17 Jan 2019 09:23:50 +0100 +Subject: [PATCH 24/53] USB: add missing SPDX lines to Kconfig and Makefiles + +There are a few remaining drivers/usb/ files that do not have SPDX +identifiers in them, all of these are either Kconfig or Makefiles. Add +the correct GPL-2.0 identifier to them to make scanning tools happy. + +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc2/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig +index b6a495e98fd8..68d095ae2865 100644 +--- a/drivers/usb/dwc2/Kconfig ++++ b/drivers/usb/dwc2/Kconfig +@@ -1,3 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ + config USB_DWC2 + tristate "DesignWare USB2 DRD Core Support" + depends on HAS_DMA +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0025-usb-dwc2-Fix-EP-TxFIFO-number-setting.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0025-usb-dwc2-Fix-EP-TxFIFO-number-setting.patch new file mode 100644 index 0000000..c60f385 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0025-usb-dwc2-Fix-EP-TxFIFO-number-setting.patch @@ -0,0 +1,31 @@ +From 97311c8f8b6e26d5ba6508f0df430ad80fc59327 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Thu, 31 Jan 2019 18:28:07 +0400 +Subject: [PATCH 25/53] usb: dwc2: Fix EP TxFIFO number setting + +In case when some EP IN is frequently reused, i.e. enabled/disabled by +function driver. It is required to clear TxFIFO number field in DIEPCTL +register before setting new number. Otherwise there is probability to +have same TxFIFO number for different EP's because of OR operator. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 55ef3cc2701b..e15d8a462085 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -4005,6 +4005,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, + ret = -ENOMEM; + goto error1; + } ++ epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); + hsotg->fifo_map |= 1 << fifo_index; + epctrl |= DXEPCTL_TXFNUM(fifo_index); + hs_ep->fifo_index = fifo_index; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0026-usb-dwc2-gadget-Add-scatter-gather-mode.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0026-usb-dwc2-gadget-Add-scatter-gather-mode.patch new file mode 100644 index 0000000..ab76ce2 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0026-usb-dwc2-gadget-Add-scatter-gather-mode.patch @@ -0,0 +1,212 @@ +From 10209abe87f5ebfd482a00323f5236d6094d0865 Mon Sep 17 00:00:00 2001 +From: Andrzej Pietrasiewicz +Date: Mon, 21 Jan 2019 14:44:47 +0100 +Subject: [PATCH 26/53] usb: dwc2: gadget: Add scatter-gather mode + +This patch adds support for transferring requests, which are +non-contiguous in physical memory, i.e. the data buffer is described by +a scatter-list. This allows transferring large requests without relying +on error-prone contiguous buffer allocations. This way of allocating +requests is already implemented in functionfs and TCM USB functions and +automatically used if UDC driver advertises scatter-gather suppport. + +Signed-off-by: Andrzej Pietrasiewicz +[mszyprow: fixed null pointer issue, rewrote commit message] +Signed-off-by: Marek Szyprowski +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 113 +++++++++++++++++++++++++++++++--------------- + 1 file changed, 77 insertions(+), 36 deletions(-) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index e15d8a462085..6812a8a3a98b 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -768,22 +768,13 @@ static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) + return desc_size; + } + +-/* +- * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. +- * @hs_ep: The endpoint +- * @dma_buff: DMA address to use +- * @len: Length of the transfer +- * +- * This function will iterate over descriptor chain and fill its entries +- * with corresponding information based on transfer data. +- */ +-static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, ++static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, ++ struct dwc2_dma_desc **desc, + dma_addr_t dma_buff, +- unsigned int len) ++ unsigned int len, ++ bool true_last) + { +- struct dwc2_hsotg *hsotg = hs_ep->parent; + int dir_in = hs_ep->dir_in; +- struct dwc2_dma_desc *desc = hs_ep->desc_list; + u32 mps = hs_ep->ep.maxpacket; + u32 maxsize = 0; + u32 offset = 0; +@@ -798,39 +789,77 @@ static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, + hs_ep->desc_count = 1; + + for (i = 0; i < hs_ep->desc_count; ++i) { +- desc->status = 0; +- desc->status |= (DEV_DMA_BUFF_STS_HBUSY ++ (*desc)->status = 0; ++ (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY + << DEV_DMA_BUFF_STS_SHIFT); + + if (len > maxsize) { + if (!hs_ep->index && !dir_in) +- desc->status |= (DEV_DMA_L | DEV_DMA_IOC); ++ (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); + +- desc->status |= (maxsize << +- DEV_DMA_NBYTES_SHIFT & mask); +- desc->buf = dma_buff + offset; ++ (*desc)->status |= ++ maxsize << DEV_DMA_NBYTES_SHIFT & mask; ++ (*desc)->buf = dma_buff + offset; + + len -= maxsize; + offset += maxsize; + } else { +- desc->status |= (DEV_DMA_L | DEV_DMA_IOC); ++ if (true_last) ++ (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); + + if (dir_in) +- desc->status |= (len % mps) ? DEV_DMA_SHORT : +- ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); +- if (len > maxsize) +- dev_err(hsotg->dev, "wrong len %d\n", len); ++ (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : ++ ((hs_ep->send_zlp && true_last) ? ++ DEV_DMA_SHORT : 0); + +- desc->status |= ++ (*desc)->status |= + len << DEV_DMA_NBYTES_SHIFT & mask; +- desc->buf = dma_buff + offset; ++ (*desc)->buf = dma_buff + offset; + } + +- desc->status &= ~DEV_DMA_BUFF_STS_MASK; +- desc->status |= (DEV_DMA_BUFF_STS_HREADY ++ (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; ++ (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY + << DEV_DMA_BUFF_STS_SHIFT); +- desc++; ++ (*desc)++; ++ } ++} ++ ++/* ++ * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. ++ * @hs_ep: The endpoint ++ * @ureq: Request to transfer ++ * @offset: offset in bytes ++ * @len: Length of the transfer ++ * ++ * This function will iterate over descriptor chain and fill its entries ++ * with corresponding information based on transfer data. ++ */ ++static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, ++ struct usb_request *ureq, ++ unsigned int offset, ++ unsigned int len) ++{ ++ struct dwc2_dma_desc *desc = hs_ep->desc_list; ++ struct scatterlist *sg; ++ int i; ++ u8 desc_count = 0; ++ ++ /* non-DMA sg buffer */ ++ if (!ureq->num_sgs) { ++ dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, ++ ureq->dma + offset, len, true); ++ return; + } ++ ++ /* DMA sg buffer */ ++ for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { ++ dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, ++ sg_dma_address(sg) + sg->offset, sg_dma_len(sg), ++ sg_is_last(sg)); ++ desc_count += hs_ep->desc_count; ++ } ++ ++ hs_ep->desc_count = desc_count; + } + + /* +@@ -944,7 +973,13 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) + + hs_ep->next_desc = 0; + list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { +- ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, ++ dma_addr_t dma_addr = hs_req->req.dma; ++ ++ if (hs_req->req.num_sgs) { ++ WARN_ON(hs_req->req.num_sgs > 1); ++ dma_addr = sg_dma_address(hs_req->req.sg); ++ } ++ ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, + hs_req->req.length); + if (ret) + break; +@@ -1100,7 +1135,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, + offset = ureq->actual; + + /* Fill DDMA chain entries */ +- dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, ++ dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq, offset, + length); + + /* write descriptor chain address to control register */ +@@ -1399,7 +1434,13 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, + */ + if (using_desc_dma(hs) && hs_ep->isochronous) { + if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { +- dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, ++ dma_addr_t dma_addr = hs_req->req.dma; ++ ++ if (hs_req->req.num_sgs) { ++ WARN_ON(hs_req->req.num_sgs > 1); ++ dma_addr = sg_dma_address(hs_req->req.sg); ++ } ++ dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, + hs_req->req.length); + } + return 0; +@@ -1987,13 +2028,12 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, + dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", + index); + if (using_desc_dma(hsotg)) { +- /* Not specific buffer needed for ep0 ZLP */ +- dma_addr_t dma = hs_ep->desc_list_dma; +- + if (!index) + dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); + +- dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); ++ /* Not specific buffer needed for ep0 ZLP */ ++ dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &hs_ep->desc_list, ++ hs_ep->desc_list_dma, 0, true); + } else { + dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(0), +@@ -4386,6 +4426,7 @@ static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, + hsotg->enabled = 0; + spin_unlock_irqrestore(&hsotg->lock, flags); + ++ gadget->sg_supported = using_desc_dma(hsotg); + dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); + + return 0; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0027-usb-dwc2-use-struct_size-in-kzalloc.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0027-usb-dwc2-use-struct_size-in-kzalloc.patch new file mode 100644 index 0000000..0f27d37 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0027-usb-dwc2-use-struct_size-in-kzalloc.patch @@ -0,0 +1,52 @@ +From eeca7606dd6e2445f505903f235e908eb7b78dfc Mon Sep 17 00:00:00 2001 +From: "Gustavo A. R. Silva" +Date: Mon, 18 Feb 2019 12:59:37 -0600 +Subject: [PATCH 27/53] usb: dwc2: use struct_size() in kzalloc() + +One of the more common cases of allocation size calculations is finding +the size of a structure that has a zero-sized array at the end, along +with memory for some number of elements for that array. For example: + +struct foo { + int stuff; + struct boo entry[]; +}; + +size = sizeof(struct foo) + count * sizeof(struct boo); +instance = kzalloc(size, GFP_KERNEL); + +Instead of leaving these open-coded and prone to type mistakes, we can +now use the new struct_size() helper: + +instance = kzalloc(struct_size(instance, entry, count), GFP_KERNEL); + +Notice that, in this case, variable size is not necessary, hence +it is removed. + +This code was detected with the help of Coccinelle. + +Signed-off-by: Gustavo A. R. Silva +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc2/hcd.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index dd82fa516f3f..3f087962f498 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -3981,10 +3981,8 @@ static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, + gfp_t mem_flags) + { + struct dwc2_hcd_urb *urb; +- u32 size = sizeof(*urb) + iso_desc_count * +- sizeof(struct dwc2_hcd_iso_packet_desc); + +- urb = kzalloc(size, mem_flags); ++ urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags); + if (urb) + urb->packet_count = iso_desc_count; + return urb; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0028-usb-dwc2-Add-Amlogic-G12A-DWC2-Params.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0028-usb-dwc2-Add-Amlogic-G12A-DWC2-Params.patch new file mode 100644 index 0000000..bc8753d --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0028-usb-dwc2-Add-Amlogic-G12A-DWC2-Params.patch @@ -0,0 +1,52 @@ +From fc4e326ee72cc36c942333c65d851247b31c567b Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Tue, 23 Apr 2019 10:51:26 +0200 +Subject: [PATCH 28/53] usb: dwc2: Add Amlogic G12A DWC2 Params + +This patchs sets the params for the DWC2 Controller found in the +Amlogic G12A SoC family. + +It mainly sets the settings reported incorrect by the driver, +leaving the remaining detected automatically by the driver and +provided by the DT node. + +Signed-off-by: Neil Armstrong +Acked-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/params.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index 24ff5f21cb25..442113246cba 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -121,6 +121,16 @@ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; + } + ++static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->lpm = false; ++ p->lpm_clock_gating = false; ++ p->besl = false; ++ p->hird_threshold_en = false; ++} ++ + static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) + { + struct dwc2_core_params *p = &hsotg->params; +@@ -167,6 +177,8 @@ const struct of_device_id dwc2_of_match_table[] = { + .data = dwc2_set_amlogic_params }, + { .compatible = "amlogic,meson-gxbb-usb", + .data = dwc2_set_amlogic_params }, ++ { .compatible = "amlogic,meson-g12a-usb", ++ .data = dwc2_set_amlogic_g12a_params }, + { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, + { .compatible = "st,stm32f4x9-fsotg", + .data = dwc2_set_stm32f4x9_fsotg_params }, +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0029-usb-dwc2-bus-suspend-resume-for-hosts-with-DWC2_POWE.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0029-usb-dwc2-bus-suspend-resume-for-hosts-with-DWC2_POWE.patch new file mode 100644 index 0000000..3e0163e --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0029-usb-dwc2-bus-suspend-resume-for-hosts-with-DWC2_POWE.patch @@ -0,0 +1,180 @@ +From 6f6d70597c15b2a406afa541517e6ad35f56a8a3 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 17 Apr 2019 17:13:52 -0700 +Subject: [PATCH 29/53] usb: dwc2: bus suspend/resume for hosts with + DWC2_POWER_DOWN_PARAM_NONE + +This is an attempt to rehash commit 0cf884e819e0 ("usb: dwc2: add bus +suspend/resume for dwc2") on ToT. That commit was reverted in commit +b0bb9bb6ce01 ("Revert "usb: dwc2: add bus suspend/resume for dwc2"") +because apparently it broke the Altera SOCFPGA. + +With all the changes that have happened to dwc2 in the meantime, it's +possible that the Altera SOCFPGA will just magically work with this +change now. ...and it would be good to get bus suspend/resume +implemented. + +This change is a forward port of one that's been living in the Chrome +OS 3.14 kernel tree. + +Signed-off-by: Douglas Anderson +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hcd.c | 84 +++++++++++++++++++++++++++++++------------------- + 1 file changed, 53 insertions(+), 31 deletions(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 3f087962f498..8667ddf3ca74 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -4471,6 +4471,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd) + unsigned long flags; + int ret = 0; + u32 hprt0; ++ u32 pcgctl; + + spin_lock_irqsave(&hsotg->lock, flags); + +@@ -4486,7 +4487,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd) + if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) + goto unlock; + +- if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) ++ if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) + goto skip_power_saving; + + /* +@@ -4495,21 +4496,35 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd) + */ + if (!hsotg->bus_suspended) { + hprt0 = dwc2_read_hprt0(hsotg); +- hprt0 |= HPRT0_SUSP; +- hprt0 &= ~HPRT0_PWR; +- dwc2_writel(hsotg, hprt0, HPRT0); +- spin_unlock_irqrestore(&hsotg->lock, flags); +- dwc2_vbus_supply_exit(hsotg); +- spin_lock_irqsave(&hsotg->lock, flags); ++ if (hprt0 & HPRT0_CONNSTS) { ++ hprt0 |= HPRT0_SUSP; ++ if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) ++ hprt0 &= ~HPRT0_PWR; ++ dwc2_writel(hsotg, hprt0, HPRT0); ++ } ++ if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) { ++ spin_unlock_irqrestore(&hsotg->lock, flags); ++ dwc2_vbus_supply_exit(hsotg); ++ spin_lock_irqsave(&hsotg->lock, flags); ++ } else { ++ pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl |= PCGCTL_STOPPCLK; ++ writel(pcgctl, hsotg->regs + PCGCTL); ++ } + } + +- /* Enter partial_power_down */ +- ret = dwc2_enter_partial_power_down(hsotg); +- if (ret) { +- if (ret != -ENOTSUPP) +- dev_err(hsotg->dev, +- "enter partial_power_down failed\n"); +- goto skip_power_saving; ++ if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) { ++ /* Enter partial_power_down */ ++ ret = dwc2_enter_partial_power_down(hsotg); ++ if (ret) { ++ if (ret != -ENOTSUPP) ++ dev_err(hsotg->dev, ++ "enter partial_power_down failed\n"); ++ goto skip_power_saving; ++ } ++ ++ /* After entering partial_power_down, hardware is no more accessible */ ++ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + } + + /* Ask phy to be suspended */ +@@ -4519,9 +4534,6 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd) + spin_lock_irqsave(&hsotg->lock, flags); + } + +- /* After entering partial_power_down, hardware is no more accessible */ +- clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); +- + skip_power_saving: + hsotg->lx_state = DWC2_L2; + unlock: +@@ -4534,6 +4546,7 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) + { + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + unsigned long flags; ++ u32 pcgctl; + int ret = 0; + + spin_lock_irqsave(&hsotg->lock, flags); +@@ -4544,18 +4557,12 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) + if (hsotg->lx_state != DWC2_L2) + goto unlock; + +- if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) { ++ if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) { + hsotg->lx_state = DWC2_L0; + goto unlock; + } + + /* +- * Set HW accessible bit before powering on the controller +- * since an interrupt may rise. +- */ +- set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); +- +- /* + * Enable power if not already done. + * This must not be spinlocked since duration + * of this call is unknown. +@@ -4566,10 +4573,23 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) + spin_lock_irqsave(&hsotg->lock, flags); + } + +- /* Exit partial_power_down */ +- ret = dwc2_exit_partial_power_down(hsotg, true); +- if (ret && (ret != -ENOTSUPP)) +- dev_err(hsotg->dev, "exit partial_power_down failed\n"); ++ if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) { ++ /* ++ * Set HW accessible bit before powering on the controller ++ * since an interrupt may rise. ++ */ ++ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); ++ ++ ++ /* Exit partial_power_down */ ++ ret = dwc2_exit_partial_power_down(hsotg, true); ++ if (ret && (ret != -ENOTSUPP)) ++ dev_err(hsotg->dev, "exit partial_power_down failed\n"); ++ } else { ++ pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl &= ~PCGCTL_STOPPCLK; ++ writel(pcgctl, hsotg->regs + PCGCTL); ++ } + + hsotg->lx_state = DWC2_L0; + +@@ -4581,10 +4601,12 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) + spin_unlock_irqrestore(&hsotg->lock, flags); + dwc2_port_resume(hsotg); + } else { +- dwc2_vbus_supply_init(hsotg); ++ if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) { ++ dwc2_vbus_supply_init(hsotg); + +- /* Wait for controller to correctly update D+/D- level */ +- usleep_range(3000, 5000); ++ /* Wait for controller to correctly update D+/D- level */ ++ usleep_range(3000, 5000); ++ } + + /* + * Clear Port Enable and Port Status changes. +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0030-usb-dwc2-gadget-Reject-LPM-token-during-Control-tran.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0030-usb-dwc2-gadget-Reject-LPM-token-during-Control-tran.patch new file mode 100644 index 0000000..08b0b8b --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0030-usb-dwc2-gadget-Reject-LPM-token-during-Control-tran.patch @@ -0,0 +1,47 @@ +From 466375657d6c5987f2f2404c75b7081ede14cff4 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Thu, 18 Apr 2019 15:40:43 +0400 +Subject: [PATCH 30/53] usb: dwc2: gadget: Reject LPM token during Control + transfers + +Avoiding switch to L1 state in any stage of control transfers. +Send NYET handshake to LPM token. + +Renamed GLPMCFG_LPM_ACCEPT_CTRL_ISOC to GLPMCFG_LPM_REJECT_CTRL_CONTROL +because by setting this bit core reject LPM token. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 1 + + drivers/usb/dwc2/hw.h | 2 +- + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 6812a8a3a98b..6ac850d6ad44 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -5073,6 +5073,7 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) + val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; + val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; + val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; ++ val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; + val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; + dwc2_writel(hsotg, val, GLPMCFG); + dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); +diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h +index 98af924a9a5c..1bc394dcfa9d 100644 +--- a/drivers/usb/dwc2/hw.h ++++ b/drivers/usb/dwc2/hw.h +@@ -333,7 +333,7 @@ + #define GLPMCFG_SNDLPM BIT(24) + #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21) + #define GLPMCFG_RETRY_CNT_SHIFT 21 +-#define GLPMCFG_LPM_ACCEPT_CTRL_CONTROL BIT(21) ++#define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21) + #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22) + #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17) + #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17 +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0032-usb-dwc2-optionally-assert-phy-reset-when-waking-up.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0032-usb-dwc2-optionally-assert-phy-reset-when-waking-up.patch new file mode 100644 index 0000000..474513e --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0032-usb-dwc2-optionally-assert-phy-reset-when-waking-up.patch @@ -0,0 +1,180 @@ +From c40cf7705e13d288d900e044c0a2f756e9e4909a Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Tue, 16 Apr 2019 14:53:49 -0700 +Subject: [PATCH 32/53] usb: dwc2: optionally assert phy reset when waking up + +On the rk3288 USB host-only port (the one that's not the OTG-enabled +port) the PHY can get into a bad state when a wakeup is asserted (not +just a wakeup from full system suspend but also a wakeup from +autosuspend). + +We can get the PHY out of its bad state by asserting its "port reset", +but unfortunately that seems to assert a reset onto the USB bus so it +could confuse things if we don't actually deenumerate / reenumerate the +device. + +We can also get the PHY out of its bad state by fully resetting it using +the reset from the CRU (clock reset unit), which does a more full +reset. The CRU-based reset appears to actually cause devices on the bus +to be removed and reinserted, which fixes the problem (albeit in a hacky +way). + +It's unfortunate that we need to do a full re-enumeration of devices at +wakeup time, but this is better than alternative of letting the bus get +wedged. + +Signed-off-by: Douglas Anderson +Signed-off-by: Yunzhi Li +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 8 ++++++++ + drivers/usb/dwc2/core_intr.c | 12 ++++++++++++ + drivers/usb/dwc2/hcd.c | 18 +++++++++++++++--- + drivers/usb/dwc2/platform.c | 9 +++++++++ + 4 files changed, 44 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 30bab8463c96..764c78ebee28 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -859,6 +859,8 @@ struct dwc2_hregs_backup { + * @gadget_enabled: Peripheral mode sub-driver initialization indicator. + * @ll_hw_enabled: Status of low-level hardware resources. + * @hibernated: True if core is hibernated ++ * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a ++ * remote wakeup. + * @frame_number: Frame number read from the core. For both device + * and host modes. The value ranges are from 0 + * to HFNUM_MAX_FRNUM. +@@ -972,6 +974,7 @@ struct dwc2_hregs_backup { + * @status_buf_dma: DMA address for status_buf + * @start_work: Delayed work for handling host A-cable connection + * @reset_work: Delayed work for handling a port reset ++ * @phy_reset_work: Work structure for doing a PHY reset + * @otg_port: OTG port number + * @frame_list: Frame list + * @frame_list_dma: Frame list DMA address +@@ -1045,6 +1048,7 @@ struct dwc2_hsotg { + unsigned int gadget_enabled:1; + unsigned int ll_hw_enabled:1; + unsigned int hibernated:1; ++ unsigned int reset_phy_on_wake:1; + u16 frame_number; + + struct phy *phy; +@@ -1147,6 +1151,7 @@ struct dwc2_hsotg { + + struct delayed_work start_work; + struct delayed_work reset_work; ++ struct work_struct phy_reset_work; + u8 otg_port; + u32 *frame_list; + dma_addr_t frame_list_dma; +@@ -1431,6 +1436,8 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); + int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); + int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, + int rem_wakeup, int reset); ++static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) ++{ schedule_work(&hsotg->phy_reset_work); } + #else + static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) + { return 0; } +@@ -1454,6 +1461,7 @@ static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) + static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, + int rem_wakeup, int reset) + { return 0; } ++static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} + + #endif + +diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c +index 19ae2595f1c3..6af6add3d4c0 100644 +--- a/drivers/usb/dwc2/core_intr.c ++++ b/drivers/usb/dwc2/core_intr.c +@@ -435,6 +435,18 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) + /* Restart the Phy Clock */ + pcgcctl &= ~PCGCTL_STOPPCLK; + dwc2_writel(hsotg, pcgcctl, PCGCTL); ++ ++ /* ++ * If we've got this quirk then the PHY is stuck upon ++ * wakeup. Assert reset. This will propagate out and ++ * eventually we'll re-enumerate the device. Not great ++ * but the best we can do. We can't call phy_reset() ++ * at interrupt time but there's no hurry, so we'll ++ * schedule it for later. ++ */ ++ if (hsotg->reset_phy_on_wake) ++ dwc2_host_schedule_phy_reset(hsotg); ++ + mod_timer(&hsotg->wkp_timer, + jiffies + msecs_to_jiffies(71)); + } else { +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 8667ddf3ca74..978232a9e4a8 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -4376,6 +4376,17 @@ static void dwc2_hcd_reset_func(struct work_struct *work) + spin_unlock_irqrestore(&hsotg->lock, flags); + } + ++static void dwc2_hcd_phy_reset_func(struct work_struct *work) ++{ ++ struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, ++ phy_reset_work); ++ int ret; ++ ++ ret = phy_reset(hsotg->phy); ++ if (ret) ++ dev_warn(hsotg->dev, "PHY reset failed\n"); ++} ++ + /* + * ========================================================================= + * Linux HC Driver Functions +@@ -5152,6 +5163,8 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) + destroy_workqueue(hsotg->wq_otg); + } + ++ cancel_work_sync(&hsotg->phy_reset_work); ++ + del_timer(&hsotg->wkp_timer); + } + +@@ -5293,11 +5306,10 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg) + hsotg->hc_ptr_array[i] = channel; + } + +- /* Initialize hsotg start work */ ++ /* Initialize work */ + INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); +- +- /* Initialize port reset work */ + INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); ++ INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func); + + /* + * Allocate space for storing data on status transactions. Normally no +diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c +index 9aa9682a5cd2..c01fa8ffc0c8 100644 +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -481,6 +481,15 @@ static int dwc2_driver_probe(struct platform_device *dev) + hsotg->gadget_enabled = 1; + } + ++ hsotg->reset_phy_on_wake = ++ of_property_read_bool(dev->dev.of_node, ++ "snps,reset-phy-on-wake"); ++ if (hsotg->reset_phy_on_wake && !hsotg->phy) { ++ dev_warn(hsotg->dev, ++ "Quirk reset-phy-on-wake only supports generic PHYs\n"); ++ hsotg->reset_phy_on_wake = false; ++ } ++ + if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { + retval = dwc2_hcd_init(hsotg); + if (retval) { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0033-usb-dwc2-Move-UTMI_PHY_DATA-defines-closer.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0033-usb-dwc2-Move-UTMI_PHY_DATA-defines-closer.patch new file mode 100644 index 0000000..5dcecc5 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0033-usb-dwc2-Move-UTMI_PHY_DATA-defines-closer.patch @@ -0,0 +1,38 @@ +From a89bae709b3492b478480a2c9734e7e9393b279c Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Fri, 5 Apr 2019 15:35:29 +0200 +Subject: [PATCH 33/53] usb: dwc2: Move UTMI_PHY_DATA defines closer + +Makes GHWCFG4_UTMI_PHY_DATA* defines closer to their relative shift and +mask defines to improve readability. + +Acked-by: Minas Harutyunyan +Signed-off-by: Jules Maselbas +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hw.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h +index 1bc394dcfa9d..510e87ec0be8 100644 +--- a/drivers/usb/dwc2/hw.h ++++ b/drivers/usb/dwc2/hw.h +@@ -310,12 +310,12 @@ + #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 +-#define GHWCFG4_ACG_SUPPORTED BIT(12) +-#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) +-#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 + #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 ++#define GHWCFG4_ACG_SUPPORTED BIT(12) ++#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) ++#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) + #define GHWCFG4_XHIBER BIT(7) + #define GHWCFG4_HIBER BIT(6) + #define GHWCFG4_MIN_AHB_FREQ BIT(5) +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0034-usb-dwc2-gadget-Remove-duplicated-phy-init.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0034-usb-dwc2-gadget-Remove-duplicated-phy-init.patch new file mode 100644 index 0000000..397c585 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0034-usb-dwc2-gadget-Remove-duplicated-phy-init.patch @@ -0,0 +1,51 @@ +From fb26b553bf2627ff96c38236daab0138a82c613a Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Fri, 5 Apr 2019 15:35:30 +0200 +Subject: [PATCH 34/53] usb: dwc2: gadget: Remove duplicated phy init + +The function dwc2_hsotg_init is only called once just before calling +dwc2_hsotg_core_init_disconnected which does the same initialization: +setting the usbcfg register with turnaround time, timeout calibration +and phy width. + +Acked-by: Minas Harutyunyan +Signed-off-by: Jules Maselbas +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 13 ------------- + 1 file changed, 13 deletions(-) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 6ac850d6ad44..9b737c4e8f50 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -4328,8 +4328,6 @@ static const struct usb_ep_ops dwc2_hsotg_ep_ops = { + */ + static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) + { +- u32 trdtim; +- u32 usbcfg; + /* unmask subset of endpoint interrupts */ + + dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | +@@ -4353,17 +4351,6 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) + + dwc2_hsotg_init_fifo(hsotg); + +- /* keep other bits untouched (so e.g. forced modes are not lost) */ +- usbcfg = dwc2_readl(hsotg, GUSBCFG); +- usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | +- GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); +- +- /* set the PLL on, remove the HNP/SRP and set the PHY */ +- trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; +- usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | +- (trdtim << GUSBCFG_USBTRDTIM_SHIFT); +- dwc2_writel(hsotg, usbcfg, GUSBCFG); +- + if (using_dma(hsotg)) + dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); + } +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0035-usb-dwc2-gadget-Replace-phyif-with-phy_utmi_width.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0035-usb-dwc2-gadget-Replace-phyif-with-phy_utmi_width.patch new file mode 100644 index 0000000..824c0ba --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0035-usb-dwc2-gadget-Replace-phyif-with-phy_utmi_width.patch @@ -0,0 +1,106 @@ +From 707d80f0a3c5fb58e61404277f6b103955fac294 Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Fri, 5 Apr 2019 15:35:31 +0200 +Subject: [PATCH 35/53] usb: dwc2: gadget: Replace phyif with phy_utmi_width + +The phy utmi width information is already set in hsotg params, +phyif is only used in few places and I don't see any reason to +not use hsotg's params. + +Moreover the utmi width was being forced to 16 bits by platform +initialization which doesn't take in account HW configuration. + +Acked-by: Minas Harutyunyan +Signed-off-by: Jules Maselbas +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 2 -- + drivers/usb/dwc2/gadget.c | 20 ++++++++++++++------ + drivers/usb/dwc2/platform.c | 5 +---- + 3 files changed, 15 insertions(+), 12 deletions(-) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 764c78ebee28..8e3edf10d76d 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -871,7 +871,6 @@ struct dwc2_hregs_backup { + * removed once all SoCs support usb transceiver. + * @supplies: Definition of USB power supplies + * @vbus_supply: Regulator supplying vbus. +- * @phyif: PHY interface width + * @lock: Spinlock that protects all the driver data structures + * @priv: Stores a pointer to the struct usb_hcd + * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth +@@ -1056,7 +1055,6 @@ struct dwc2_hsotg { + struct dwc2_hsotg_plat *plat; + struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; + struct regulator *vbus_supply; +- u32 phyif; + + spinlock_t lock; + void *priv; +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 9b737c4e8f50..614f8c34d759 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -3314,20 +3314,28 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, + + /* keep other bits untouched (so e.g. forced modes are not lost) */ + usbcfg = dwc2_readl(hsotg, GUSBCFG); ++ /* remove the HNP/SRP */ + usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | +- GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); ++ GUSBCFG_HNPCAP); ++ usbcfg |= GUSBCFG_TOUTCAL(7); + + if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && + (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || + hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { + /* FS/LS Dedicated Transceiver Interface */ + usbcfg |= GUSBCFG_PHYSEL; +- } else { +- /* set the PLL on, remove the HNP/SRP and set the PHY */ +- val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; +- usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | +- (val << GUSBCFG_USBTRDTIM_SHIFT); ++ } else if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_UTMI) { ++ if (hsotg->params.phy_utmi_width == 16) ++ usbcfg |= GUSBCFG_PHYIF16; ++ ++ /* Set turnaround time */ ++ usbcfg &= ~GUSBCFG_USBTRDTIM_MASK; ++ if (hsotg->params.phy_utmi_width == 16) ++ usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT; ++ else ++ usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT; + } ++ + dwc2_writel(hsotg, usbcfg, GUSBCFG); + + dwc2_hsotg_init_fifo(hsotg); +diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c +index c01fa8ffc0c8..d10a7f8daec3 100644 +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -230,9 +230,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) + + reset_control_deassert(hsotg->reset_ecc); + +- /* Set default UTMI width */ +- hsotg->phyif = GUSBCFG_PHYIF16; +- + /* + * Attempt to find a generic PHY, then look for an old style + * USB PHY and then fall back to pdata +@@ -280,7 +277,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) + * width is 8-bit and set the phyif appropriately. + */ + if (phy_get_bus_width(hsotg->phy) == 8) +- hsotg->phyif = GUSBCFG_PHYIF8; ++ hsotg->params.phy_utmi_width = 8; + } + + /* Clock */ +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0036-usb-dwc2-Move-phy-init-into-core.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0036-usb-dwc2-Move-phy-init-into-core.patch new file mode 100644 index 0000000..796233e --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0036-usb-dwc2-Move-phy-init-into-core.patch @@ -0,0 +1,436 @@ +From 059d8d528718407435216251eff8b49935b92b34 Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Fri, 5 Apr 2019 15:35:32 +0200 +Subject: [PATCH 36/53] usb: dwc2: Move phy init into core + +As the phy initialization is almost the same in host and gadget +mode. This only move the phy initialization functions into core.c +for now, the goal is to share theses functions between the two modes. + +Acked-by: Minas Harutyunyan +Signed-off-by: Jules Maselbas +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++++ + drivers/usb/dwc2/core.h | 2 + + drivers/usb/dwc2/hcd.c | 190 ------------------------------------------------ + 3 files changed, 192 insertions(+), 190 deletions(-) + +diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c +index 55d5ae2a7ec7..01ac4a064feb 100644 +--- a/drivers/usb/dwc2/core.c ++++ b/drivers/usb/dwc2/core.c +@@ -1020,6 +1020,196 @@ int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, + return -ETIMEDOUT; + } + ++/* ++ * Initializes the FSLSPClkSel field of the HCFG register depending on the ++ * PHY type ++ */ ++void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) ++{ ++ u32 hcfg, val; ++ ++ if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && ++ hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && ++ hsotg->params.ulpi_fs_ls) || ++ hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { ++ /* Full speed PHY */ ++ val = HCFG_FSLSPCLKSEL_48_MHZ; ++ } else { ++ /* High speed PHY running at full speed or high speed */ ++ val = HCFG_FSLSPCLKSEL_30_60_MHZ; ++ } ++ ++ dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); ++ hcfg = dwc2_readl(hsotg, HCFG); ++ hcfg &= ~HCFG_FSLSPCLKSEL_MASK; ++ hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; ++ dwc2_writel(hsotg, hcfg, HCFG); ++} ++ ++static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ++{ ++ u32 usbcfg, ggpio, i2cctl; ++ int retval = 0; ++ ++ /* ++ * core_init() is now called on every switch so only call the ++ * following for the first time through ++ */ ++ if (select_phy) { ++ dev_dbg(hsotg->dev, "FS PHY selected\n"); ++ ++ usbcfg = dwc2_readl(hsotg, GUSBCFG); ++ if (!(usbcfg & GUSBCFG_PHYSEL)) { ++ usbcfg |= GUSBCFG_PHYSEL; ++ dwc2_writel(hsotg, usbcfg, GUSBCFG); ++ ++ /* Reset after a PHY select */ ++ retval = dwc2_core_reset(hsotg, false); ++ ++ if (retval) { ++ dev_err(hsotg->dev, ++ "%s: Reset failed, aborting", __func__); ++ return retval; ++ } ++ } ++ ++ if (hsotg->params.activate_stm_fs_transceiver) { ++ ggpio = dwc2_readl(hsotg, GGPIO); ++ if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { ++ dev_dbg(hsotg->dev, "Activating transceiver\n"); ++ /* ++ * STM32F4x9 uses the GGPIO register as general ++ * core configuration register. ++ */ ++ ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; ++ dwc2_writel(hsotg, ggpio, GGPIO); ++ } ++ } ++ } ++ ++ /* ++ * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also ++ * do this on HNP Dev/Host mode switches (done in dev_init and ++ * host_init). ++ */ ++ if (dwc2_is_host_mode(hsotg)) ++ dwc2_init_fs_ls_pclk_sel(hsotg); ++ ++ if (hsotg->params.i2c_enable) { ++ dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); ++ ++ /* Program GUSBCFG.OtgUtmiFsSel to I2C */ ++ usbcfg = dwc2_readl(hsotg, GUSBCFG); ++ usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; ++ dwc2_writel(hsotg, usbcfg, GUSBCFG); ++ ++ /* Program GI2CCTL.I2CEn */ ++ i2cctl = dwc2_readl(hsotg, GI2CCTL); ++ i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; ++ i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; ++ i2cctl &= ~GI2CCTL_I2CEN; ++ dwc2_writel(hsotg, i2cctl, GI2CCTL); ++ i2cctl |= GI2CCTL_I2CEN; ++ dwc2_writel(hsotg, i2cctl, GI2CCTL); ++ } ++ ++ return retval; ++} ++ ++static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ++{ ++ u32 usbcfg, usbcfg_old; ++ int retval = 0; ++ ++ if (!select_phy) ++ return 0; ++ ++ usbcfg = dwc2_readl(hsotg, GUSBCFG); ++ usbcfg_old = usbcfg; ++ ++ /* ++ * HS PHY parameters. These parameters are preserved during soft reset ++ * so only program the first time. Do a soft reset immediately after ++ * setting phyif. ++ */ ++ switch (hsotg->params.phy_type) { ++ case DWC2_PHY_TYPE_PARAM_ULPI: ++ /* ULPI interface */ ++ dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); ++ usbcfg |= GUSBCFG_ULPI_UTMI_SEL; ++ usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); ++ if (hsotg->params.phy_ulpi_ddr) ++ usbcfg |= GUSBCFG_DDRSEL; ++ ++ /* Set external VBUS indicator as needed. */ ++ if (hsotg->params.oc_disable) ++ usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | ++ GUSBCFG_INDICATORPASSTHROUGH); ++ break; ++ case DWC2_PHY_TYPE_PARAM_UTMI: ++ /* UTMI+ interface */ ++ dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); ++ usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); ++ if (hsotg->params.phy_utmi_width == 16) ++ usbcfg |= GUSBCFG_PHYIF16; ++ break; ++ default: ++ dev_err(hsotg->dev, "FS PHY selected at HS!\n"); ++ break; ++ } ++ ++ if (usbcfg != usbcfg_old) { ++ dwc2_writel(hsotg, usbcfg, GUSBCFG); ++ ++ /* Reset after setting the PHY parameters */ ++ retval = dwc2_core_reset(hsotg, false); ++ if (retval) { ++ dev_err(hsotg->dev, ++ "%s: Reset failed, aborting", __func__); ++ return retval; ++ } ++ } ++ ++ return retval; ++} ++ ++int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) ++{ ++ u32 usbcfg; ++ int retval = 0; ++ ++ if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || ++ hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && ++ hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { ++ /* If FS/LS mode with FS/LS PHY */ ++ retval = dwc2_fs_phy_init(hsotg, select_phy); ++ if (retval) ++ return retval; ++ } else { ++ /* High speed PHY */ ++ retval = dwc2_hs_phy_init(hsotg, select_phy); ++ if (retval) ++ return retval; ++ } ++ ++ if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && ++ hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && ++ hsotg->params.ulpi_fs_ls) { ++ dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); ++ usbcfg = dwc2_readl(hsotg, GUSBCFG); ++ usbcfg |= GUSBCFG_ULPI_FS_LS; ++ usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; ++ dwc2_writel(hsotg, usbcfg, GUSBCFG); ++ } else { ++ usbcfg = dwc2_readl(hsotg, GUSBCFG); ++ usbcfg &= ~GUSBCFG_ULPI_FS_LS; ++ usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; ++ dwc2_writel(hsotg, usbcfg, GUSBCFG); ++ } ++ ++ return retval; ++} ++ + MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); + MODULE_AUTHOR("Synopsys, Inc."); + MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 8e3edf10d76d..9f3fc8e18277 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -1286,6 +1286,8 @@ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); + int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); + int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, + int reset, int is_host); ++void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); ++int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); + + void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); + void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 978232a9e4a8..7ac7b524243d 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -97,196 +97,6 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) + dwc2_writel(hsotg, intmsk, GINTMSK); + } + +-/* +- * Initializes the FSLSPClkSel field of the HCFG register depending on the +- * PHY type +- */ +-static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) +-{ +- u32 hcfg, val; +- +- if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && +- hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && +- hsotg->params.ulpi_fs_ls) || +- hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { +- /* Full speed PHY */ +- val = HCFG_FSLSPCLKSEL_48_MHZ; +- } else { +- /* High speed PHY running at full speed or high speed */ +- val = HCFG_FSLSPCLKSEL_30_60_MHZ; +- } +- +- dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); +- hcfg = dwc2_readl(hsotg, HCFG); +- hcfg &= ~HCFG_FSLSPCLKSEL_MASK; +- hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; +- dwc2_writel(hsotg, hcfg, HCFG); +-} +- +-static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +-{ +- u32 usbcfg, ggpio, i2cctl; +- int retval = 0; +- +- /* +- * core_init() is now called on every switch so only call the +- * following for the first time through +- */ +- if (select_phy) { +- dev_dbg(hsotg->dev, "FS PHY selected\n"); +- +- usbcfg = dwc2_readl(hsotg, GUSBCFG); +- if (!(usbcfg & GUSBCFG_PHYSEL)) { +- usbcfg |= GUSBCFG_PHYSEL; +- dwc2_writel(hsotg, usbcfg, GUSBCFG); +- +- /* Reset after a PHY select */ +- retval = dwc2_core_reset(hsotg, false); +- +- if (retval) { +- dev_err(hsotg->dev, +- "%s: Reset failed, aborting", __func__); +- return retval; +- } +- } +- +- if (hsotg->params.activate_stm_fs_transceiver) { +- ggpio = dwc2_readl(hsotg, GGPIO); +- if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { +- dev_dbg(hsotg->dev, "Activating transceiver\n"); +- /* +- * STM32F4x9 uses the GGPIO register as general +- * core configuration register. +- */ +- ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; +- dwc2_writel(hsotg, ggpio, GGPIO); +- } +- } +- } +- +- /* +- * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also +- * do this on HNP Dev/Host mode switches (done in dev_init and +- * host_init). +- */ +- if (dwc2_is_host_mode(hsotg)) +- dwc2_init_fs_ls_pclk_sel(hsotg); +- +- if (hsotg->params.i2c_enable) { +- dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); +- +- /* Program GUSBCFG.OtgUtmiFsSel to I2C */ +- usbcfg = dwc2_readl(hsotg, GUSBCFG); +- usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; +- dwc2_writel(hsotg, usbcfg, GUSBCFG); +- +- /* Program GI2CCTL.I2CEn */ +- i2cctl = dwc2_readl(hsotg, GI2CCTL); +- i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; +- i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; +- i2cctl &= ~GI2CCTL_I2CEN; +- dwc2_writel(hsotg, i2cctl, GI2CCTL); +- i2cctl |= GI2CCTL_I2CEN; +- dwc2_writel(hsotg, i2cctl, GI2CCTL); +- } +- +- return retval; +-} +- +-static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +-{ +- u32 usbcfg, usbcfg_old; +- int retval = 0; +- +- if (!select_phy) +- return 0; +- +- usbcfg = dwc2_readl(hsotg, GUSBCFG); +- usbcfg_old = usbcfg; +- +- /* +- * HS PHY parameters. These parameters are preserved during soft reset +- * so only program the first time. Do a soft reset immediately after +- * setting phyif. +- */ +- switch (hsotg->params.phy_type) { +- case DWC2_PHY_TYPE_PARAM_ULPI: +- /* ULPI interface */ +- dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); +- usbcfg |= GUSBCFG_ULPI_UTMI_SEL; +- usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); +- if (hsotg->params.phy_ulpi_ddr) +- usbcfg |= GUSBCFG_DDRSEL; +- +- /* Set external VBUS indicator as needed. */ +- if (hsotg->params.oc_disable) +- usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | +- GUSBCFG_INDICATORPASSTHROUGH); +- break; +- case DWC2_PHY_TYPE_PARAM_UTMI: +- /* UTMI+ interface */ +- dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); +- usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); +- if (hsotg->params.phy_utmi_width == 16) +- usbcfg |= GUSBCFG_PHYIF16; +- break; +- default: +- dev_err(hsotg->dev, "FS PHY selected at HS!\n"); +- break; +- } +- +- if (usbcfg != usbcfg_old) { +- dwc2_writel(hsotg, usbcfg, GUSBCFG); +- +- /* Reset after setting the PHY parameters */ +- retval = dwc2_core_reset(hsotg, false); +- if (retval) { +- dev_err(hsotg->dev, +- "%s: Reset failed, aborting", __func__); +- return retval; +- } +- } +- +- return retval; +-} +- +-static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +-{ +- u32 usbcfg; +- int retval = 0; +- +- if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || +- hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && +- hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { +- /* If FS/LS mode with FS/LS PHY */ +- retval = dwc2_fs_phy_init(hsotg, select_phy); +- if (retval) +- return retval; +- } else { +- /* High speed PHY */ +- retval = dwc2_hs_phy_init(hsotg, select_phy); +- if (retval) +- return retval; +- } +- +- if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && +- hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && +- hsotg->params.ulpi_fs_ls) { +- dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); +- usbcfg = dwc2_readl(hsotg, GUSBCFG); +- usbcfg |= GUSBCFG_ULPI_FS_LS; +- usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; +- dwc2_writel(hsotg, usbcfg, GUSBCFG); +- } else { +- usbcfg = dwc2_readl(hsotg, GUSBCFG); +- usbcfg &= ~GUSBCFG_ULPI_FS_LS; +- usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; +- dwc2_writel(hsotg, usbcfg, GUSBCFG); +- } +- +- return retval; +-} +- + static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) + { + u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0037-usb-dwc2-gadget-Move-gadget-phy-init-into-core-phy-i.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0037-usb-dwc2-gadget-Move-gadget-phy-init-into-core-phy-i.patch new file mode 100644 index 0000000..1a1d1e2 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0037-usb-dwc2-gadget-Move-gadget-phy-init-into-core-phy-i.patch @@ -0,0 +1,80 @@ +From 1e868545f2bb06f7dd4a1c97c5b9ed2615929cf0 Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Fri, 5 Apr 2019 15:35:33 +0200 +Subject: [PATCH 37/53] usb: dwc2: gadget: Move gadget phy init into core phy + init + +Most of the phy initialization is shared between host and gadget, +this adds the turnaround configuration only used by gadgets to +the global phy init. + +Acked-by: Minas Harutyunyan +Signed-off-by: Jules Maselbas +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.c | 9 +++++++++ + drivers/usb/dwc2/gadget.c | 25 +++++-------------------- + 2 files changed, 14 insertions(+), 20 deletions(-) + +diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c +index 01ac4a064feb..8b499d643461 100644 +--- a/drivers/usb/dwc2/core.c ++++ b/drivers/usb/dwc2/core.c +@@ -1152,6 +1152,15 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) + usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); + if (hsotg->params.phy_utmi_width == 16) + usbcfg |= GUSBCFG_PHYIF16; ++ ++ /* Set turnaround time */ ++ if (dwc2_is_device_mode(hsotg)) { ++ usbcfg &= ~GUSBCFG_USBTRDTIM_MASK; ++ if (hsotg->params.phy_utmi_width == 16) ++ usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT; ++ else ++ usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT; ++ } + break; + default: + dev_err(hsotg->dev, "FS PHY selected at HS!\n"); +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 614f8c34d759..2e2f9cbf6a3d 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -3314,29 +3314,14 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, + + /* keep other bits untouched (so e.g. forced modes are not lost) */ + usbcfg = dwc2_readl(hsotg, GUSBCFG); +- /* remove the HNP/SRP */ +- usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | +- GUSBCFG_HNPCAP); ++ usbcfg &= ~GUSBCFG_TOUTCAL_MASK; + usbcfg |= GUSBCFG_TOUTCAL(7); + +- if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && +- (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || +- hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { +- /* FS/LS Dedicated Transceiver Interface */ +- usbcfg |= GUSBCFG_PHYSEL; +- } else if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_UTMI) { +- if (hsotg->params.phy_utmi_width == 16) +- usbcfg |= GUSBCFG_PHYIF16; +- +- /* Set turnaround time */ +- usbcfg &= ~GUSBCFG_USBTRDTIM_MASK; +- if (hsotg->params.phy_utmi_width == 16) +- usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT; +- else +- usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT; +- } ++ /* remove the HNP/SRP and set the PHY */ ++ usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); ++ dwc2_writel(hsotg, usbcfg, GUSBCFG); + +- dwc2_writel(hsotg, usbcfg, GUSBCFG); ++ dwc2_phy_init(hsotg, true); + + dwc2_hsotg_init_fifo(hsotg); + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0038-usb-dwc2-Delayed-status-support.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0038-usb-dwc2-Delayed-status-support.patch new file mode 100644 index 0000000..6655e8b --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0038-usb-dwc2-Delayed-status-support.patch @@ -0,0 +1,111 @@ +From b4c53b4ac66a75a93672abf08aafac64dfb08d00 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Tue, 12 Mar 2019 11:45:12 +0400 +Subject: [PATCH 38/53] usb: dwc2: Delayed status support + +Added delayed status support for Control transfers. + +Tested in all 3 modes: Slave, BDMA and DDMA. +Performed tests: USB CV (Ch9 and MSC), Control Read/Write tests +using Synopsys USB test environment function driver. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 2 ++ + drivers/usb/dwc2/gadget.c | 31 +++++++++++++++++++++++++++---- + 2 files changed, 29 insertions(+), 4 deletions(-) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 9f3fc8e18277..152ac41dfb2d 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -993,6 +993,7 @@ struct dwc2_hregs_backup { + * @ctrl_buff: Buffer for EP0 control requests. + * @ctrl_req: Request for EP0 control packets. + * @ep0_state: EP0 control transfers state ++ * @delayed_status: true when gadget driver asks for delayed status + * @test_mode: USB test mode requested by the host + * @remote_wakeup_allowed: True if device is allowed to wake-up host by + * remote-wakeup signalling +@@ -1175,6 +1176,7 @@ struct dwc2_hsotg { + void *ep0_buff; + void *ctrl_buff; + enum dwc2_ep0_state ep0_state; ++ unsigned delayed_status : 1; + u8 test_mode; + + dma_addr_t setup_desc_dma[2]; +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 2e2f9cbf6a3d..5f314a10a116 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -27,6 +27,8 @@ + #include + #include + #include ++#include ++ + + #include "core.h" + #include "hw.h" +@@ -1446,6 +1448,11 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, + return 0; + } + ++ /* Change EP direction if status phase request is after data out */ ++ if (!hs_ep->index && !req->length && !hs_ep->dir_in && ++ hs->ep0_state == DWC2_EP0_DATA_OUT) ++ hs_ep->dir_in = 1; ++ + if (first) { + if (!hs_ep->isochronous) { + dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); +@@ -1938,6 +1945,10 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, + dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); + } + ++ hsotg->delayed_status = false; ++ if (ret == USB_GADGET_DELAYED_STATUS) ++ hsotg->delayed_status = true; ++ + /* + * the request is either unhandlable, or is not formatted correctly + * so respond with a STALL for the status stage to indicate failure. +@@ -2387,8 +2398,8 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) + if (!using_desc_dma(hsotg) && epnum == 0 && + hsotg->ep0_state == DWC2_EP0_DATA_OUT) { + /* Move to STATUS IN */ +- dwc2_hsotg_ep0_zlp(hsotg, true); +- return; ++ if (!hsotg->delayed_status) ++ dwc2_hsotg_ep0_zlp(hsotg, true); + } + + /* +@@ -3053,8 +3064,20 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, + /* Safety check EP0 state when STSPHSERCVD asserted */ + if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { + /* Move to STATUS IN for DDMA */ +- if (using_desc_dma(hsotg)) +- dwc2_hsotg_ep0_zlp(hsotg, true); ++ if (using_desc_dma(hsotg)) { ++ if (!hsotg->delayed_status) ++ dwc2_hsotg_ep0_zlp(hsotg, true); ++ else ++ /* In case of 3 stage Control Write with delayed ++ * status, when Status IN transfer started ++ * before STSPHSERCVD asserted, NAKSTS bit not ++ * cleared by CNAK in dwc2_hsotg_start_req() ++ * function. Clear now NAKSTS to allow complete ++ * transfer. ++ */ ++ dwc2_set_bit(hsotg, DIEPCTL(0), ++ DXEPCTL_CNAK); ++ } + } + + } +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0040-usb-dwc2-Set-actual-frame-number-for-completed-ISOC-.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0040-usb-dwc2-Set-actual-frame-number-for-completed-ISOC-.patch new file mode 100644 index 0000000..d8d261f --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0040-usb-dwc2-Set-actual-frame-number-for-completed-ISOC-.patch @@ -0,0 +1,36 @@ +From c8006f67ae0371900e601112d9f9cd8fff1c8387 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Tue, 12 Mar 2019 13:27:46 +0400 +Subject: [PATCH 40/53] usb: dwc2: Set actual frame number for completed ISOC + transfer + +On ISOC transfer completion, in DDMA mode, set actual frame +number returning to function driver in usb_request. + +Due to core limitation, returning frame number is 11-bit wide. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index fafd9cc9c8b2..a17e444e467b 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -2166,6 +2166,11 @@ static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) + */ + if (!hs_ep->dir_in && ureq->length & 0x3) + ureq->actual += 4 - (ureq->length & 0x3); ++ ++ /* Set actual frame number for completed transfers */ ++ ureq->frame_number = ++ (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >> ++ DEV_DMA_ISOC_FRNUM_SHIFT; + } + + dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0041-usb-dwc2-Fix-channel-disable-flow.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0041-usb-dwc2-Fix-channel-disable-flow.patch new file mode 100644 index 0000000..ac0bf22 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0041-usb-dwc2-Fix-channel-disable-flow.patch @@ -0,0 +1,68 @@ +From 5799aecd64f2bb6c8175a2e86fbcb9e60d052221 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Tue, 5 Mar 2019 15:08:55 +0400 +Subject: [PATCH 41/53] usb: dwc2: Fix channel disable flow + +Channel disabling/halting should performed for enabled only channels +to avoid warnings "Unable to clear enable on channel N" which seen +if host works in Slave mode. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hcd.c | 34 ++++++++++++++++++++-------------- + 1 file changed, 20 insertions(+), 14 deletions(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 7ac7b524243d..b50ec3714fd8 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -2247,25 +2247,31 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) + num_channels = hsotg->params.host_channels; + for (i = 0; i < num_channels; i++) { + hcchar = dwc2_readl(hsotg, HCCHAR(i)); +- hcchar &= ~HCCHAR_CHENA; +- hcchar |= HCCHAR_CHDIS; +- hcchar &= ~HCCHAR_EPDIR; +- dwc2_writel(hsotg, hcchar, HCCHAR(i)); ++ if (hcchar & HCCHAR_CHENA) { ++ hcchar &= ~HCCHAR_CHENA; ++ hcchar |= HCCHAR_CHDIS; ++ hcchar &= ~HCCHAR_EPDIR; ++ dwc2_writel(hsotg, hcchar, HCCHAR(i)); ++ } + } + + /* Halt all channels to put them into a known state */ + for (i = 0; i < num_channels; i++) { + hcchar = dwc2_readl(hsotg, HCCHAR(i)); +- hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; +- hcchar &= ~HCCHAR_EPDIR; +- dwc2_writel(hsotg, hcchar, HCCHAR(i)); +- dev_dbg(hsotg->dev, "%s: Halt channel %d\n", +- __func__, i); +- +- if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), +- HCCHAR_CHENA, 1000)) { +- dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n", +- i); ++ if (hcchar & HCCHAR_CHENA) { ++ hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; ++ hcchar &= ~HCCHAR_EPDIR; ++ dwc2_writel(hsotg, hcchar, HCCHAR(i)); ++ dev_dbg(hsotg->dev, "%s: Halt channel %d\n", ++ __func__, i); ++ ++ if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), ++ HCCHAR_CHENA, ++ 1000)) { ++ dev_warn(hsotg->dev, ++ "Unable to clear enable on channel %d\n", ++ i); ++ } + } + } + } +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0042-usb-dwc2-Set-lpm-mode-parameters-depend-on-HW-config.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0042-usb-dwc2-Set-lpm-mode-parameters-depend-on-HW-config.patch new file mode 100644 index 0000000..e211c5a --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0042-usb-dwc2-Set-lpm-mode-parameters-depend-on-HW-config.patch @@ -0,0 +1,69 @@ +From 28b5c129ca6e585ec95c160ec4297bc6c6360b6f Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Mon, 4 Mar 2019 17:08:07 +0400 +Subject: [PATCH 42/53] usb: dwc2: Set lpm mode parameters depend on HW + configuration + +If core not supported lpm, i.e. BCM2835 then confusing warnings seen +in log. + +To avoid these warnings, added function dwc2_set_param_lpm() to set +lpm and other lpm related parameters based on lpm support by core. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/params.c | 23 ++++++++++++++++++----- + 1 file changed, 18 insertions(+), 5 deletions(-) + +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index 442113246cba..6900eea57526 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -285,6 +285,23 @@ static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) + hsotg->params.power_down = val; + } + ++static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) ++{ ++ struct dwc2_core_params *p = &hsotg->params; ++ ++ p->lpm = hsotg->hw_params.lpm_mode; ++ if (p->lpm) { ++ p->lpm_clock_gating = true; ++ p->besl = true; ++ p->hird_threshold_en = true; ++ p->hird_threshold = 4; ++ } else { ++ p->lpm_clock_gating = false; ++ p->besl = false; ++ p->hird_threshold_en = false; ++ } ++} ++ + /** + * dwc2_set_default_params() - Set all core parameters to their + * auto-detected default values. +@@ -303,6 +320,7 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) + dwc2_set_param_speed(hsotg); + dwc2_set_param_phy_utmi_width(hsotg); + dwc2_set_param_power_down(hsotg); ++ dwc2_set_param_lpm(hsotg); + p->phy_ulpi_ddr = false; + p->phy_ulpi_ext_vbus = false; + +@@ -315,11 +333,6 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) + p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); + p->uframe_sched = true; + p->external_id_pin_ctl = false; +- p->lpm = true; +- p->lpm_clock_gating = true; +- p->besl = true; +- p->hird_threshold_en = true; +- p->hird_threshold = 4; + p->ipg_isoc_en = false; + p->service_interval = false; + p->max_packet_count = hw->max_packet_count; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0043-dwc2-gadget-Fix-completed-transfer-size-calculation-.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0043-dwc2-gadget-Fix-completed-transfer-size-calculation-.patch new file mode 100644 index 0000000..3ce11c3 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0043-dwc2-gadget-Fix-completed-transfer-size-calculation-.patch @@ -0,0 +1,35 @@ +From 5acb4b970184d189d901192d075997c933b82260 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Fri, 22 Feb 2019 15:49:19 +0400 +Subject: [PATCH 43/53] dwc2: gadget: Fix completed transfer size calculation + in DDMA + +Fix calculation of transfer size on completion in function +dwc2_gadget_get_xfersize_ddma(). + +Added increment of descriptor pointer to move to next descriptor in +the loop. + +Fixes: aa3e8bc81311 ("usb: dwc2: gadget: DDMA transfer start and complete") + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index a17e444e467b..16ffd9fd9361 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -2325,6 +2325,7 @@ static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) + if (status & DEV_DMA_STS_MASK) + dev_err(hsotg->dev, "descriptor %d closed with %x\n", + i, status & DEV_DMA_STS_MASK); ++ desc++; + } + + return bytes_rem; +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch new file mode 100644 index 0000000..a554c8a --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch @@ -0,0 +1,50 @@ +From d991f855cb4f84c638e2016818259720ceed4191 Mon Sep 17 00:00:00 2001 +From: Bartlomiej Zolnierkiewicz +Date: Mon, 20 May 2019 16:14:33 +0200 +Subject: [PATCH 44/53] usb: remove redundant 'default n' from Kconfig-s + +'default n' is the default value for any bool or tristate Kconfig +setting so there is no need to write it explicitly. + +Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO +is not set' for visible symbols") the Kconfig behavior is the same +regardless of 'default n' being present or not: + + ... + One side effect of (and the main motivation for) this change is making + the following two definitions behave exactly the same: + + config FOO + bool + + config FOO + bool + default n + + With this change, neither of these will generate a + '# CONFIG_FOO is not set' line (assuming FOO isn't selected/implied). + That might make it clearer to people that a bare 'default n' is + redundant. + ... + +Signed-off-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc2/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig +index 68d095ae2865..16e1aa304edc 100644 +--- a/drivers/usb/dwc2/Kconfig ++++ b/drivers/usb/dwc2/Kconfig +@@ -58,7 +58,6 @@ config USB_DWC2_PCI + tristate "DWC2 PCI" + depends on USB_PCI + depends on USB_GADGET || !USB_GADGET +- default n + select NOP_USB_XCEIV + help + The Designware USB2.0 PCI interface module for controllers +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0047-usb-dwc2-Set-actual-frame-number-for-completed-ISOC-.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0047-usb-dwc2-Set-actual-frame-number-for-completed-ISOC-.patch new file mode 100644 index 0000000..fa3bf64 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0047-usb-dwc2-Set-actual-frame-number-for-completed-ISOC-.patch @@ -0,0 +1,33 @@ +From 4faf3b36553a0a5304f58ee3a620e659739a2e20 Mon Sep 17 00:00:00 2001 +From: Minas Harutyunyan +Date: Mon, 29 Apr 2019 15:23:43 +0400 +Subject: [PATCH 47/53] usb: dwc2: Set actual frame number for completed ISOC + transfer for none DDMA + +On ISOC OUT transfer completion, in none DDMA mode, set actual frame +number returning to function driver in usb_request. + +Signed-off-by: Minas Harutyunyan +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 16ffd9fd9361..1d4aef8d4137 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -2417,6 +2417,10 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) + dwc2_gadget_incr_frame_num(hs_ep); + } + ++ /* Set actual frame number for completed transfers */ ++ if (!using_desc_dma(hsotg) && hs_ep->isochronous) ++ req->frame_number = hsotg->frame_number; ++ + dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); + } + +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0048-usb-gadget-dwc2-fix-zlp-handling.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0048-usb-gadget-dwc2-fix-zlp-handling.patch new file mode 100644 index 0000000..ff6314d --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0048-usb-gadget-dwc2-fix-zlp-handling.patch @@ -0,0 +1,88 @@ +From 066cfd0770aba8a9ac79b59d99530653885d919d Mon Sep 17 00:00:00 2001 +From: Andrzej Pietrasiewicz +Date: Mon, 1 Apr 2019 12:50:45 +0200 +Subject: [PATCH 48/53] usb: gadget: dwc2: fix zlp handling + +The patch 10209abe87f5ebfd482a00323f5236d6094d0865 +usb: dwc2: gadget: Add scatter-gather mode + +avoided a NULL pointer dereference (hs_ep->req == NULL) by +calling dwc2_gadget_fill_nonisoc_xfer_dma_one() directly instead of through +the dwc2_gadget_config_nonisoc_xfer_ddma() wrapper, which unconditionally +dereferenced the said pointer. + +However, this was based on an incorrect assumption that in the context of +dwc2_hsotg_program_zlp() the pointer is always NULL, which is not the case. +The result were SB CV MSC tests failing starting from Test Case 6. + +Instead, this patch reverts to calling the wrapper and adds a check for +the pointer being NULL inside the wrapper. + +Fixes: 10209abe87f5 (usb: dwc2: gadget: Add scatter-gather mode) +Acked-by: Minas Harutyunyan +Signed-off-by: Andrzej Pietrasiewicz +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/gadget.c | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c +index 1d4aef8d4137..bff48a8a1984 100644 +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -835,19 +835,22 @@ static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, + * with corresponding information based on transfer data. + */ + static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, +- struct usb_request *ureq, +- unsigned int offset, ++ dma_addr_t dma_buff, + unsigned int len) + { ++ struct usb_request *ureq = NULL; + struct dwc2_dma_desc *desc = hs_ep->desc_list; + struct scatterlist *sg; + int i; + u8 desc_count = 0; + ++ if (hs_ep->req) ++ ureq = &hs_ep->req->req; ++ + /* non-DMA sg buffer */ +- if (!ureq->num_sgs) { ++ if (!ureq || !ureq->num_sgs) { + dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, +- ureq->dma + offset, len, true); ++ dma_buff, len, true); + return; + } + +@@ -1135,7 +1138,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, + offset = ureq->actual; + + /* Fill DDMA chain entries */ +- dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq, offset, ++ dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, + length); + + /* write descriptor chain address to control register */ +@@ -2037,12 +2040,13 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, + dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", + index); + if (using_desc_dma(hsotg)) { ++ /* Not specific buffer needed for ep0 ZLP */ ++ dma_addr_t dma = hs_ep->desc_list_dma; ++ + if (!index) + dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); + +- /* Not specific buffer needed for ep0 ZLP */ +- dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &hs_ep->desc_list, +- hs_ep->desc_list_dma, 0, true); ++ dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); + } else { + dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(0), +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0049-usb-dwc2-Use-generic-PHY-width-in-params-setup.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0049-usb-dwc2-Use-generic-PHY-width-in-params-setup.patch new file mode 100644 index 0000000..5b0b3d2 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0049-usb-dwc2-Use-generic-PHY-width-in-params-setup.patch @@ -0,0 +1,68 @@ +From 42de8afc40c97002fceb500e2331f6a722be3c14 Mon Sep 17 00:00:00 2001 +From: Jules Maselbas +Date: Thu, 9 May 2019 11:15:28 +0200 +Subject: [PATCH 49/53] usb: dwc2: Use generic PHY width in params setup + +Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since +it's value will be overwritten by dwc2_init_params(). + +This change make sure to take in account the generic PHY width information +during paraminitialisation, done in dwc2_set_param_phy_utmi_width(). + +By doing so, the phy_utmi_width params can still be overrided by +devicetree specific params and will also be checked against hardware +capabilities. + +Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width") +Acked-by: Minas Harutyunyan +Tested-by: Marek Szyprowski +Signed-off-by: Jules Maselbas +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/params.c | 9 +++++++++ + drivers/usb/dwc2/platform.c | 9 --------- + 2 files changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index 6900eea57526..5949262ff669 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -253,6 +253,15 @@ static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) + val = (hsotg->hw_params.utmi_phy_data_width == + GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; + ++ if (hsotg->phy) { ++ /* ++ * If using the generic PHY framework, check if the PHY bus ++ * width is 8-bit and set the phyif appropriately. ++ */ ++ if (phy_get_bus_width(hsotg->phy) == 8) ++ val = 8; ++ } ++ + hsotg->params.phy_utmi_width = val; + } + +diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c +index d10a7f8daec3..e98d7812da2d 100644 +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -271,15 +271,6 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) + + hsotg->plat = dev_get_platdata(hsotg->dev); + +- if (hsotg->phy) { +- /* +- * If using the generic PHY framework, check if the PHY bus +- * width is 8-bit and set the phyif appropriately. +- */ +- if (phy_get_bus_width(hsotg->phy) == 8) +- hsotg->params.phy_utmi_width = 8; +- } +- + /* Clock */ + hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg"); + if (IS_ERR(hsotg->clk)) { +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0050-usb-dwc2-Force-8bit-UTMI-width-for-Samsung-Exynos-So.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0050-usb-dwc2-Force-8bit-UTMI-width-for-Samsung-Exynos-So.patch new file mode 100644 index 0000000..7ee3fcf --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0050-usb-dwc2-Force-8bit-UTMI-width-for-Samsung-Exynos-So.patch @@ -0,0 +1,35 @@ +From 1112cf4c4109473fd8a30a4678d25f9321ef5d67 Mon Sep 17 00:00:00 2001 +From: Marek Szyprowski +Date: Fri, 14 Jun 2019 08:52:53 +0200 +Subject: [PATCH 50/53] usb: dwc2: Force 8bit UTMI width for Samsung Exynos + SoCs + +Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the +host side of the shared USB2 PHY doesn't work. + +Reported-by: Krzysztof Kozlowski +Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width") +Signed-off-by: Marek Szyprowski +Acked-by: Minas Harutyunyan +Acked-by: Krzysztof Kozlowski +Tested-by: Krzysztof Kozlowski +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/params.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c +index 6900eea57526..9ece4affb9d4 100644 +--- a/drivers/usb/dwc2/params.c ++++ b/drivers/usb/dwc2/params.c +@@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) + struct dwc2_core_params *p = &hsotg->params; + + p->power_down = 0; ++ p->phy_utmi_width = 8; + } + + static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch new file mode 100644 index 0000000..3cb1304 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch @@ -0,0 +1,164 @@ +From c846b03ff767149d75d4d8dca6d3d4945a21074a Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Mon, 20 May 2019 10:56:04 -0700 +Subject: [PATCH 51/53] USB: dwc2: Don't turn off the usbphy in suspend if + wakeup is enabled + +If the 'snps,need-phy-for-wake' is set in the device tree then: + +- We know that we can wakeup, so call device_set_wakeup_capable(). + The USB core will use this knowledge to enable wakeup by default. +- We know that we should keep the PHY on during suspend if something + on our root hub needs remote wakeup. This requires the patch (USB: + Export usb_wakeup_enabled_descendants()). Note that we don't keep + the PHY on at suspend time if it's not needed because it would be a + power draw. + +If we later find some users of dwc2 that can support wakeup without +keeping the PHY on we may want to add a way to call +device_set_wakeup_capable() without keeping the PHY on at suspend +time. + +Signed-off-by: Douglas Anderson +Signed-off-by: Chris Zhong +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/core.h | 8 ++++++++ + drivers/usb/dwc2/hcd.c | 19 +++++++++++++++++++ + drivers/usb/dwc2/platform.c | 23 ++++++++++++++++++++--- + 3 files changed, 47 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h +index 152ac41dfb2d..d08d070a0fb6 100644 +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -861,6 +861,9 @@ struct dwc2_hregs_backup { + * @hibernated: True if core is hibernated + * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a + * remote wakeup. ++ * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. ++ * @need_phy_for_wake: Quirk saying that we should keep the PHY on at ++ * suspend if we need USB to wake us up. + * @frame_number: Frame number read from the core. For both device + * and host modes. The value ranges are from 0 + * to HFNUM_MAX_FRNUM. +@@ -1049,6 +1052,8 @@ struct dwc2_hsotg { + unsigned int ll_hw_enabled:1; + unsigned int hibernated:1; + unsigned int reset_phy_on_wake:1; ++ unsigned int need_phy_for_wake:1; ++ unsigned int phy_off_for_suspend:1; + u16 frame_number; + + struct phy *phy; +@@ -1438,6 +1443,7 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); + int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); + int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, + int rem_wakeup, int reset); ++bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); + static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) + { schedule_work(&hsotg->phy_reset_work); } + #else +@@ -1463,6 +1469,8 @@ static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) + static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, + int rem_wakeup, int reset) + { return 0; } ++static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) ++{ return false; } + static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} + + #endif +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 2192a2873c7c..4c78a390c958 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -5587,3 +5587,22 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, + dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); + return ret; + } ++ ++bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) ++{ ++ struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub; ++ ++ /* If the controller isn't allowed to wakeup then we can power off. */ ++ if (!device_may_wakeup(dwc2->dev)) ++ return true; ++ ++ /* ++ * We don't want to power off the PHY if something under the ++ * root hub has wakeup enabled. ++ */ ++ if (usb_wakeup_enabled_descendants(root_hub)) ++ return false; ++ ++ /* No reason to keep the PHY powered, so allow poweroff */ ++ return true; ++} +diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c +index d10a7f8daec3..3e6c3c8a32ff 100644 +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -447,6 +447,10 @@ static int dwc2_driver_probe(struct platform_device *dev) + if (retval) + goto error; + ++ hsotg->need_phy_for_wake = ++ of_property_read_bool(dev->dev.of_node, ++ "snps,need-phy-for-wake"); ++ + /* + * Reset before dwc2_get_hwparams() then it could get power-on real + * reset value form registers. +@@ -478,6 +482,14 @@ static int dwc2_driver_probe(struct platform_device *dev) + hsotg->gadget_enabled = 1; + } + ++ /* ++ * If we need PHY for wakeup we must be wakeup capable. ++ * When we have a device that can wake without the PHY we ++ * can adjust this condition. ++ */ ++ if (hsotg->need_phy_for_wake) ++ device_set_wakeup_capable(&dev->dev, true); ++ + hsotg->reset_phy_on_wake = + of_property_read_bool(dev->dev.of_node, + "snps,reset-phy-on-wake"); +@@ -516,13 +528,17 @@ static int dwc2_driver_probe(struct platform_device *dev) + static int __maybe_unused dwc2_suspend(struct device *dev) + { + struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); ++ bool is_device_mode = dwc2_is_device_mode(dwc2); + int ret = 0; + +- if (dwc2_is_device_mode(dwc2)) ++ if (is_device_mode) + dwc2_hsotg_suspend(dwc2); + +- if (dwc2->ll_hw_enabled) ++ if (dwc2->ll_hw_enabled && ++ (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) { + ret = __dwc2_lowlevel_hw_disable(dwc2); ++ dwc2->phy_off_for_suspend = true; ++ } + + return ret; + } +@@ -532,11 +548,12 @@ static int __maybe_unused dwc2_resume(struct device *dev) + struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); + int ret = 0; + +- if (dwc2->ll_hw_enabled) { ++ if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) { + ret = __dwc2_lowlevel_hw_enable(dwc2); + if (ret) + return ret; + } ++ dwc2->phy_off_for_suspend = false; + + if (dwc2_is_device_mode(dwc2)) + ret = dwc2_hsotg_resume(dwc2); +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch new file mode 100644 index 0000000..43f2253 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch @@ -0,0 +1,53 @@ +From ad408a1596b45868e38d0504f2ec1d5fb06f17d4 Mon Sep 17 00:00:00 2001 +From: Guenter Roeck +Date: Wed, 29 May 2019 13:54:43 -0700 +Subject: [PATCH 52/53] Revert "usb: dwc2: host: Setting qtd to NULL after + freeing it" + +This reverts commit b0d659022e5c96ee5c4bd62d22d3da2d66de306b. + +The reverted commit does nothing but adding two unnecessary lines +of code. It sets a local variable to NULL in two functions, but +that variable is not used anywhere in the rest of those functions. +This is just confusing, so let's remove it. + +Cc: Vardan Mikayelyan +Cc: John Youn +Cc: Douglas Anderson +Cc: Felipe Balbi +Acked-by: Minas Harutyunyan +Reviewed-by: Douglas Anderson +Signed-off-by: Guenter Roeck +Signed-off-by: Felipe Balbi +--- + drivers/usb/dwc2/hcd.c | 1 - + drivers/usb/dwc2/hcd.h | 1 - + 2 files changed, 2 deletions(-) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index 4c78a390c958..ee144ff8af5b 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -4685,7 +4685,6 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, + spin_unlock_irqrestore(&hsotg->lock, flags); + urb->hcpriv = NULL; + kfree(qtd); +- qtd = NULL; + fail1: + if (qh_allocated) { + struct dwc2_qtd *qtd2, *qtd2_tmp; +diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h +index ce6445a06588..8ca6d12a6f57 100644 +--- a/drivers/usb/dwc2/hcd.h ++++ b/drivers/usb/dwc2/hcd.h +@@ -582,7 +582,6 @@ static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, + { + list_del(&qtd->qtd_list_entry); + kfree(qtd); +- qtd = NULL; + } + + /* Descriptor DMA support functions */ +-- +2.11.0 + diff --git a/resources/BuildResources/patches-tested/kernel/5.x-usb/export-usb_wakeup_enabled_descendants.patch b/resources/BuildResources/patches-tested/kernel/5.x-usb/export-usb_wakeup_enabled_descendants.patch new file mode 100644 index 0000000..26ddbb6 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/5.x-usb/export-usb_wakeup_enabled_descendants.patch @@ -0,0 +1,77 @@ +From 7a6127e39a16c97b505f13352238567fdc3f79a2 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Wed, 17 Apr 2019 17:13:53 -0700 +Subject: [PATCH] USB: Export usb_wakeup_enabled_descendants() + +In (e583d9d USB: global suspend and remote wakeup don't mix) we +introduced wakeup_enabled_descendants() as a static function. We'd +like to use this function in USB controller drivers to know if we +should keep the controller on during suspend time, since doing so has +a power impact. + +Signed-off-by: Douglas Anderson +Signed-off-by: Felipe Balbi +--- + drivers/usb/core/hub.c | 7 ++++--- + include/linux/usb/hcd.h | 5 +++++ + 2 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c +index 8d4631c81b9f0..5e8f3fa7ae5a9 100644 +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -3174,13 +3174,14 @@ static int usb_disable_remote_wakeup(struct usb_device *udev) + } + + /* Count of wakeup-enabled devices at or below udev */ +-static unsigned wakeup_enabled_descendants(struct usb_device *udev) ++unsigned usb_wakeup_enabled_descendants(struct usb_device *udev) + { + struct usb_hub *hub = usb_hub_to_struct_hub(udev); + + return udev->do_remote_wakeup + + (hub ? hub->wakeup_enabled_descendants : 0); + } ++EXPORT_SYMBOL_GPL(usb_wakeup_enabled_descendants); + + /* + * usb_port_suspend - suspend a usb device's upstream port +@@ -3282,7 +3283,7 @@ int usb_port_suspend(struct usb_device *udev, pm_message_t msg) + * Therefore we will turn on the suspend feature if udev or any of its + * descendants is enabled for remote wakeup. + */ +- else if (PMSG_IS_AUTO(msg) || wakeup_enabled_descendants(udev) > 0) ++ else if (PMSG_IS_AUTO(msg) || usb_wakeup_enabled_descendants(udev) > 0) + status = set_port_feature(hub->hdev, port1, + USB_PORT_FEAT_SUSPEND); + else { +@@ -3687,7 +3688,7 @@ static int hub_suspend(struct usb_interface *intf, pm_message_t msg) + } + if (udev) + hub->wakeup_enabled_descendants += +- wakeup_enabled_descendants(udev); ++ usb_wakeup_enabled_descendants(udev); + } + + if (hdev->do_remote_wakeup && hub->quirk_check_port_auto_suspend) { +diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h +index 695931b03684d..ed4fbbd1b35f5 100644 +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -652,11 +652,16 @@ extern wait_queue_head_t usb_kill_urb_queue; + #define usb_endpoint_out(ep_dir) (!((ep_dir) & USB_DIR_IN)) + + #ifdef CONFIG_PM ++extern unsigned usb_wakeup_enabled_descendants(struct usb_device *udev); + extern void usb_root_hub_lost_power(struct usb_device *rhdev); + extern int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg); + extern int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg); + extern void usb_hcd_resume_root_hub(struct usb_hcd *hcd); + #else ++static inline unsigned usb_wakeup_enabled_descendants(struct usb_device *udev) ++{ ++ return 0; ++} + static inline void usb_hcd_resume_root_hub(struct usb_hcd *hcd) + { + return; diff --git a/resources/BuildResources/patches-tested/kernel/reverse-do-not-use-bulk-on-EP3-and-EP4.patch b/resources/BuildResources/patches-tested/kernel/reverse-do-not-use-bulk-on-EP3-and-EP4.patch deleted file mode 100644 index 551c18c..0000000 --- a/resources/BuildResources/patches-tested/kernel/reverse-do-not-use-bulk-on-EP3-and-EP4.patch +++ /dev/null @@ -1,101 +0,0 @@ -FROM: Solidhal - -This patch reverses commit 2b721118b7821107757eb1d37af4b60e877b27e7, as can bee seen here: -https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2b721118b7821107757eb1d37af4b60e877b27e7 - -This commit caused issues on veyron speedy with ath9k and dwc2 drivers. Any ath9k device (ar9271) -would intermittently work, most of the time ending in errors as can bee seen here: -https://github.com/SolidHal/PrawnOS/issues/38 -This commit fixes that issue. -This is only a temporary work around while a permenant fix is found, as this commit seems to only cause issues -with dwc2 - -diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c ---- b/drivers/net/wireless/ath/ath9k/hif_usb.c -+++ a/drivers/net/wireless/ath/ath9k/hif_usb.c -@@ -115,10 +115,10 @@ - cmd->skb = skb; - cmd->hif_dev = hif_dev; - -+ usb_fill_bulk_urb(urb, hif_dev->udev, -+ usb_sndbulkpipe(hif_dev->udev, USB_REG_OUT_PIPE), -- usb_fill_int_urb(urb, hif_dev->udev, -- usb_sndintpipe(hif_dev->udev, USB_REG_OUT_PIPE), - skb->data, skb->len, -+ hif_usb_regout_cb, cmd); -- hif_usb_regout_cb, cmd, 1); - - usb_anchor_urb(urb, &hif_dev->regout_submitted); - ret = usb_submit_urb(urb, GFP_KERNEL); -@@ -723,11 +723,11 @@ - return; - } - -+ usb_fill_bulk_urb(urb, hif_dev->udev, -+ usb_rcvbulkpipe(hif_dev->udev, -- usb_fill_int_urb(urb, hif_dev->udev, -- usb_rcvintpipe(hif_dev->udev, - USB_REG_IN_PIPE), - nskb->data, MAX_REG_IN_BUF_SIZE, -+ ath9k_hif_usb_reg_in_cb, nskb); -- ath9k_hif_usb_reg_in_cb, nskb, 1); - } - - resubmit: -@@ -909,11 +909,11 @@ - goto err_skb; - } - -+ usb_fill_bulk_urb(urb, hif_dev->udev, -+ usb_rcvbulkpipe(hif_dev->udev, -- usb_fill_int_urb(urb, hif_dev->udev, -- usb_rcvintpipe(hif_dev->udev, - USB_REG_IN_PIPE), - skb->data, MAX_REG_IN_BUF_SIZE, -+ ath9k_hif_usb_reg_in_cb, skb); -- ath9k_hif_usb_reg_in_cb, skb, 1); - - /* Anchor URB */ - usb_anchor_urb(urb, &hif_dev->reg_in_submitted); -@@ -1031,7 +1031,9 @@ - - static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev) - { -+ struct usb_host_interface *alt = &hif_dev->interface->altsetting[0]; -+ struct usb_endpoint_descriptor *endp; -+ int ret, idx; -- int ret; - - ret = ath9k_hif_usb_download_fw(hif_dev); - if (ret) { -@@ -1041,6 +1043,20 @@ - return ret; - } - -+ /* On downloading the firmware to the target, the USB descriptor of EP4 -+ * is 'patched' to change the type of the endpoint to Bulk. This will -+ * bring down CPU usage during the scan period. -+ */ -+ for (idx = 0; idx < alt->desc.bNumEndpoints; idx++) { -+ endp = &alt->endpoint[idx].desc; -+ if ((endp->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) -+ == USB_ENDPOINT_XFER_INT) { -+ endp->bmAttributes &= ~USB_ENDPOINT_XFERTYPE_MASK; -+ endp->bmAttributes |= USB_ENDPOINT_XFER_BULK; -+ endp->bInterval = 0; -+ } -+ } -+ - /* Alloc URBs */ - ret = ath9k_hif_usb_alloc_urbs(hif_dev); - if (ret) { -@@ -1252,7 +1268,7 @@ - if (!buf) - return; - -+ ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, USB_REG_OUT_PIPE), -- ret = usb_interrupt_msg(udev, usb_sndintpipe(udev, USB_REG_OUT_PIPE), - buf, 4, NULL, USB_MSG_TIMEOUT); - if (ret) - dev_err(&udev->dev, "ath9k_htc: USB reboot failed\n"); - diff --git a/scripts/buildKernel.sh b/scripts/buildKernel.sh index 0a5cd44..3580513 100755 --- a/scripts/buildKernel.sh +++ b/scripts/buildKernel.sh @@ -46,6 +46,10 @@ make mrproper #Apply the usb and mmc patches if unapplied [ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/DTS/*.patch; do echo $i; patch -p1 < $i; done [ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/kernel/*.patch; do echo $i; patch -p1 < $i; done +[ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/kernel/5.x-dwc2/*.patch; do echo $i; patch -p1 < $i; done +[ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/kernel/5.x-clk/*.patch; do echo $i; patch -p1 < $i; done +[ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/kernel/5.x-usb/*.patch; do echo $i; patch -p1 < $i; done +[ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/DTS/5.x-dts/*.patch; do echo $i; patch -p1 < $i; done #Apply all of the rockMyy patches that make sense [ "$TEST_PATCHES" = true ] && for i in $RESOURCES/patches-untested/kernel/*.patch; do patch -p1 < $i; done [ "$TEST_PATCHES" = true ] && for i in $RESOURCES/patches-untested/DTS/*.patch; do patch -p1 < $i; done