diff --git a/resources/BuildResources/patches-tested/kernel/0100-arm-errata-workaround-errata-A12-857271-and-A17-857272.patch b/resources/BuildResources/patches-tested/kernel/0100-arm-errata-workaround-errata-A12-857271-and-A17-857272.patch new file mode 100644 index 0000000..f6a80ad --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/0100-arm-errata-workaround-errata-A12-857271-and-A17-857272.patch @@ -0,0 +1,87 @@ +[1/2] ARM: errata: Workaround errata A12 857271 / A17 857272 + +This adds support for working around errata A12 857271 / A17 857272. +These errata were causing hangs on rk3288-based Chromebooks and it was +confirmed that this workaround fixed the problems. In the Chrome OS +3.14 kernel [1] this erratum was known as ERRATA_FOOBAR due to lack of +an official number from ARM (though the workaround of setting chicken +bit 10 came from ARM). In the meantime ARM came up with official +errata numbers but never published the workaround upstream. + +Let's actually get the workaround landed. + +[1] https://crrev.com/c/342753 + +Signed-off-by: Sonny Rao +Signed-off-by: Douglas Anderson +--- + + arch/arm/Kconfig | 19 +++++++++++++++++++ + arch/arm/mm/proc-v7.S | 10 ++++++++++ + 2 files changed, 29 insertions(+) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index b509cd338219..4376fe74f95e 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1172,6 +1172,15 @@ config ARM_ERRATA_825619 + DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable + and Device/Strongly-Ordered loads and stores might cause deadlock + ++config ARM_ERRATA_857271 ++ bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" ++ depends on CPU_V7 ++ help ++ This option enables the workaround for the 857271 Cortex-A12 ++ (all revs) erratum. Under very rare timing conditions, the CPU might ++ hang. The workaround is expected to have a negligible performance ++ impact. ++ + config ARM_ERRATA_852421 + bool "ARM errata: A17: DMB ST might fail to create order between stores" + depends on CPU_V7 +@@ -1193,6 +1202,16 @@ config ARM_ERRATA_852423 + config option from the A12 erratum due to the way errata are checked + for and handled. + ++config ARM_ERRATA_857272 ++ bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" ++ depends on CPU_V7 ++ help ++ This option enables the workaround for the 857272 Cortex-A17 erratum. ++ This erratum is not known to be fixed in any A17 revision. ++ This is identical to Cortex-A12 erratum 857271. It is a separate ++ config option from the A12 erratum due to the way errata are checked ++ for and handled. ++ + endmenu + + source "arch/arm/common/Kconfig" +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index 339eb17c9808..cd2accbab844 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -391,6 +391,11 @@ __ca12_errata: + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 24 @ set bit #24 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register ++#endif ++#ifdef CONFIG_ARM_ERRATA_857271 ++ mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register ++ orr r10, r10, #1 << 10 @ set bit #10 ++ mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register + #endif + b __errata_finish + +@@ -406,6 +411,11 @@ __ca17_errata: + mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrle r10, r10, #1 << 12 @ set bit #12 + mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register ++#endif ++#ifdef CONFIG_ARM_ERRATA_857272 ++ mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register ++ orr r10, r10, #1 << 10 @ set bit #10 ++ mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register + #endif + b __errata_finish + diff --git a/resources/BuildResources/patches-tested/kernel/0101-arm-errata-add-support-for-A12-and-A17-errata-CR711784.patch b/resources/BuildResources/patches-tested/kernel/0101-arm-errata-add-support-for-A12-and-A17-errata-CR711784.patch new file mode 100644 index 0000000..0bf1786 --- /dev/null +++ b/resources/BuildResources/patches-tested/kernel/0101-arm-errata-add-support-for-A12-and-A17-errata-CR711784.patch @@ -0,0 +1,85 @@ +[2/2] ARM: errata: add support for A12/A17 errata CR711784 + +This adds a code for turning on chicken bit 11, which appears to avoid +a potential CPU deadlock that could occur. The exact set of +instruction needed to trigger this errata is not totaly known but we +have a high level of confidence that the problem is fixed by setting +chicken bit 11. + +All details are in http://crbug.com/711784 + +This erratum has no known number and thus I have tagged it CR711784 +(after the Chrome OS bug number). I have created separate A12 / A17 +configs to match how the rest of the A12 / A17 errata is handled. + +Signed-off-by: Douglas Anderson +--- + + arch/arm/Kconfig | 18 ++++++++++++++++++ + arch/arm/mm/proc-v7.S | 10 ++++++++++ + 2 files changed, 28 insertions(+) + + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 4376fe74f95e..34ec9039206b 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1181,6 +1181,13 @@ config ARM_ERRATA_857271 + hang. The workaround is expected to have a negligible performance + impact. + ++config ARM_ERRATA_CR711784_A12 ++ bool "ARM errata: A12: conditional instructions can lead to a CPU hang" ++ depends on CPU_V7 ++ help ++ This option enables the workaround for a Cortex-A12 erratum without a ++ number. The problems are best described in https://crbug.com/711784 ++ + config ARM_ERRATA_852421 + bool "ARM errata: A17: DMB ST might fail to create order between stores" + depends on CPU_V7 +@@ -1212,6 +1219,17 @@ config ARM_ERRATA_857272 + config option from the A12 erratum due to the way errata are checked + for and handled. + ++config ARM_ERRATA_CR711784_A17 ++ bool "ARM errata: A17: conditional instructions can lead to a CPU hang" ++ depends on CPU_V7 ++ help ++ This option enables the workaround for a Cortex-A17 erratum without a ++ number. The problems are best described in https://crbug.com/711784 ++ This erratum is not known to be fixed in any A17 revision. ++ This is identical to Cortex-A12 erratum CR711784. It is a separate ++ config option from the A12 erratum due to the way errata are checked ++ for and handled. ++ + endmenu + + source "arch/arm/common/Kconfig" +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index cd2accbab844..a5156ea734ee 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -396,6 +396,11 @@ __ca12_errata: + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 10 @ set bit #10 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register ++#endif ++#ifdef CONFIG_ARM_ERRATA_CR711784_A12 ++ mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register ++ orr r10, r10, #1 << 11 @ set bit #11 ++ mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register + #endif + b __errata_finish + +@@ -416,6 +421,11 @@ __ca17_errata: + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 10 @ set bit #10 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register ++#endif ++#ifdef CONFIG_ARM_ERRATA_CR711784_A17 ++ mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register ++ orr r10, r10, #1 << 11 @ set bit #11 ++ mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register + #endif + b __errata_finish