diff --git a/makefile b/makefile index 028b1be..363bedd 100644 --- a/makefile +++ b/makefile @@ -13,7 +13,7 @@ # You should have received a copy of the GNU General Public License # along with PrawnOS. If not, see . -KVER=5.2.21 +KVER=5.4.22 ifeq ($(DEBIAN_SUITE),) DEBIAN_SUITE=buster endif @@ -92,6 +92,12 @@ filesystem: kernel_inject: #Targets an already built .img and swaps the old kernel with the newly compiled kernel scripts/injectKernelIntoFS.sh $(KVER) $(OUTNAME) +.PHONY: kernel_update +kernel_update: + make initramfs + make kernel + make kernel_inject + .PHONY: injected_image injected_image: #makes a copy of the base image with a new injected kernel make kernel diff --git a/resources/BuildResources/config b/resources/BuildResources/config index 4cc5580..380ad60 100644 --- a/resources/BuildResources/config +++ b/resources/BuildResources/config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.2.21-gnu Kernel Configuration +# Linux/arm 5.4.22-gnu Kernel Configuration # # @@ -20,6 +20,7 @@ CONFIG_BUILDTIME_EXTABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -85,6 +86,7 @@ CONFIG_HIGH_RES_TIMERS=y # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting @@ -121,10 +123,16 @@ CONFIG_LOG_BUF_SHIFT=18 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + CONFIG_CGROUPS=y # CONFIG_MEMCG is not set CONFIG_BLK_CGROUP=y -# CONFIG_DEBUG_BLK_CGROUP is not set CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y @@ -254,20 +262,13 @@ CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_LPC32XX is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP1 is not set # @@ -286,6 +287,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_ASPEED is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set @@ -360,6 +362,7 @@ CONFIG_ARM_THUMBEE=y CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y # CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_CPU_SPECTRE=y CONFIG_HARDEN_BRANCH_PREDICTOR=y @@ -400,6 +403,7 @@ CONFIG_ARM_ERRATA_825619=y # # Bus support # +# CONFIG_ARM_ERRATA_814220 is not set # end of Bus support # @@ -643,6 +647,8 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=16 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y @@ -679,6 +685,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -691,6 +699,7 @@ CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set # CONFIG_BLK_DEBUG_FS is not set # CONFIG_BLK_SED_OPAL is not set @@ -728,6 +737,7 @@ CONFIG_MQ_IOSCHED_DEADLINE=y CONFIG_MQ_IOSCHED_KYBER=y CONFIG_IOSCHED_BFQ=y CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set # end of IO Schedulers CONFIG_ASN1=y @@ -746,7 +756,9 @@ CONFIG_BINFMT_ELF=y CONFIG_ELFCORE=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y # CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BINFMT_MISC=y CONFIG_COREDUMP=y # end of Executable file formats @@ -1083,6 +1095,7 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=y # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set @@ -1173,13 +1186,16 @@ CONFIG_NET_ACT_GACT=y # CONFIG_NET_ACT_SIMP is not set # CONFIG_NET_ACT_SKBEDIT is not set # CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set # CONFIG_NET_ACT_VLAN is not set # CONFIG_NET_ACT_BPF is not set # CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_NET_ACT_CTINFO is not set # CONFIG_NET_ACT_SKBMOD is not set # CONFIG_NET_ACT_IFE is not set # CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_CLS_IND is not set +# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_TC_SKB_EXT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -1234,6 +1250,7 @@ CONFIG_BT_RTL=y CONFIG_BT_HCIBTUSB=y # CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set # CONFIG_BT_HCIBTUSB_BCM is not set +# CONFIG_BT_HCIBTUSB_MTK is not set CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=y CONFIG_BT_HCIUART=y @@ -1242,7 +1259,6 @@ CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_ATH3K=y # CONFIG_BT_HCIUART_INTEL is not set # CONFIG_BT_HCIUART_AG6XX is not set -# CONFIG_BT_HCIUART_MRVL is not set # CONFIG_BT_HCIBCM203X is not set # CONFIG_BT_HCIBPA10X is not set CONFIG_BT_HCIBFUSB=y @@ -1304,6 +1320,7 @@ CONFIG_RFKILL_LEDS=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y # CONFIG_FAILOVER is not set CONFIG_HAVE_EBPF_JIT=y @@ -1331,6 +1348,7 @@ CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="htc_9271.fw htc_7010.fw" CONFIG_EXTRA_FIRMWARE_DIR="../open-ath9k-htc-firmware/target_firmware" # CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1355,6 +1373,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # Bus devices # # CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set # CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set # end of Bus devices @@ -1364,13 +1383,13 @@ CONFIG_PROC_EVENTS=y # CONFIG_GNSS is not set CONFIG_MTD=y # CONFIG_MTD_TESTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # Partition parsers # +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # end of Partition parsers @@ -1416,7 +1435,6 @@ CONFIG_MTD_CFI_I2=y # Self-contained MTD device drivers # # CONFIG_MTD_DATAFLASH is not set -CONFIG_MTD_M25P80=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set @@ -1446,6 +1464,7 @@ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_MTK_QUADSPI is not set # CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set @@ -1500,9 +1519,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set +# CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set @@ -1585,7 +1604,6 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set @@ -1631,6 +1649,7 @@ CONFIG_DM_THIN_PROVISIONING=y # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set # CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set # CONFIG_DM_MIRROR is not set # CONFIG_DM_RAID is not set # CONFIG_DM_ZERO is not set @@ -1641,6 +1660,7 @@ CONFIG_DM_THIN_PROVISIONING=y # CONFIG_DM_UEVENT is not set CONFIG_DM_FLAKEY=y CONFIG_DM_VERITY=y +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set # CONFIG_DM_VERITY_FEC is not set # CONFIG_DM_SWITCH is not set # CONFIG_DM_LOG_WRITES is not set @@ -1702,6 +1722,7 @@ CONFIG_NET_VENDOR_EZCHIP=y CONFIG_NET_VENDOR_FARADAY=y # CONFIG_FTMAC100 is not set # CONFIG_FTGMAC100 is not set +CONFIG_NET_VENDOR_GOOGLE=y CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set @@ -1732,6 +1753,7 @@ CONFIG_NET_VENDOR_NI=y CONFIG_NET_VENDOR_8390=y # CONFIG_AX88796 is not set # CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PENSANDO=y CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set # CONFIG_QCOM_EMAC is not set @@ -1749,6 +1771,7 @@ CONFIG_NET_VENDOR_SMSC=y CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_SELFTESTS is not set CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y @@ -1761,6 +1784,8 @@ CONFIG_NET_VENDOR_VIA=y CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y # CONFIG_MDIO_BCM_UNIMAC is not set @@ -1770,6 +1795,7 @@ CONFIG_MDIO_BUS=y # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_HISI_FEMAC is not set # CONFIG_MDIO_MSCC_MIIM is not set +CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set @@ -1777,6 +1803,8 @@ CONFIG_SWPHY=y # # MII PHY device drivers # +# CONFIG_SFP is not set +# CONFIG_ADIN_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set @@ -1803,6 +1831,7 @@ CONFIG_FIXED_PHY=y # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y # CONFIG_RENESAS_PHY is not set @@ -2016,6 +2045,7 @@ CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_FSIA6B is not set CONFIG_INPUT_TABLET=y # CONFIG_TABLET_USB_ACECAD is not set # CONFIG_TABLET_USB_AIPTEK is not set @@ -2135,7 +2165,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set @@ -2204,6 +2233,7 @@ CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_EM is not set @@ -2235,10 +2265,12 @@ CONFIG_SERIAL_ARC=y CONFIG_SERIAL_ARC_CONSOLE=y CONFIG_SERIAL_ARC_NR_PORTS=1 # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set # end of Serial drivers +CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_HVC_DCC is not set @@ -2260,6 +2292,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_XILLYBUS is not set # end of Character devices +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + # # I2C support # @@ -2479,8 +2513,10 @@ CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_SYSCON is not set # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set @@ -2533,6 +2569,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set @@ -2620,7 +2657,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set @@ -2672,6 +2708,7 @@ CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # @@ -2691,7 +2728,6 @@ CONFIG_SOFT_WATCHDOG=y # CONFIG_FTWDT010_WATCHDOG is not set CONFIG_DW_WATCHDOG=y # CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_IMX_SC_WDT is not set # CONFIG_MEN_A21_WDT is not set # @@ -2721,8 +2757,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -CONFIG_MFD_CROS_EC=y -CONFIG_MFD_CROS_EC_CHARDEV=y +CONFIG_MFD_CROS_EC_DEV=y # CONFIG_MFD_MADERA is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_PMIC_DA903X is not set @@ -2809,6 +2844,7 @@ CONFIG_MFD_TPS6586X=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # end of Multifunction device drivers @@ -2847,7 +2883,9 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y +# CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS65023 is not set @@ -2888,6 +2926,7 @@ CONFIG_MEDIA_CONTROLLER_REQUEST_API=y CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set @@ -2939,45 +2978,154 @@ CONFIG_VIDEOBUF2_VMALLOC=y CONFIG_MEDIA_SUBDRV_AUTOSELECT=y CONFIG_VIDEO_IR_I2C=y +# +# I2C Encoders, decoders, sensors and other helper chips +# + # # Audio decoders, processors and mixers # +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set # # RDS decoders # +# CONFIG_VIDEO_SAA6588 is not set # # Video decoders # +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set # # Video and audio decoders # +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set # # Video encoders # +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set # # Camera sensor devices # +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set # # Lens drivers # +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9807_VCM is not set # # Flash devices # +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set # # Video improvement chips # +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set # # Audio/Video compression chips # +# CONFIG_VIDEO_SAA6752HS is not set # # SDR tuner chips @@ -2986,15 +3134,31 @@ CONFIG_VIDEO_IR_I2C=y # # Miscellaneous helper chips # +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of I2C Encoders, decoders, sensors and other helper chips + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips # # Media SPI Adapters # # end of Media SPI Adapters +# +# Customise DVB Frontends +# + # # Tools to develop new frontends # +# end of Customise DVB Frontends # # Graphics support @@ -3072,23 +3236,33 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set # CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set # CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set # end of Display Panels @@ -3127,7 +3301,14 @@ CONFIG_DRM_DW_MIPI_DSI=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_PL111 is not set # CONFIG_DRM_LIMA is not set CONFIG_DRM_PANFROST=y @@ -3346,6 +3527,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set # CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set @@ -3357,6 +3539,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set CONFIG_SND_SOC_MAX98090=y +# CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set @@ -3406,6 +3589,7 @@ CONFIG_SND_SOC_TLV320AIC23_I2C=y CONFIG_SND_SOC_TS3A227E=y # CONFIG_SND_SOC_TSCS42XX is not set # CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8524 is not set @@ -3473,6 +3657,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_PRODIKEYS is not set # CONFIG_HID_CMEDIA is not set # CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set @@ -3569,6 +3754,9 @@ CONFIG_I2C_HID=y CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y @@ -3584,7 +3772,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=y -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -3644,6 +3831,7 @@ CONFIG_USB_UAS=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set CONFIG_USB_DWC2=y @@ -3725,7 +3913,6 @@ CONFIG_USB_SERIAL_OPTION=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -3805,9 +3992,6 @@ CONFIG_USB_CONFIGFS_F_FS=y # CONFIG_USB_CONFIGFS_F_PRINTER is not set # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y # CONFIG_PWRSEQ_SD8787 is not set @@ -3825,6 +4009,7 @@ CONFIG_MMC_TEST=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set # CONFIG_MMC_SDHCI_OF_DWCMSHC is not set # CONFIG_MMC_SDHCI_CADENCE is not set @@ -3891,6 +4076,8 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set # # LED Triggers @@ -4065,6 +4252,7 @@ CONFIG_PL330_DMA=y CONFIG_SYNC_FILE=y CONFIG_SW_SYNC=y # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -4079,6 +4267,7 @@ CONFIG_VIRTIO_MENU=y # # end of Microsoft Hyper-V guest support +# CONFIG_GREYBUS is not set CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set @@ -4153,7 +4342,7 @@ CONFIG_STAGING=y # end of Speakup console speech CONFIG_STAGING_MEDIA=y -# CONFIG_VIDEO_ROCKCHIP_VPU is not set +# CONFIG_VIDEO_HANTRO is not set # # soc_camera sensor drivers @@ -4176,7 +4365,6 @@ CONFIG_ASHMEM=y # CONFIG_WILC1000_SPI is not set # CONFIG_MOST is not set # CONFIG_KS7010 is not set -# CONFIG_GREYBUS is not set # CONFIG_PI433 is not set # @@ -4185,13 +4373,18 @@ CONFIG_ASHMEM=y # end of Gasket devices # CONFIG_XIL_AXIS_FIFO is not set -# CONFIG_EROFS_FS is not set # CONFIG_FIELDBUS_DEV is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_UWB is not set +# CONFIG_EXFAT_FS is not set # CONFIG_GOLDFISH is not set +CONFIG_MFD_CROS_EC=y CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y # CONFIG_CROS_EC_I2C is not set CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_PROTO=y +CONFIG_CROS_EC_CHARDEV=y CONFIG_CROS_EC_LIGHTBAR=y CONFIG_CROS_EC_VBC=y CONFIG_CROS_EC_DEBUGFS=y @@ -4207,6 +4400,7 @@ CONFIG_COMMON_CLK=y # CONFIG_CLK_HSDK is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y +# CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI544 is not set @@ -4300,13 +4494,6 @@ CONFIG_ROCKCHIP_IOMMU=y # # end of i.MX SoC drivers -# -# IXP4xx SoC drivers -# -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers - # # Qualcomm SoC drivers # @@ -4442,6 +4629,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set # end of Analog to digital converters # @@ -4470,6 +4658,7 @@ CONFIG_ROCKCHIP_SARADC=y CONFIG_IIO_CROS_EC_SENSORS_CORE=y # CONFIG_IIO_CROS_EC_SENSORS is not set +# CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE is not set # # Hid Sensor IIO Common @@ -4539,6 +4728,7 @@ CONFIG_IIO_CROS_EC_SENSORS_CORE=y # Phase-Locked Loop (PLL) frequency synthesizers # # CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -4587,6 +4777,7 @@ CONFIG_IIO_CROS_EC_SENSORS_CORE=y # Inertial measurement units # # CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set @@ -4621,6 +4812,7 @@ CONFIG_SENSORS_ISL29018=y # CONFIG_LV0104CS is not set # CONFIG_MAX44000 is not set # CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set # CONFIG_OPT3001 is not set # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set @@ -4681,6 +4873,7 @@ CONFIG_IIO_SYSFS_TRIGGER=y # # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set # CONFIG_MAX5481 is not set # CONFIG_MAX5487 is not set # CONFIG_MCP4018 is not set @@ -4702,6 +4895,7 @@ CONFIG_IIO_SYSFS_TRIGGER=y # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set # CONFIG_IIO_CROS_EC_BARO is not set +# CONFIG_DPS310 is not set # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set @@ -4766,13 +4960,13 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_AL_FIC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_TI_SYSCON is not set -# CONFIG_FMC is not set # # PHY Subsystem @@ -4783,6 +4977,7 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_CPCAP_USB is not set @@ -4872,6 +5067,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY_USER=y @@ -4889,6 +5085,7 @@ CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y # CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set # CONFIG_OVERLAY_FS is not set # @@ -4985,6 +5182,7 @@ CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_RAM=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -5004,7 +5202,16 @@ CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y # CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set -# CONFIG_CIFS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_WEAK_PW_HASH=y +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +# CONFIG_CIFS_DFS_UPCALL is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -5066,6 +5273,7 @@ CONFIG_NLS_UTF8=y # Security options # CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_BIG_KEYS is not set # CONFIG_TRUSTED_KEYS is not set @@ -5098,6 +5306,7 @@ CONFIG_SECURITY_LOADPIN=y # CONFIG_SECURITY_LOADPIN_ENFORCE is not set CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y +# CONFIG_SECURITY_LOCKDOWN_LSM is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -5115,6 +5324,8 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" # Memory initialization # CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization # end of Kernel hardening options # end of Security options @@ -5148,7 +5359,6 @@ CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set @@ -5170,10 +5380,6 @@ CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS1280 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y @@ -5191,6 +5397,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=y # # Hash modes @@ -5205,10 +5412,11 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_GHASH=y # CONFIG_CRYPTO_POLY1305 is not set -# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_RMD128 is not set @@ -5216,6 +5424,7 @@ CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set @@ -5227,14 +5436,17 @@ CONFIG_CRYPTO_SHA512=y # # Ciphers # +CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=y CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set @@ -5273,7 +5485,10 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_ROCKCHIP is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y @@ -5366,7 +5581,6 @@ CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_CLZ_TAB=y -# CONFIG_DDR is not set # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y CONFIG_LIBFDT=y @@ -5409,10 +5623,9 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -# CONFIG_OPTIMIZE_INLINING is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set # CONFIG_SECTION_MISMATCH_WARN_ONLY is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y @@ -5570,6 +5783,7 @@ CONFIG_LKDTM=y # CONFIG_TEST_SORT is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set @@ -5590,6 +5804,7 @@ CONFIG_TEST_LKM=m # CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set # CONFIG_FIND_BIT_BENCHMARK is not set CONFIG_TEST_FIRMWARE=y # CONFIG_TEST_SYSCTL is not set @@ -5598,6 +5813,7 @@ CONFIG_TEST_UDELAY=y # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set # CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set # CONFIG_MEMTEST is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch deleted file mode 100644 index 2f9e178..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6773af2684b7bc1b7b2d9ef874599cccaba2559e Mon Sep 17 00:00:00 2001 -From: Caesar Wang -Date: Tue, 9 Apr 2019 13:47:07 -0700 -Subject: [PATCH 28/54] ARM: dts: rockchip: fix PWM clock found on RK3288 Socs - -We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect. - -Signed-off-by: Caesar Wang -Signed-off-by: Douglas Anderson -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index aa017abf4f42..171231a0cd9b 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -682,7 +682,7 @@ - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; -- clocks = <&cru PCLK_PWM>; -+ clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; -@@ -693,7 +693,7 @@ - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; -- clocks = <&cru PCLK_PWM>; -+ clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; -@@ -704,7 +704,7 @@ - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; -- clocks = <&cru PCLK_PWM>; -+ clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; -@@ -715,7 +715,7 @@ - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; -- clocks = <&cru PCLK_PWM>; -+ clocks = <&cru PCLK_RKPWM>; - clock-names = "pwm"; - status = "disabled"; - }; --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch deleted file mode 100644 index 5656c1e..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch +++ /dev/null @@ -1,42 +0,0 @@ -From d190bfaaa2a1575e7998d8487ed26cdf9e74b42b Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Fri, 3 May 2019 16:48:14 -0700 -Subject: [PATCH 29/54] ARM: dts: rockchip: Remove bogus 'i2s_clk_out' from - rk3288-veyron-mickey - -The rk3288-veyron-mickey device tree overrides the default "i2s" clock -settings to add the clock for "i2s_clk_out". - -That clock is only present in the bindings downstream Chrome OS 3.14 -tree. Upstream the i2s port bindings doesn't specify that as a -possible clock. - -Let's remove it. - -NOTE: for other rk3288-veyron devices this clock is consumed by -'maxim,max98090'. Presumably if this clock is needed for mickey it'll -need to be consumed by something similar. - -Signed-off-by: Douglas Anderson -Reviewed-by: Matthias Kaehlcke -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-mickey.dts | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts -index e852594417b5..f9c4ece3c0d3 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts -@@ -142,8 +142,6 @@ - - &i2s { - status = "okay"; -- clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; -- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; - }; - - &rk808 { --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch deleted file mode 100644 index e2bdc07..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775 Mon Sep 17 00:00:00 2001 -From: Matthias Kaehlcke -Date: Thu, 16 May 2019 09:29:40 -0700 -Subject: [PATCH 32/54] ARM: dts: rockchip: raise CPU trip point temperature - for veyron to 100 degC -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This value matches what is used by the downstream Chrome OS 3.14 -kernel, the 'official' kernel for veyron devices. Keep the temperature -for 'speedy' at 90°C, as in the downstream kernel. - -Increase the temperature for a hardware shutdown to 125°C, which -matches the downstream configuration and gives the system a chance -to shut down orderly at the criticial trip point. - -Signed-off-by: Matthias Kaehlcke -Reviewed-by: Douglas Anderson -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++ - arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ - 2 files changed, 9 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts -index 2ac8748a3a0c..b07a07e81551 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts -@@ -64,6 +64,10 @@ - temperature = <70000>; - }; - -+&cpu_crit { -+ temperature = <90000>; -+}; -+ - &edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; -diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi -index 1252522392c7..e81f1a0cac83 100644 ---- a/arch/arm/boot/dts/rk3288-veyron.dtsi -+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi -@@ -123,6 +123,10 @@ - cpu0-supply = <&vdd_cpu>; - }; - -+&cpu_crit { -+ temperature = <100000>; -+}; -+ - /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ - &cpu_opp_table { - /delete-node/ opp-312000000; -@@ -394,6 +398,7 @@ - - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-temp = <125000>; - }; - - &uart0 { --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch deleted file mode 100644 index dc182c6..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f6dcbb3ad5ce927adbdcc04bde312387f3b68035 Mon Sep 17 00:00:00 2001 -From: Matthias Kaehlcke -Date: Thu, 16 May 2019 10:25:09 -0700 -Subject: [PATCH 38/54] ARM: dts: rockchip: Add #cooling-cells entry for rk3288 - GPU - -The Mali GPU of the rk3288 can be used as cooling device, add -a #cooling-cells entry for it. - -Signed-off-by: Matthias Kaehlcke -Reviewed-by: Douglas Anderson -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 1e5260b556b7..7e9b8c7f6ab7 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1286,6 +1286,7 @@ - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - operating-points-v2 = <&gpu_opp_table>; -+ #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3288_PD_GPU>; - status = "disabled"; - }; --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch deleted file mode 100644 index 7e3539d..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch +++ /dev/null @@ -1,40 +0,0 @@ -From ae2b6ba865d8bb59493aaf50cb3d19312a6ff5a4 Mon Sep 17 00:00:00 2001 -From: Matthias Kaehlcke -Date: Thu, 16 May 2019 10:25:10 -0700 -Subject: [PATCH 39/54] ARM: dts: rockchip: Use GPU as cooling device for the - GPU thermal zone of the rk3288 - -Currently the CPUs are used as cooling devices of the rk3288 GPU -thermal zone. The CPUs are also configured as cooling devices in the -CPU thermal zone, which indirectly helps with cooling the GPU thermal -zone, since the CPU and GPU temperatures are correlated on the rk3288. - -Configure the ARM Mali Midgard GPU as cooling device for the GPU -thermal zone instead of the CPUs. - -Signed-off-by: Matthias Kaehlcke -Reviewed-by: Douglas Anderson -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 7e9b8c7f6ab7..fd188bb4fd48 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -552,10 +552,7 @@ - map0 { - trip = <&gpu_alert0>; - cooling-device = -- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch deleted file mode 100644 index 9a6453b..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 75481833c6dbab4c29d15452f6b4337c16f5407b Mon Sep 17 00:00:00 2001 -From: Matthias Kaehlcke -Date: Mon, 20 May 2019 15:00:49 -0700 -Subject: [PATCH 40/54] ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288 - -The NPLL is the only safe way to generate 500 MHz for the GPU. The -downstream Chrome OS 3.14 kernel ('official' kernel for veyron -devices) re-purposes NPLL to HDMI and hence disables the OPP for -the GPU (see https://crrev.com/c/1574579). Disable it here as well -to keep in sync and avoid problems in case someone decides to -re-purpose NPLL. - -Signed-off-by: Matthias Kaehlcke -Reviewed-by: Douglas Anderson -[moved from veyron to general rk3288, as tying up the NPLL for a - not-that-helpful opp (not really fast but will still generate - quite a bit of heat) doesn't make so much sense when it will - keep us from supporting other display modes in the future] -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index fd188bb4fd48..159d91180cee 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1307,10 +1307,6 @@ - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1100000>; - }; -- opp-500000000 { -- opp-hz = /bits/ 64 <500000000>; -- opp-microvolt = <1200000>; -- }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1250000>; --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch deleted file mode 100644 index 11c2a08..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 9dbf05bd8ae5b436b02c9845a350dec11c788a73 Mon Sep 17 00:00:00 2001 -From: John Keeping -Date: Mon, 3 Jun 2019 15:34:35 +0100 -Subject: [PATCH 43/54] ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3 - -This is the same as the other PWMs on this SoC and uses 3 cells. - -Signed-off-by: John Keeping -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 159d91180cee..766d1cf51a5b 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -710,7 +710,7 @@ - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; -- #pwm-cells = <2>; -+ #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_RKPWM>; --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch deleted file mode 100644 index 155529e..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch +++ /dev/null @@ -1,637 +0,0 @@ -From d85b2ad35a2ab320b9c0530992ee532f10a6aeb2 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Fri, 24 May 2019 16:33:09 -0700 -Subject: [PATCH 44/54] ARM: dts: rockchip: Add pin names for rk3288-veyron - jaq, mickey, speedy - -This is like commit 0ca87bd5baa6 ("ARM: dts: rockchip: Add pin names -for rk3288-veyron-jerry") and commit ca3516b32cd9 ("ARM: dts: -rockchip: Add pin names for rk3288-veyron-minnie") but for 3 more -veyron boards. - -A few notes: -- While there is most certainly duplication between all the veyron - boards, it still feels like it is sane to just have each board have - a full list of its pin names. The format of "gpio-line-names" does - not lend itself to one-off overriding and besides it seems sane to - more fully match schematic names. Also note that the extra - duplication here is only in source code and is unlikely to ever - change (since these boards are shipped). Duplication in the .dtb - files is unavoidable. -- veyron-jaq and veyron-mighty are very closely related and so I have - shared a single list for them both with comments on how they are - different. This is just a typo fix on one of the boards, a possible - missing signal on one of the boards (or perhaps I was never given - the most recent schematics?) and dealing with the fact that one of - the two boards has full sized SD. - -Signed-off-by: Douglas Anderson -Reviewed-by: Matthias Kaehlcke -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-jaq.dts | 207 +++++++++++++++++++++++++++++ - arch/arm/boot/dts/rk3288-veyron-mickey.dts | 151 +++++++++++++++++++++ - arch/arm/boot/dts/rk3288-veyron-speedy.dts | 207 +++++++++++++++++++++++++++++ - 3 files changed, 565 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts -index e248f55ee8d2..fcd119168cb6 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts -@@ -135,6 +135,213 @@ - pinctrl-0 = <&vcc50_hdmi_en>; - }; - -+&gpio0 { -+ gpio-line-names = "PMIC_SLEEP_AP", -+ "DDRIO_PWROFF", -+ "DDRIO_RETEN", -+ "TS3A227E_INT_L", -+ "PMIC_INT_L", -+ "PWR_KEY_L", -+ "AP_LID_INT_L", -+ "EC_IN_RW", -+ -+ "AC_PRESENT_AP", -+ /* -+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call -+ * it REC_MODE_L. -+ */ -+ "RECOVERY_SW_L", -+ "OTP_OUT", -+ "HOST1_PWR_EN", -+ "USBOTG_PWREN_H", -+ "AP_WARM_RESET_H", -+ "nFALUT2", -+ "I2C0_SDA_PMIC", -+ -+ "I2C0_SCL_PMIC", -+ "SUSPEND_L", -+ "USB_INT"; -+}; -+ -+&gpio2 { -+ gpio-line-names = "CONFIG0", -+ "CONFIG1", -+ "CONFIG2", -+ "", -+ "", -+ "", -+ "", -+ "CONFIG3", -+ -+ "", -+ "EMMC_RST_L", -+ "", -+ "", -+ "BL_PWR_EN", -+ "AVDD_1V8_DISP_EN"; -+}; -+ -+&gpio3 { -+ gpio-line-names = "FLASH0_D0", -+ "FLASH0_D1", -+ "FLASH0_D2", -+ "FLASH0_D3", -+ "FLASH0_D4", -+ "FLASH0_D5", -+ "FLASH0_D6", -+ "FLASH0_D7", -+ -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "FLASH0_CS2/EMMC_CMD", -+ "", -+ "FLASH0_DQS/EMMC_CLKO"; -+}; -+ -+&gpio4 { -+ gpio-line-names = "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "UART0_RXD", -+ "UART0_TXD", -+ "UART0_CTS", -+ "UART0_RTS", -+ "SDIO0_D0", -+ "SDIO0_D1", -+ "SDIO0_D2", -+ "SDIO0_D3", -+ -+ "SDIO0_CMD", -+ "SDIO0_CLK", -+ "BT_DEV_WAKE", /* Maybe missing from mighty? */ -+ "", -+ "WIFI_ENABLE_H", -+ "BT_ENABLE_L", -+ "WIFI_HOST_WAKE", -+ "BT_HOST_WAKE"; -+}; -+ -+&gpio5 { -+ gpio-line-names = "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "", -+ "", -+ "", -+ "", -+ "SPI0_CLK", -+ "SPI0_CS0", -+ "SPI0_TXD", -+ "SPI0_RXD", -+ -+ "", -+ "", -+ "", -+ "VCC50_HDMI_EN"; -+}; -+ -+&gpio6 { -+ gpio-line-names = "I2S0_SCLK", -+ "I2S0_LRCK_RX", -+ "I2S0_LRCK_TX", -+ "I2S0_SDI", -+ "I2S0_SDO0", -+ "HP_DET_H", -+ "ALS_INT", -+ "INT_CODEC", -+ -+ "I2S0_CLK", -+ "I2C2_SDA", -+ "I2C2_SCL", -+ "MICDET", -+ "", -+ "", -+ "", -+ "", -+ -+ "SDMMC_D0", -+ "SDMMC_D1", -+ "SDMMC_D2", -+ "SDMMC_D3", -+ "SDMMC_CLK", -+ "SDMMC_CMD"; -+}; -+ -+&gpio7 { -+ gpio-line-names = "LCDC_BL", -+ "PWM_LOG", -+ "BL_EN", -+ "TRACKPAD_INT", -+ "TPM_INT_H", -+ "SDMMC_DET_L", -+ /* -+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call -+ * it FW_WP_AP. -+ */ -+ "AP_FLASH_WP_L", -+ "EC_INT", -+ -+ "CPU_NMI", -+ "DVSOK", -+ "SDMMC_WP", /* mighty only */ -+ "EDP_HPD", -+ "DVS1", -+ "nFALUT1", /* nFAULT1 on jaq */ -+ "LCD_EN", -+ "DVS2", -+ -+ "VCC5V_GOOD_H", -+ "I2C4_SDA_TP", -+ "I2C4_SCL_TP", -+ "I2C5_SDA_HDMI", -+ "I2C5_SCL_HDMI", -+ "5V_DRV", -+ "UART2_RXD", -+ "UART2_TXD"; -+}; -+ -+&gpio8 { -+ gpio-line-names = "RAM_ID0", -+ "RAM_ID1", -+ "RAM_ID2", -+ "RAM_ID3", -+ "I2C1_SDA_TPM", -+ "I2C1_SCL_TPM", -+ "SPI2_CLK", -+ "SPI2_CS0", -+ -+ "SPI2_RXD", -+ "SPI2_TXD"; -+}; -+ - &pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { -diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts -index 945e80801292..aa352d40c991 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts -@@ -252,6 +252,157 @@ - }; - }; - -+&gpio0 { -+ gpio-line-names = "PMIC_SLEEP_AP", -+ "", -+ "", -+ "", -+ "PMIC_INT_L", -+ "POWER_BUTTON_L", -+ "", -+ "", -+ -+ "", -+ /* -+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call -+ * it REC_MODE_L. -+ */ -+ "RECOVERY_SW_L", -+ "OT_RESET", -+ "", -+ "", -+ "AP_WARM_RESET_H", -+ "", -+ "I2C0_SDA_PMIC", -+ -+ "I2C0_SCL_PMIC", -+ "", -+ "nFALUT"; -+}; -+ -+&gpio2 { -+ gpio-line-names = "CONFIG0", -+ "CONFIG1", -+ "CONFIG2", -+ "", -+ "", -+ "", -+ "", -+ "CONFIG3", -+ -+ "", -+ "EMMC_RST_L"; -+}; -+ -+&gpio3 { -+ gpio-line-names = "FLASH0_D0", -+ "FLASH0_D1", -+ "FLASH0_D2", -+ "FLASH0_D3", -+ "FLASH0_D4", -+ "FLASH0_D5", -+ "FLASH0_D6", -+ "FLASH0_D7", -+ -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "FLASH0_CS2/EMMC_CMD", -+ "", -+ "FLASH0_DQS/EMMC_CLKO"; -+}; -+ -+&gpio4 { -+ gpio-line-names = "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "UART0_RXD", -+ "UART0_TXD", -+ "UART0_CTS_L", -+ "UART0_RTS_L", -+ "SDIO0_D0", -+ "SDIO0_D1", -+ "SDIO0_D2", -+ "SDIO0_D3", -+ -+ "SDIO0_CMD", -+ "SDIO0_CLK", -+ "BT_DEV_WAKE", -+ "", -+ "WIFI_ENABLE_H", -+ "BT_ENABLE_L", -+ "WIFI_HOST_WAKE", -+ "BT_HOST_WAKE"; -+}; -+ -+&gpio7 { -+ gpio-line-names = "", -+ "PWM_LOG", -+ "", -+ "", -+ "TPM_INT_H", -+ "SDMMC_DET_L", -+ /* -+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call -+ * it FW_WP_AP. -+ */ -+ "AP_FLASH_WP_L", -+ "", -+ -+ "CPU_NMI", -+ "DVSOK", -+ "HDMI_WAKE", -+ "POWER_HDMI_ON", -+ "DVS1", -+ "", -+ "", -+ "DVS2", -+ -+ "HDMI_CEC", -+ "", -+ "", -+ "I2C5_SDA_HDMI", -+ "I2C5_SCL_HDMI", -+ "", -+ "UART2_RXD", -+ "UART2_TXD"; -+}; -+ -+&gpio8 { -+ gpio-line-names = "RAM_ID0", -+ "RAM_ID1", -+ "RAM_ID2", -+ "RAM_ID3", -+ "I2C1_SDA_TPM", -+ "I2C1_SCL_TPM", -+ "SPI2_CLK", -+ "SPI2_CS0", -+ -+ "SPI2_RXD", -+ "SPI2_TXD"; -+}; -+ - &pinctrl { - hdmi { - power_hdmi_on: power-hdmi-on { -diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts -index 9a87017347ea..9b140db04456 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts -@@ -113,6 +113,213 @@ - pinctrl-0 = <&vcc50_hdmi_en>; - }; - -+&gpio0 { -+ gpio-line-names = "PMIC_SLEEP_AP", -+ "DDRIO_PWROFF", -+ "DDRIO_RETEN", -+ "TS3A227E_INT_L", -+ "PMIC_INT_L", -+ "PWR_KEY_L", -+ "AP_LID_INT_L", -+ "EC_IN_RW", -+ -+ "AC_PRESENT_AP", -+ /* -+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call -+ * it REC_MODE_L. -+ */ -+ "RECOVERY_SW_L", -+ "OTP_OUT", -+ "HOST1_PWR_EN", -+ "USBOTG_PWREN_H", -+ "AP_WARM_RESET_H", -+ "nFALUT2", -+ "I2C0_SDA_PMIC", -+ -+ "I2C0_SCL_PMIC", -+ "SUSPEND_L", -+ "USB_INT"; -+}; -+ -+&gpio2 { -+ gpio-line-names = "CONFIG0", -+ "CONFIG1", -+ "CONFIG2", -+ "", -+ "", -+ "", -+ "", -+ "CONFIG3", -+ -+ "PWRLIMIT#_CPU", -+ "EMMC_RST_L", -+ "", -+ "", -+ "BL_PWR_EN", -+ "AVDD_1V8_DISP_EN"; -+}; -+ -+&gpio3 { -+ gpio-line-names = "FLASH0_D0", -+ "FLASH0_D1", -+ "FLASH0_D2", -+ "FLASH0_D3", -+ "FLASH0_D4", -+ "FLASH0_D5", -+ "FLASH0_D6", -+ "FLASH0_D7", -+ -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "FLASH0_CS2/EMMC_CMD", -+ "", -+ "FLASH0_DQS/EMMC_CLKO"; -+}; -+ -+&gpio4 { -+ gpio-line-names = "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "UART0_RXD", -+ "UART0_TXD", -+ "UART0_CTS", -+ "UART0_RTS", -+ "SDIO0_D0", -+ "SDIO0_D1", -+ "SDIO0_D2", -+ "SDIO0_D3", -+ -+ "SDIO0_CMD", -+ "SDIO0_CLK", -+ "BT_DEV_WAKE", -+ "", -+ "WIFI_ENABLE_H", -+ "BT_ENABLE_L", -+ "WIFI_HOST_WAKE", -+ "BT_HOST_WAKE"; -+}; -+ -+&gpio5 { -+ gpio-line-names = "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ "", -+ -+ "", -+ "", -+ "", -+ "", -+ "SPI0_CLK", -+ "SPI0_CS0", -+ "SPI0_TXD", -+ "SPI0_RXD", -+ -+ "", -+ "", -+ "", -+ "VCC50_HDMI_EN"; -+}; -+ -+&gpio6 { -+ gpio-line-names = "I2S0_SCLK", -+ "I2S0_LRCK_RX", -+ "I2S0_LRCK_TX", -+ "I2S0_SDI", -+ "I2S0_SDO0", -+ "HP_DET_H", -+ "ALS_INT", /* not connected */ -+ "INT_CODEC", -+ -+ "I2S0_CLK", -+ "I2C2_SDA", -+ "I2C2_SCL", -+ "MICDET", -+ "", -+ "", -+ "", -+ "", -+ -+ "SDMMC_D0", -+ "SDMMC_D1", -+ "SDMMC_D2", -+ "SDMMC_D3", -+ "SDMMC_CLK", -+ "SDMMC_CMD"; -+}; -+ -+&gpio7 { -+ gpio-line-names = "LCDC_BL", -+ "PWM_LOG", -+ "BL_EN", -+ "TRACKPAD_INT", -+ "TPM_INT_H", -+ "SDMMC_DET_L", -+ /* -+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call -+ * it FW_WP_AP. -+ */ -+ "AP_FLASH_WP_L", -+ "EC_INT", -+ -+ "CPU_NMI", -+ "DVS_OK", -+ "", -+ "EDP_HOTPLUG", -+ "DVS1", -+ "nFALUT1", -+ "LCD_EN", -+ "DVS2", -+ -+ "VCC5V_GOOD_H", -+ "I2C4_SDA_TP", -+ "I2C4_SCL_TP", -+ "I2C5_SDA_HDMI", -+ "I2C5_SCL_HDMI", -+ "5V_DRV", -+ "UART2_RXD", -+ "UART2_TXD"; -+}; -+ -+&gpio8 { -+ gpio-line-names = "RAM_ID0", -+ "RAM_ID1", -+ "RAM_ID2", -+ "RAM_ID3", -+ "I2C1_SDA_TPM", -+ "I2C1_SCL_TPM", -+ "SPI2_CLK", -+ "SPI2_CS0", -+ -+ "SPI2_RXD", -+ "SPI2_TXD"; -+}; -+ - &pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch deleted file mode 100644 index cba84ed..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch +++ /dev/null @@ -1,47 +0,0 @@ -From c077d9d717dc481a6a95f9ef2562ef6bda74fbdf Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Thu, 2 May 2019 15:53:35 -0700 -Subject: [PATCH 46/54] ARM: dts: rockchip: Add unwedge pinctrl entries for - dw_hdmi on rk3288 - -This adds the "unwedge" pinctrl entries introduced by a recent dw_hdmi -change that can unwedge the dw_hdmi i2c bus in some cases. It's -expected that any boards using this would add: - - pinctrl-names = "default", "unwedge"; - pinctrl-0 = <&hdmi_ddc>; - pinctrl-1 = <&hdmi_ddc_unwedge>; - -Note that this isn't added by default because some boards may choose -to mux i2c5 for their DDC bus (if that is more tested for them). - -Signed-off-by: Douglas Anderson -Reviewed-by: Sean Paul -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 766d1cf51a5b..cc893e154fe5 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1547,6 +1547,15 @@ - rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; -+ -+ hdmi_ddc_unwedge: hdmi-ddc-unwedge { -+ rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, -+ <7 RK_PC4 2 &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcfg_output_low: pcfg-output-low { -+ output-low; - }; - - pcfg_pull_up: pcfg-pull-up { --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch deleted file mode 100644 index e7b03a8..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch +++ /dev/null @@ -1,155 +0,0 @@ -From b8925b7c2f867df6ce3e20deb4b3e2b9b32b20ff Mon Sep 17 00:00:00 2001 -From: Matthias Kaehlcke -Date: Wed, 5 Jun 2019 13:43:19 -0700 -Subject: [PATCH 48/54] ARM: dts: rockchip: Split GPIO keys for veyron into - multiple devices - -With a single device DT overrides can become messy, especially when -keys are added or removed. Multiple devices also allow to -enable/disable wakeup per key/group. - -Signed-off-by: Matthias Kaehlcke -[used actual switch+event constants in new lid-switch entry] -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 27 ++++++++++-------- - arch/arm/boot/dts/rk3288-veyron-minnie.dts | 38 +++++++++++++------------ - arch/arm/boot/dts/rk3288-veyron-pinky.dts | 2 +- - arch/arm/boot/dts/rk3288-veyron.dtsi | 4 +-- - 4 files changed, 38 insertions(+), 33 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi -index fbef34578100..5727017f34b2 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi -+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi -@@ -70,6 +70,21 @@ - pinctrl-0 = <&ac_present_ap>; - }; - -+ lid_switch: lid-switch { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ap_lid_int_l>; -+ -+ lid { -+ label = "Lid"; -+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; -+ wakeup-source; -+ linux,code = ; -+ linux,input-type = ; -+ debounce-interval = <1>; -+ }; -+ }; -+ - panel: panel { - compatible ="innolux,n116bge", "simple-panel"; - status = "okay"; -@@ -149,18 +164,6 @@ - status = "okay"; - }; - --&gpio_keys { -- pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; -- lid { -- label = "Lid"; -- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; -- wakeup-source; -- linux,code = <0>; /* SW_LID */ -- linux,input-type = <5>; /* EV_SW */ -- debounce-interval = <1>; -- }; --}; -- - &pwm0 { - status = "okay"; - }; -diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts -index a65099b4aef1..b2cc70a08554 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts -@@ -48,6 +48,26 @@ - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; -+ -+ volume_buttons: volume-buttons { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&volum_down_l &volum_up_l>; -+ -+ volum_down { -+ label = "Volum_down"; -+ gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <100>; -+ }; -+ -+ volum_up { -+ label = "Volum_up"; -+ gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ debounce-interval = <100>; -+ }; -+ }; - }; - - &backlight { -@@ -90,24 +110,6 @@ - pwm-off-delay-ms = <200>; - }; - --&gpio_keys { -- pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>; -- -- volum_down { -- label = "Volum_down"; -- gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; -- linux,code = ; -- debounce-interval = <100>; -- }; -- -- volum_up { -- label = "Volum_up"; -- gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; -- linux,code = ; -- debounce-interval = <100>; -- }; --}; -- - &i2c_tunnel { - battery: bq27500@55 { - compatible = "ti,bq27500"; -diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts -index 9645be7b3d8c..9b6f4d9b03b6 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts -@@ -35,7 +35,7 @@ - force-hpd; - }; - --&gpio_keys { -+&lid_switch { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - - power { -diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi -index c574844a6bb2..3257ca90f0e8 100644 ---- a/arch/arm/boot/dts/rk3288-veyron.dtsi -+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi -@@ -23,11 +23,11 @@ - reg = <0x0 0x0 0x0 0x80000000>; - }; - -- gpio_keys: gpio-keys { -+ power_button: power-button { - compatible = "gpio-keys"; -- - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; -+ - power { - label = "Power"; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch deleted file mode 100644 index 16b24f7..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 1d390437f605db28596ad4c4bfeca2fed052c025 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Mon, 20 May 2019 10:56:05 -0700 -Subject: [PATCH 50/54] ARM: dts: rockchip: Allow wakeup from rk3288-veyron's - dwc2 USB ports - -We want to be able to wake from USB if a device is plugged in that -wants remote wakeup. Enable it on both dwc2 controllers. - -NOTE: this is added specifically to veyron and not to rk3288 in -general since it's not known whether all rk3288 boards are designed to -support USB wakeup. It is plausible that some boards could shut down -important rails in S3. - -Also note that currently wakeup doesn't seem to happen unless you use -the "deep" suspend mode (where SDRAM is turned off). Presumably the -shallow suspend mode is gating some sort of clock that's important but -I couldn't easily figure out how to get it working. - -Signed-off-by: Douglas Anderson -Signed-off-by: Felipe Balbi ---- - arch/arm/boot/dts/rk3288-veyron.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi -index 1252522392c7..1d8bfed7830c 100644 ---- a/arch/arm/boot/dts/rk3288-veyron.dtsi -+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi -@@ -424,6 +424,7 @@ - - &usb_host1 { - status = "okay"; -+ snps,need-phy-for-wake; - }; - - &usb_otg { -@@ -432,6 +433,7 @@ - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&usbphy0>; - dr_mode = "host"; -+ snps,need-phy-for-wake; - }; - - &vopb { --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch b/resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch deleted file mode 100644 index eb33aeb..0000000 --- a/resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 4db11c378ab1e170c3a197ea3719ffe54cd06637 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Wed, 19 Jun 2019 11:34:25 -0700 -Subject: [PATCH 51/54] ARM: dts: rockchip: Configure BT_DEV_WAKE in on - rk3288-veyron - -This is the other half of the hacky solution from commit f497ab6b4bb8 -("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on -veyron"). Specifically the LPM driver that the Broadcom Bluetooth -expects to have (but is missing in mainline) has two halves of the -equation: BT_HOST_WAKE and BT_DEV_WAKE. The BT_HOST_WAKE (which was -handled in the previous commit) is the one that lets the Bluetooth -wake the system up. The BT_DEV_WAKE (this patch) tells the Bluetooth -that it's OK to go into a low power mode. That means we were burning -a bit of extra power in S3 without this patch. Measurements are a bit -noisy, but it appears to be a few mA worth of difference. - -NOTE: Though these pins don't do much on systems with Marvell -Bluetooth, downstream kernels set it on all veyron boards so we'll do -the same. - -Signed-off-by: Douglas Anderson -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 ++ - arch/arm/boot/dts/rk3288-veyron.dtsi | 20 ++++++++++++++++++++ - 2 files changed, 22 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi -index 5727017f34b2..1cadb522fd0d 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi -+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi -@@ -237,6 +237,7 @@ - - /* Wake only */ - &suspend_l_wake -+ &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ -@@ -246,6 +247,7 @@ - - /* Sleep only */ - &suspend_l_sleep -+ &bt_dev_wake_sleep - >; - - backlight { -diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi -index e2635ad574e7..53d2f2452868 100644 ---- a/arch/arm/boot/dts/rk3288-veyron.dtsi -+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi -@@ -485,12 +485,18 @@ - &ddr0_retention - &ddrio_pwroff - &global_pwroff -+ -+ /* Wake only */ -+ &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff -+ -+ /* Sleep only */ -+ &bt_dev_wake_sleep - >; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { -@@ -596,6 +602,20 @@ - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; - }; -+ -+ /* -+ * These pins are only present on very new veyron boards; on -+ * older boards bt_dev_wake is simply always high. Note that -+ * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt -+ * to map this pin everywhere -+ */ -+ bt_dev_wake_sleep: bt-dev-wake-sleep { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; -+ }; -+ -+ bt_dev_wake_awake: bt-dev-wake-awake { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; -+ }; - }; - - tpm { --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch deleted file mode 100644 index a554c8a..0000000 --- a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d991f855cb4f84c638e2016818259720ceed4191 Mon Sep 17 00:00:00 2001 -From: Bartlomiej Zolnierkiewicz -Date: Mon, 20 May 2019 16:14:33 +0200 -Subject: [PATCH 44/53] usb: remove redundant 'default n' from Kconfig-s - -'default n' is the default value for any bool or tristate Kconfig -setting so there is no need to write it explicitly. - -Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO -is not set' for visible symbols") the Kconfig behavior is the same -regardless of 'default n' being present or not: - - ... - One side effect of (and the main motivation for) this change is making - the following two definitions behave exactly the same: - - config FOO - bool - - config FOO - bool - default n - - With this change, neither of these will generate a - '# CONFIG_FOO is not set' line (assuming FOO isn't selected/implied). - That might make it clearer to people that a bare 'default n' is - redundant. - ... - -Signed-off-by: Bartlomiej Zolnierkiewicz -Signed-off-by: Greg Kroah-Hartman ---- - drivers/usb/dwc2/Kconfig | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig -index 68d095ae2865..16e1aa304edc 100644 ---- a/drivers/usb/dwc2/Kconfig -+++ b/drivers/usb/dwc2/Kconfig -@@ -58,7 +58,6 @@ config USB_DWC2_PCI - tristate "DWC2 PCI" - depends on USB_PCI - depends on USB_GADGET || !USB_GADGET -- default n - select NOP_USB_XCEIV - help - The Designware USB2.0 PCI interface module for controllers --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch deleted file mode 100644 index 3cb1304..0000000 --- a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch +++ /dev/null @@ -1,164 +0,0 @@ -From c846b03ff767149d75d4d8dca6d3d4945a21074a Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Mon, 20 May 2019 10:56:04 -0700 -Subject: [PATCH 51/53] USB: dwc2: Don't turn off the usbphy in suspend if - wakeup is enabled - -If the 'snps,need-phy-for-wake' is set in the device tree then: - -- We know that we can wakeup, so call device_set_wakeup_capable(). - The USB core will use this knowledge to enable wakeup by default. -- We know that we should keep the PHY on during suspend if something - on our root hub needs remote wakeup. This requires the patch (USB: - Export usb_wakeup_enabled_descendants()). Note that we don't keep - the PHY on at suspend time if it's not needed because it would be a - power draw. - -If we later find some users of dwc2 that can support wakeup without -keeping the PHY on we may want to add a way to call -device_set_wakeup_capable() without keeping the PHY on at suspend -time. - -Signed-off-by: Douglas Anderson -Signed-off-by: Chris Zhong -Signed-off-by: Felipe Balbi ---- - drivers/usb/dwc2/core.h | 8 ++++++++ - drivers/usb/dwc2/hcd.c | 19 +++++++++++++++++++ - drivers/usb/dwc2/platform.c | 23 ++++++++++++++++++++--- - 3 files changed, 47 insertions(+), 3 deletions(-) - -diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h -index 152ac41dfb2d..d08d070a0fb6 100644 ---- a/drivers/usb/dwc2/core.h -+++ b/drivers/usb/dwc2/core.h -@@ -861,6 +861,9 @@ struct dwc2_hregs_backup { - * @hibernated: True if core is hibernated - * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a - * remote wakeup. -+ * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. -+ * @need_phy_for_wake: Quirk saying that we should keep the PHY on at -+ * suspend if we need USB to wake us up. - * @frame_number: Frame number read from the core. For both device - * and host modes. The value ranges are from 0 - * to HFNUM_MAX_FRNUM. -@@ -1049,6 +1052,8 @@ struct dwc2_hsotg { - unsigned int ll_hw_enabled:1; - unsigned int hibernated:1; - unsigned int reset_phy_on_wake:1; -+ unsigned int need_phy_for_wake:1; -+ unsigned int phy_off_for_suspend:1; - u16 frame_number; - - struct phy *phy; -@@ -1438,6 +1443,7 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); - int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); - int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, - int rem_wakeup, int reset); -+bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); - static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) - { schedule_work(&hsotg->phy_reset_work); } - #else -@@ -1463,6 +1469,8 @@ static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) - static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, - int rem_wakeup, int reset) - { return 0; } -+static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) -+{ return false; } - static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} - - #endif -diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c -index 2192a2873c7c..4c78a390c958 100644 ---- a/drivers/usb/dwc2/hcd.c -+++ b/drivers/usb/dwc2/hcd.c -@@ -5587,3 +5587,22 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, - dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); - return ret; - } -+ -+bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) -+{ -+ struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub; -+ -+ /* If the controller isn't allowed to wakeup then we can power off. */ -+ if (!device_may_wakeup(dwc2->dev)) -+ return true; -+ -+ /* -+ * We don't want to power off the PHY if something under the -+ * root hub has wakeup enabled. -+ */ -+ if (usb_wakeup_enabled_descendants(root_hub)) -+ return false; -+ -+ /* No reason to keep the PHY powered, so allow poweroff */ -+ return true; -+} -diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c -index d10a7f8daec3..3e6c3c8a32ff 100644 ---- a/drivers/usb/dwc2/platform.c -+++ b/drivers/usb/dwc2/platform.c -@@ -447,6 +447,10 @@ static int dwc2_driver_probe(struct platform_device *dev) - if (retval) - goto error; - -+ hsotg->need_phy_for_wake = -+ of_property_read_bool(dev->dev.of_node, -+ "snps,need-phy-for-wake"); -+ - /* - * Reset before dwc2_get_hwparams() then it could get power-on real - * reset value form registers. -@@ -478,6 +482,14 @@ static int dwc2_driver_probe(struct platform_device *dev) - hsotg->gadget_enabled = 1; - } - -+ /* -+ * If we need PHY for wakeup we must be wakeup capable. -+ * When we have a device that can wake without the PHY we -+ * can adjust this condition. -+ */ -+ if (hsotg->need_phy_for_wake) -+ device_set_wakeup_capable(&dev->dev, true); -+ - hsotg->reset_phy_on_wake = - of_property_read_bool(dev->dev.of_node, - "snps,reset-phy-on-wake"); -@@ -516,13 +528,17 @@ static int dwc2_driver_probe(struct platform_device *dev) - static int __maybe_unused dwc2_suspend(struct device *dev) - { - struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); -+ bool is_device_mode = dwc2_is_device_mode(dwc2); - int ret = 0; - -- if (dwc2_is_device_mode(dwc2)) -+ if (is_device_mode) - dwc2_hsotg_suspend(dwc2); - -- if (dwc2->ll_hw_enabled) -+ if (dwc2->ll_hw_enabled && -+ (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) { - ret = __dwc2_lowlevel_hw_disable(dwc2); -+ dwc2->phy_off_for_suspend = true; -+ } - - return ret; - } -@@ -532,11 +548,12 @@ static int __maybe_unused dwc2_resume(struct device *dev) - struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); - int ret = 0; - -- if (dwc2->ll_hw_enabled) { -+ if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) { - ret = __dwc2_lowlevel_hw_enable(dwc2); - if (ret) - return ret; - } -+ dwc2->phy_off_for_suspend = false; - - if (dwc2_is_device_mode(dwc2)) - ret = dwc2_hsotg_resume(dwc2); --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch b/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch deleted file mode 100644 index 43f2253..0000000 --- a/resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch +++ /dev/null @@ -1,53 +0,0 @@ -From ad408a1596b45868e38d0504f2ec1d5fb06f17d4 Mon Sep 17 00:00:00 2001 -From: Guenter Roeck -Date: Wed, 29 May 2019 13:54:43 -0700 -Subject: [PATCH 52/53] Revert "usb: dwc2: host: Setting qtd to NULL after - freeing it" - -This reverts commit b0d659022e5c96ee5c4bd62d22d3da2d66de306b. - -The reverted commit does nothing but adding two unnecessary lines -of code. It sets a local variable to NULL in two functions, but -that variable is not used anywhere in the rest of those functions. -This is just confusing, so let's remove it. - -Cc: Vardan Mikayelyan -Cc: John Youn -Cc: Douglas Anderson -Cc: Felipe Balbi -Acked-by: Minas Harutyunyan -Reviewed-by: Douglas Anderson -Signed-off-by: Guenter Roeck -Signed-off-by: Felipe Balbi ---- - drivers/usb/dwc2/hcd.c | 1 - - drivers/usb/dwc2/hcd.h | 1 - - 2 files changed, 2 deletions(-) - -diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c -index 4c78a390c958..ee144ff8af5b 100644 ---- a/drivers/usb/dwc2/hcd.c -+++ b/drivers/usb/dwc2/hcd.c -@@ -4685,7 +4685,6 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, - spin_unlock_irqrestore(&hsotg->lock, flags); - urb->hcpriv = NULL; - kfree(qtd); -- qtd = NULL; - fail1: - if (qh_allocated) { - struct dwc2_qtd *qtd2, *qtd2_tmp; -diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h -index ce6445a06588..8ca6d12a6f57 100644 ---- a/drivers/usb/dwc2/hcd.h -+++ b/drivers/usb/dwc2/hcd.h -@@ -582,7 +582,6 @@ static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, - { - list_del(&qtd->qtd_list_entry); - kfree(qtd); -- qtd = NULL; - } - - /* Descriptor DMA support functions */ --- -2.11.0 - diff --git a/resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch b/resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch deleted file mode 100644 index fe0aaf7..0000000 --- a/resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: Douglas Anderson -Date: Tue, 07 May 2019 13:49:58 -0700 (PDT) - -When calculating the MMC phase we can just use clk_hw_get_rate() -instead of clk_get_rate(). This avoids recalculating the rate. - -Suggested-by: Stephen Boyd -Signed-off-by: Douglas Anderson ---- - - drivers/clk/rockchip/clk-mmc-phase.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c -index 026a26bb702d..07526f64dbfd 100644 ---- a/drivers/clk/rockchip/clk-mmc-phase.c -+++ b/drivers/clk/rockchip/clk-mmc-phase.c -@@ -55,7 +55,7 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, - static int rockchip_mmc_get_phase(struct clk_hw *hw) - { - struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); -- unsigned long rate = clk_get_rate(hw->clk); -+ unsigned long rate = clk_hw_get_rate(hw); - u32 raw_value; - u16 degrees; - u32 delay_num = 0; -@@ -86,7 +86,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) - static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) - { - struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); -- unsigned long rate = clk_get_rate(hw->clk); -+ unsigned long rate = clk_hw_get_rate(hw); - u8 nineties, remainder; - u8 delay_num; - u32 raw_value; -