0002-clk-rockchip-add-all-known-operating-points-to-the-a.patch 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950
  1. From e0c5a419cf5464cd02996431afa98e3b22dc6801 Mon Sep 17 00:00:00 2001
  2. From: Myy <myy@miouyouyou.fr>
  3. Date: Mon, 17 Jul 2017 23:14:48 +0000
  4. Subject: [PATCH] clk: rockchip: add all known operating points to the allowed
  5. CPU freqs
  6. Patch from Willy Tarreau
  7. Original commit message :
  8. At least 1920 MHz runs stable on the MiQi even on openssl speed -multi 4,
  9. which is by far the most intensive workload, and 1992/2016 work fine on
  10. the CS-008 until it starts to heat too much. So add all of them so that
  11. the device tree can simply manipulate them.
  12. Signed-off-by: Myy <myy@miouyouyou.fr>
  13. ---
  14. drivers/clk/rockchip/clk-rk3288.c | 17 +++++++++++++++++
  15. 1 file changed, 17 insertions(+)
  16. diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
  17. index 753c649..fd2058f 100644
  18. --- a/drivers/clk/rockchip/clk-rk3288.c
  19. +++ b/drivers/clk/rockchip/clk-rk3288.c
  20. @@ -145,6 +145,23 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
  21. }
  22. static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
  23. + RK3288_CPUCLK_RATE(2208000000U, 1, 3, 1, 3, 3),
  24. + RK3288_CPUCLK_RATE(2184000000U, 1, 3, 1, 3, 3),
  25. + RK3288_CPUCLK_RATE(2160000000U, 1, 3, 1, 3, 3),
  26. + RK3288_CPUCLK_RATE(2136000000, 1, 3, 1, 3, 3),
  27. + RK3288_CPUCLK_RATE(2112000000, 1, 3, 1, 3, 3),
  28. + RK3288_CPUCLK_RATE(2088000000, 1, 3, 1, 3, 3),
  29. + RK3288_CPUCLK_RATE(2064000000, 1, 3, 1, 3, 3),
  30. + RK3288_CPUCLK_RATE(2040000000, 1, 3, 1, 3, 3),
  31. + RK3288_CPUCLK_RATE(2016000000, 1, 3, 1, 3, 3),
  32. + RK3288_CPUCLK_RATE(1992000000, 1, 3, 1, 3, 3),
  33. + RK3288_CPUCLK_RATE(1968000000, 1, 3, 1, 3, 3),
  34. + RK3288_CPUCLK_RATE(1944000000, 1, 3, 1, 3, 3),
  35. + RK3288_CPUCLK_RATE(1920000000, 1, 3, 1, 3, 3),
  36. + RK3288_CPUCLK_RATE(1896000000, 1, 3, 1, 3, 3),
  37. + RK3288_CPUCLK_RATE(1872000000, 1, 3, 1, 3, 3),
  38. + RK3288_CPUCLK_RATE(1848000000, 1, 3, 1, 3, 3),
  39. + RK3288_CPUCLK_RATE(1824000000, 1, 3, 1, 3, 3),
  40. RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
  41. RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
  42. RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
  43. --
  44. 2.10.2