1cd8ae19a9
Add backported patched from 5.x from usb related fixes Up kernel version to most recent lts
58 lines
1.6 KiB
Diff
58 lines
1.6 KiB
Diff
From 6773af2684b7bc1b7b2d9ef874599cccaba2559e Mon Sep 17 00:00:00 2001
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From: Caesar Wang <caesar.wang@rock-chips.com>
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Date: Tue, 9 Apr 2019 13:47:07 -0700
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Subject: [PATCH 28/54] ARM: dts: rockchip: fix PWM clock found on RK3288 Socs
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We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect.
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Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
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Signed-off-by: Douglas Anderson <dianders@chromium.org>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm/boot/dts/rk3288.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index aa017abf4f42..171231a0cd9b 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -682,7 +682,7 @@
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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- clocks = <&cru PCLK_PWM>;
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+ clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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@@ -693,7 +693,7 @@
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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- clocks = <&cru PCLK_PWM>;
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+ clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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@@ -704,7 +704,7 @@
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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- clocks = <&cru PCLK_PWM>;
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+ clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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@@ -715,7 +715,7 @@
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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- clocks = <&cru PCLK_PWM>;
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+ clocks = <&cru PCLK_RKPWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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--
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2.11.0
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