47 lines
1.6 KiB
Diff
47 lines
1.6 KiB
Diff
From: Douglas Anderson <dianders@chromium.org>
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Subject: [PATCH] clk: rockchip: Don't yell about bad mmc phases when getting
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Date: Fri, 3 May 2019 14:22:08 -0700
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At boot time, my rk3288-veyron devices yell with 8 lines that look
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like this:
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[ 0.000000] rockchip_mmc_get_phase: invalid clk rate
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This is because the clock framework at clk_register() time tries to
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get the phase but we don't have a parent yet.
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While the errors appear to be harmless they are still ugly and, in
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general, we don't want yells like this in the log unless they are
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important.
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There's no real reason to be yelling here. We can still return
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-EINVAL to indicate that the phase makes no sense without a parent.
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If someone really tries to do tuning and the clock is reported as 0
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then we'll see the yells in rockchip_mmc_set_phase().
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Fixes: 4bf59902b500 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero")
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Signed-off-by: Douglas Anderson <dianders@chromium.org>
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---
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drivers/clk/rockchip/clk-mmc-phase.c | 4 +---
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1 file changed, 1 insertion(+), 3 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
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index 026a26bb702d..dbec84238ecd 100644
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--- a/drivers/clk/rockchip/clk-mmc-phase.c
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+++ b/drivers/clk/rockchip/clk-mmc-phase.c
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@@ -61,10 +61,8 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
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u32 delay_num = 0;
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/* See the comment for rockchip_mmc_set_phase below */
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- if (!rate) {
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- pr_err("%s: invalid clk rate\n", __func__);
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+ if (!rate)
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return -EINVAL;
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- }
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raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
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--
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2.21.0.1020.gf2820cf01a-goog
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