1cd8ae19a9
Add backported patched from 5.x from usb related fixes Up kernel version to most recent lts
67 lines
2.0 KiB
Diff
67 lines
2.0 KiB
Diff
From 83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775 Mon Sep 17 00:00:00 2001
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From: Matthias Kaehlcke <mka@chromium.org>
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Date: Thu, 16 May 2019 09:29:40 -0700
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Subject: [PATCH 32/54] ARM: dts: rockchip: raise CPU trip point temperature
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for veyron to 100 degC
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This value matches what is used by the downstream Chrome OS 3.14
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kernel, the 'official' kernel for veyron devices. Keep the temperature
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for 'speedy' at 90°C, as in the downstream kernel.
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Increase the temperature for a hardware shutdown to 125°C, which
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matches the downstream configuration and gives the system a chance
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to shut down orderly at the criticial trip point.
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Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
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Reviewed-by: Douglas Anderson <dianders@chromium.org>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++
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arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++
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2 files changed, 9 insertions(+)
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diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
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index 2ac8748a3a0c..b07a07e81551 100644
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--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
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+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
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@@ -64,6 +64,10 @@
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temperature = <70000>;
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};
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+&cpu_crit {
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+ temperature = <90000>;
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+};
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+
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&edp {
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/delete-property/pinctrl-names;
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/delete-property/pinctrl-0;
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diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
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index 1252522392c7..e81f1a0cac83 100644
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--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
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+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
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@@ -123,6 +123,10 @@
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cpu0-supply = <&vdd_cpu>;
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};
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+&cpu_crit {
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+ temperature = <100000>;
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+};
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+
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/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
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&cpu_opp_table {
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/delete-node/ opp-312000000;
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@@ -394,6 +398,7 @@
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rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
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rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
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+ rockchip,hw-tshut-temp = <125000>;
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};
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&uart0 {
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--
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2.11.0
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