1cd8ae19a9
Add backported patched from 5.x from usb related fixes Up kernel version to most recent lts
96 lines
2.9 KiB
Diff
96 lines
2.9 KiB
Diff
From 4db11c378ab1e170c3a197ea3719ffe54cd06637 Mon Sep 17 00:00:00 2001
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From: Douglas Anderson <dianders@chromium.org>
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Date: Wed, 19 Jun 2019 11:34:25 -0700
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Subject: [PATCH 51/54] ARM: dts: rockchip: Configure BT_DEV_WAKE in on
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rk3288-veyron
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This is the other half of the hacky solution from commit f497ab6b4bb8
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("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on
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veyron"). Specifically the LPM driver that the Broadcom Bluetooth
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expects to have (but is missing in mainline) has two halves of the
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equation: BT_HOST_WAKE and BT_DEV_WAKE. The BT_HOST_WAKE (which was
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handled in the previous commit) is the one that lets the Bluetooth
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wake the system up. The BT_DEV_WAKE (this patch) tells the Bluetooth
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that it's OK to go into a low power mode. That means we were burning
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a bit of extra power in S3 without this patch. Measurements are a bit
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noisy, but it appears to be a few mA worth of difference.
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NOTE: Though these pins don't do much on systems with Marvell
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Bluetooth, downstream kernels set it on all veyron boards so we'll do
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the same.
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Signed-off-by: Douglas Anderson <dianders@chromium.org>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 ++
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arch/arm/boot/dts/rk3288-veyron.dtsi | 20 ++++++++++++++++++++
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2 files changed, 22 insertions(+)
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diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
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index 5727017f34b2..1cadb522fd0d 100644
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--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
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+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
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@@ -237,6 +237,7 @@
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/* Wake only */
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&suspend_l_wake
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+ &bt_dev_wake_awake
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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@@ -246,6 +247,7 @@
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/* Sleep only */
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&suspend_l_sleep
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+ &bt_dev_wake_sleep
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>;
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backlight {
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diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
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index e2635ad574e7..53d2f2452868 100644
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--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
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+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
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@@ -485,12 +485,18 @@
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&ddr0_retention
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&ddrio_pwroff
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&global_pwroff
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+
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+ /* Wake only */
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+ &bt_dev_wake_awake
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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&ddr0_retention
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&ddrio_pwroff
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&global_pwroff
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+
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+ /* Sleep only */
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+ &bt_dev_wake_sleep
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>;
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pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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@@ -596,6 +602,20 @@
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sdio0_clk: sdio0-clk {
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rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
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};
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+
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+ /*
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+ * These pins are only present on very new veyron boards; on
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+ * older boards bt_dev_wake is simply always high. Note that
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+ * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
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+ * to map this pin everywhere
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+ */
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+ bt_dev_wake_sleep: bt-dev-wake-sleep {
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+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
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+ };
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+
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+ bt_dev_wake_awake: bt-dev-wake-awake {
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+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
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+ };
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};
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tpm {
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--
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2.11.0
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