cad1891021
Added three patches to fix the mmc issue as described here: https://github.com/SolidHal/Librean/issues/17 Source for the patches is the chrome os kernel. Links to the commits can be found in the issue. Locking into version 4.17.2 for the time being. Better organized patches. Added logic to only apply tested patches on fresh kernel. Moved some debian build improvements in from my devsus master branch, including switching from xfce to lxqt. May be able to add option between the two in the future, as the issue that led to switching DEs may have been with the xorg video drivers that are now skipped by the script and not xfce itself. Cleaned up uneeded old configs
42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From b82f540967f6a732a22bbd236457b864951aeda7 Mon Sep 17 00:00:00 2001
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From: Myy <myy@miouyouyou.fr>
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Date: Sun, 14 May 2017 10:13:26 +0000
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Subject: [PATCH] clk: rockchip: rk3288: prefer vdpu for vcodec clock source
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Patch provided by Randy Li. The original commit message reads :
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_______________
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The RK3288 CRU system clock solution would suggest use
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the vdpu clock source for the VPU(aclk_vpu and hclk_vpu).
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Reading the registers of VPU(both VEPU and VDPU) would become all high
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when the vepu is used as the clock source. It may be a bug in the SoC,
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not sure whether it is fixed at RK3288W.
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Signed-off-by: Randy Li <ayaka@soulik.info>
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_______________
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This also resolves a freeze when loading the OOT Video Codec driver
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Signed-off-by: Myy <myy@miouyouyou.fr>
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---
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drivers/clk/rockchip/clk-rk3288.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index 1227f74..f218256 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -215,7 +215,7 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
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PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
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PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
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-PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vepu", "aclk_vdpu" };
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+PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
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PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
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"sclk_otgphy0_480m" };
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PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
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--
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2.10.2
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