cad1891021
Added three patches to fix the mmc issue as described here: https://github.com/SolidHal/Librean/issues/17 Source for the patches is the chrome os kernel. Links to the commits can be found in the issue. Locking into version 4.17.2 for the time being. Better organized patches. Added logic to only apply tested patches on fresh kernel. Moved some debian build improvements in from my devsus master branch, including switching from xfce to lxqt. May be able to add option between the two in the future, as the issue that led to switching DEs may have been with the xorg video drivers that are now skipped by the script and not xfce itself. Cleaned up uneeded old configs
51 lines
2.0 KiB
Diff
51 lines
2.0 KiB
Diff
From e0c5a419cf5464cd02996431afa98e3b22dc6801 Mon Sep 17 00:00:00 2001
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From: Myy <myy@miouyouyou.fr>
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Date: Mon, 17 Jul 2017 23:14:48 +0000
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Subject: [PATCH] clk: rockchip: add all known operating points to the allowed
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CPU freqs
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Patch from Willy Tarreau
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Original commit message :
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At least 1920 MHz runs stable on the MiQi even on openssl speed -multi 4,
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which is by far the most intensive workload, and 1992/2016 work fine on
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the CS-008 until it starts to heat too much. So add all of them so that
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the device tree can simply manipulate them.
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Signed-off-by: Myy <myy@miouyouyou.fr>
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---
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drivers/clk/rockchip/clk-rk3288.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index 753c649..fd2058f 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -145,6 +145,23 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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}
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static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
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+ RK3288_CPUCLK_RATE(2208000000U, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2184000000U, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2160000000U, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2136000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2112000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2088000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2064000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2040000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(2016000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1992000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1968000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1944000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1920000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1896000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1872000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1848000000, 1, 3, 1, 3, 3),
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+ RK3288_CPUCLK_RATE(1824000000, 1, 3, 1, 3, 3),
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RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
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RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
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RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
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--
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2.10.2
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