0009-ARM-DTSI-rk3288-Adding-cells-addresses-and-size.patch 1.7 KB

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  1. From 7af8d2bf732cb3baab7d926ed8a7e061e7a09ad9 Mon Sep 17 00:00:00 2001
  2. From: Myy Miouyouyou <myy@miouyouyou.fr>
  3. Date: Thu, 19 Oct 2017 21:39:00 +0200
  4. Subject: [PATCH 13/28] ARM: DTSI: rk3288.dtsi: Adding cells addresses and
  5. sizes of MMC nodes
  6. Imported from the Rockchip 4.4 patches.
  7. Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
  8. ---
  9. arch/arm/boot/dts/rk3288.dtsi | 8 ++++++++
  10. 1 file changed, 8 insertions(+)
  11. diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
  12. index be985f02..14ef8202 100644
  13. --- a/arch/arm/boot/dts/rk3288.dtsi
  14. +++ b/arch/arm/boot/dts/rk3288.dtsi
  15. @@ -236,6 +236,8 @@
  16. clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  17. fifo-depth = <0x100>;
  18. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  19. + #address-cells = <1>;
  20. + #size-cells = <0>;
  21. reg = <0x0 0xff0c0000 0x0 0x4000>;
  22. resets = <&cru SRST_MMC0>;
  23. reset-names = "reset";
  24. @@ -250,6 +252,8 @@
  25. clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  26. fifo-depth = <0x100>;
  27. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  28. + #address-cells = <1>;
  29. + #size-cells = <0>;
  30. reg = <0x0 0xff0d0000 0x0 0x4000>;
  31. resets = <&cru SRST_SDIO0>;
  32. reset-names = "reset";
  33. @@ -264,6 +268,8 @@
  34. clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  35. fifo-depth = <0x100>;
  36. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  37. + #address-cells = <1>;
  38. + #size-cells = <0>;
  39. reg = <0x0 0xff0e0000 0x0 0x4000>;
  40. resets = <&cru SRST_SDIO1>;
  41. reset-names = "reset";
  42. @@ -278,6 +284,8 @@
  43. clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  44. fifo-depth = <0x100>;
  45. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  46. + #address-cells = <1>;
  47. + #size-cells = <0>;
  48. reg = <0x0 0xff0f0000 0x0 0x4000>;
  49. resets = <&cru SRST_EMMC>;
  50. reset-names = "reset";
  51. --
  52. 2.11.0