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- From f4480cb8198085607c15e523b49aa21bc38cf62c Mon Sep 17 00:00:00 2001
- From: Myy Miouyouyou <myy@miouyouyou.fr>
- Date: Tue, 21 Nov 2017 21:47:33 +0100
- Subject: [PATCH 1/5] ARM: DTSI: rk3288.dtsi: Define the VPU services
- Still, you will need appropriate drivers to use them.
- Contrary to the previous versions of this patch, these services are :
- * NOT enabled by default;
- * MUST be activated in each individual DTS;
- I currently do not own enough RK3288 boards to ensure that the
- VPU and HEVC MMU + services can be activated without issues.
- Still this patch does not generate issues like the previous one AND
- still enable these services on boot, when activated properly in
- individual DTS files.
- Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
- ---
- arch/arm/boot/dts/rk3288.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 63 insertions(+)
- diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
- index 30b04257..bc3601ac 100644
- --- a/arch/arm/boot/dts/rk3288.dtsi
- +++ b/arch/arm/boot/dts/rk3288.dtsi
- @@ -1182,6 +1182,27 @@
- status = "disabled";
- };
-
- + vpu_service: vpu-service@ff9a0000 {
- + compatible = "rockchip,vpu_service";
- + reg = <0x0 0xff9a0000 0x0 0x800>;
- + interrupts =
- + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- + interrupt-names = "irq_enc", "irq_dec";
- + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- + clock-names = "aclk_vcodec", "hclk_vcodec";
- + power-domains = <&power RK3288_PD_VIDEO>;
- + rockchip,grf = <&grf>;
- + resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
- + reset-names = "video_a", "video_h";
- + iommus = <&vpu_mmu>;
- + iommu_enabled = <1>;
- + dev_mode = <0>;
- + status = "disabled";
- + /* 0 means ion, 1 means drm */
- + allocator = <1>;
- + };
- +
- hevc_mmu: iommu@ff9c0440 {
- compatible = "rockchip,iommu";
- reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
- @@ -1191,6 +1212,48 @@
- status = "disabled";
- };
-
- + hevc_service: hevc-service@ff9c0000 {
- + compatible = "rockchip,hevc_service";
- + reg = <0x0 0xff9c0000 0x0 0x400>;
- + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- + interrupt-names = "irq_dec";
- + clocks =
- + <&cru ACLK_HEVC>,
- + <&cru HCLK_HEVC>,
- + <&cru SCLK_HEVC_CORE>,
- + <&cru SCLK_HEVC_CABAC>;
- + clock-names =
- + "aclk_vcodec",
- + "hclk_vcodec",
- + "clk_core",
- + "clk_cabac";
- + /*
- + * The 4K hevc would also work well with 500/125/300/300,
- + * no more err irq and reset request.
- + */
- + assigned-clocks =
- + <&cru ACLK_HEVC>,
- + <&cru HCLK_HEVC>,
- + <&cru SCLK_HEVC_CORE>,
- + <&cru SCLK_HEVC_CABAC>;
- + assigned-clock-rates =
- + <400000000>,
- + <100000000>,
- + <300000000>,
- + <300000000>;
- +
- + resets = <&cru SRST_HEVC>;
- + reset-names = "video";
- + power-domains = <&power RK3288_PD_HEVC>;
- + rockchip,grf = <&grf>;
- + dev_mode = <1>;
- + iommus = <&hevc_mmu>;
- + iommu_enabled = <1>;
- + status = "disabled";
- + /* 0 means ion, 1 means drm */
- + allocator = <1>;
- + };
- +
- gpu: gpu@ffa30000 {
- compatible = "rockchip,rk3288-mali", "arm,mali-t760";
- reg = <0x0 0xffa30000 0x0 0x10000>;
- --
- 2.14.1
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