diff --git a/build-apu.sh b/build-apu.sh new file mode 100755 index 0000000..6f9d495 --- /dev/null +++ b/build-apu.sh @@ -0,0 +1,66 @@ +#!/usr/bin/env bash + +# for dependencies +# apt install -t build-essential libncurses-dev bison flex libssl-dev libelf-dev + +#if [ $# -ne 3 ] +# then +# echo "No arguments supplied" +#fi + +#flag1=$1 +#flag2=$2 +#flag3=$3 + +flag1="cc{prima_flag}" +flag2="cc{seconda_flag}" +flag3="cc{terza_flag}" +password=`hexdump -n 32 -e '4/4 "%08X"' /dev/urandom` + +echo "[+] Starting build script..." +mkdir -p target/overlay/var/www/html + +echo "[+] Cloning buildroot" +git clone https://github.com/buildroot/buildroot.git target/buildroot + +echo "[+] Adding customization files" +cp -R buildroot/* target/buildroot # copy buildroot configs +sed -i "s/###ROOTPASSWORD###/$password/g" target/buildroot/configs/pcengines_apu2_defconfig +cp -R conf/* target/overlay # copy target system config files +cp -R webpanel/* target/overlay/var/www/html # copy the webpanel +cp -R update/update.sh target/overlay #copy the update script and certificate + +echo "[+] Writing flags" +sed -i "s/##FLAG1##/$flag1/g" target/overlay/var/www/html/includes/config.php +echo $flag2 > target/overlay/flag +chmod 444 target/overlay/flag +mkdir target/overlay/root +chmod 700 target/overlay/root +echo $flag3 > target/overlay/root/flag +chmod 400 target/overlay/root/flag + +echo "[+] Building the keygen" +mkdir -p target/overlay/usr/sbin +gcc -o target/overlay/usr/sbin/cfgbin keygen/keygen.c -static -lm +strip target/overlay/usr/sbin/cfgbin + +echo "[+] Generating Update Key" +mkdir -p target/keys +openssl genrsa -out target/keys/signingkey.pem 2048 +openssl rsa -in target/keys/signingkey.pem -outform PEM -pubout -out target/keys/signingpub.pem +cp target/keys/signingpub.pem target/overlay/pub.pem + +echo "[+] Generating Monitoring SSH Key" +ssh-keygen -t ecdsa -f target/keys/sshkey -q -N "" +mkdir -p target/overlay/root/.ssh +cp target/keys/sshkey target/overlay/root/.ssh/authorized_keys +chmod -R 600 target/overlay/root/.ssh/ + +echo "[+] Saving the root password" +echo $password > target/keys/rootpassword + +echo "[+] Building the image" +N=`grep -c '^processor' /proc/cpuinfo` +cd target/buildroot +make pcengines_apu2_defconfig +make -j$N diff --git a/build-tgr.sh b/build-tgr.sh new file mode 100755 index 0000000..6f9d495 --- /dev/null +++ b/build-tgr.sh @@ -0,0 +1,66 @@ +#!/usr/bin/env bash + +# for dependencies +# apt install -t build-essential libncurses-dev bison flex libssl-dev libelf-dev + +#if [ $# -ne 3 ] +# then +# echo "No arguments supplied" +#fi + +#flag1=$1 +#flag2=$2 +#flag3=$3 + +flag1="cc{prima_flag}" +flag2="cc{seconda_flag}" +flag3="cc{terza_flag}" +password=`hexdump -n 32 -e '4/4 "%08X"' /dev/urandom` + +echo "[+] Starting build script..." +mkdir -p target/overlay/var/www/html + +echo "[+] Cloning buildroot" +git clone https://github.com/buildroot/buildroot.git target/buildroot + +echo "[+] Adding customization files" +cp -R buildroot/* target/buildroot # copy buildroot configs +sed -i "s/###ROOTPASSWORD###/$password/g" target/buildroot/configs/pcengines_apu2_defconfig +cp -R conf/* target/overlay # copy target system config files +cp -R webpanel/* target/overlay/var/www/html # copy the webpanel +cp -R update/update.sh target/overlay #copy the update script and certificate + +echo "[+] Writing flags" +sed -i "s/##FLAG1##/$flag1/g" target/overlay/var/www/html/includes/config.php +echo $flag2 > target/overlay/flag +chmod 444 target/overlay/flag +mkdir target/overlay/root +chmod 700 target/overlay/root +echo $flag3 > target/overlay/root/flag +chmod 400 target/overlay/root/flag + +echo "[+] Building the keygen" +mkdir -p target/overlay/usr/sbin +gcc -o target/overlay/usr/sbin/cfgbin keygen/keygen.c -static -lm +strip target/overlay/usr/sbin/cfgbin + +echo "[+] Generating Update Key" +mkdir -p target/keys +openssl genrsa -out target/keys/signingkey.pem 2048 +openssl rsa -in target/keys/signingkey.pem -outform PEM -pubout -out target/keys/signingpub.pem +cp target/keys/signingpub.pem target/overlay/pub.pem + +echo "[+] Generating Monitoring SSH Key" +ssh-keygen -t ecdsa -f target/keys/sshkey -q -N "" +mkdir -p target/overlay/root/.ssh +cp target/keys/sshkey target/overlay/root/.ssh/authorized_keys +chmod -R 600 target/overlay/root/.ssh/ + +echo "[+] Saving the root password" +echo $password > target/keys/rootpassword + +echo "[+] Building the image" +N=`grep -c '^processor' /proc/cpuinfo` +cd target/buildroot +make pcengines_apu2_defconfig +make -j$N diff --git a/buildroot/board/tiesse/tgr/kernel-patches/1000-imx8mm-Add-imx8mm-tgr-device-tree.patch b/buildroot/board/tiesse/tgr/kernel-patches/1000-imx8mm-Add-imx8mm-tgr-device-tree.patch new file mode 100644 index 0000000..c11679c --- /dev/null +++ b/buildroot/board/tiesse/tgr/kernel-patches/1000-imx8mm-Add-imx8mm-tgr-device-tree.patch @@ -0,0 +1,671 @@ +diff --git arch/arm64/boot/dts/freescale/Makefile arch/arm64/boot/dts/freescale/Makefile +index da7ede2f5744..2a0a0f56b9a8 100644 +--- arch/arm64/boot/dts/freescale/Makefile ++++ arch/arm64/boot/dts/freescale/Makefile +@@ -116,7 +116,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ + fsl-imx8mq-evk-inmate.dtb \ + fsl-imx8mq-evk-dp.dtb \ + fsl-imx8mq-evk-edp.dtb +-dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \ ++dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-tgr.dtb \ ++ fsl-imx8mm-evk.dtb \ + fsl-imx8mm-evk-ak4497.dtb \ + fsl-imx8mm-evk-m4.dtb \ + fsl-imx8mm-evk-ak5558.dtb \ +diff --git arch/arm64/boot/dts/freescale/fsl-imx8mm-tgr.dts arch/arm64/boot/dts/freescale/fsl-imx8mm-tgr.dts +new file mode 100755 +index 000000000000..411de1c8c620 +--- /dev/null ++++ arch/arm64/boot/dts/freescale/fsl-imx8mm-tgr.dts +@@ -0,0 +1,629 @@ ++/* ++ * Copyright 2018 NXP ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++ ++#include "fsl-imx8mm.dtsi" ++ ++/ { ++ model = "Tiesse tgr"; ++ compatible = "fsl,imx8mm-tgr", "fsl,imx8mm"; ++ ++ chosen { ++ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; ++ stdout-path = &uart2; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_led>; ++ ++ pwr { ++ label = "pwr"; ++ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ lte { ++ label = "lte"; ++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ ble { ++ label = "ble"; ++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ wifi { ++ label = "wifi"; ++ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ wan { ++ label = "wan"; ++ gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ reg_hub_pwr_on: reg_hub_pwr_on { ++ compatible = "regulator-fixed"; ++ regulator-name = "hub_pwr_on"; ++ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ status = "okay"; ++ }; ++ ++ reg_modem_pwr_on: reg_modem_pwr_on { ++ compatible = "regulator-fixed"; ++ regulator-name = "modem_pwr_on"; ++ gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++ }; ++ }; ++}; ++ ++&memory { ++ reg = <0x0 0x40000000 0 0x40000000>; ++}; ++ ++&linux_cma { ++ size = <0 0x14000000>; ++ alloc-ranges = <0 0x40000000 0 0x30000000>; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ imx8mm-evk { ++ ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ /*PCIE WIFI*/ ++ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x10 /* WIFI_EN_PCIE */ ++ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x10 /* PCIE_RESET */ ++ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x10 /* BLE WAKE */ ++ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x10 /* BLE ENABLE */ ++ ++ /* USB */ ++ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x80 /* OC HUB USB */ ++ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x10 /* USB PWR */ ++ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x80 /* OC USB */ ++ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x10 /* RST HUB */ ++ ++ /* SDIO WIFI */ ++ MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x10 /* SDIO WIFI ENABLE */ ++ ++ /* MODEM */ ++ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x10 /* MODEM ON/OFF */ ++ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x10 /* MODEM RST */ ++ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x10 /* SIM SELECT */ ++ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x10 /* CMD_POWER */ ++ >; ++ }; ++ ++ pinctrl_fec1_gpio: fec1grpgpio { ++ fsl,pins = < ++ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x10 ++ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x80 ++ >; ++ }; ++ ++ pinctrl_fec1: fec1grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 ++ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 ++ MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f ++ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f ++ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f ++ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x92 ++ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 ++ MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 ++ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 ++ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x91 ++ >; ++ }; ++ ++ pinctrl_gpio_led: gpioledgrp { ++ fsl,pins = < ++ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x10 ++ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x10 ++ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x10 ++ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x10 ++ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x10 ++ >; ++ }; ++ ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 ++ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 ++ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 ++ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_pcie0: pcie0grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 ++ >; ++ }; ++ ++ pinctrl_pmic: pmicirq { ++ fsl,pins = < ++ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 ++ MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10 ++ >; ++ }; ++ ++ pinctrl_uart1: uart1grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 ++ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 ++ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 ++ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 ++ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 ++ >; ++ }; ++ ++ pinctrl_uart2: uart2grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 ++ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 ++ >; ++ }; ++ ++ pinctrl_uart3: uart3grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 ++ MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 ++ MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 ++ MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 ++ >; ++ }; ++ ++ pinctrl_usdhc1_gpio: usdhc1grpgpio { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 ++ >; ++ }; ++ ++ pinctrl_usdhc1: usdhc1grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 ++ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 ++ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 ++ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 ++ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 ++ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 ++ >; ++ }; ++ ++ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 ++ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 ++ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 ++ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 ++ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 ++ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 ++ >; ++ }; ++ ++ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 ++ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 ++ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 ++ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 ++ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 ++ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 ++ >; ++ }; ++ ++ pinctrl_usdhc2_gpio: usdhc2grpgpio { ++ fsl,pins = < ++ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 ++ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 ++ >; ++ }; ++ ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 ++ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 ++ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 ++ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 ++ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 ++ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 ++ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 ++ >; ++ }; ++ ++ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 ++ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 ++ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 ++ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 ++ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 ++ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 ++ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 ++ >; ++ }; ++ ++ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { ++ fsl,pins = < ++ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 ++ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 ++ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 ++ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 ++ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 ++ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 ++ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 ++ >; ++ }; ++ ++ pinctrl_usdhc3_gpio: usdhc3grpgpio { ++ fsl,pins = < ++ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x10 ++ >; ++ }; ++ ++ pinctrl_usdhc3: usdhc3grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 ++ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 ++ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 ++ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 ++ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 ++ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 ++ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 ++ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 ++ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 ++ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 ++ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 ++ >; ++ }; ++ ++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { ++ fsl,pins = < ++ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 ++ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 ++ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 ++ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 ++ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 ++ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 ++ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 ++ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 ++ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 ++ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 ++ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 ++ >; ++ }; ++ ++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz { ++ fsl,pins = < ++ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 ++ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 ++ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 ++ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 ++ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 ++ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 ++ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 ++ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 ++ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 ++ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 ++ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 ++ >; ++ }; ++ ++ pinctrl_wdog: wdoggrp { ++ fsl,pins = < ++ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 ++ >; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ pmic: pca9450@25 { ++ reg = <0x25>; ++ compatible = "nxp,pca9450"; ++ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ ++ pinctrl-0 = <&pinctrl_pmic>; ++ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; ++ ++ gpo { ++ nxp,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ ++ }; ++ ++ regulators { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pca9450,pmic-buck2-uses-i2c-dvs; ++ pca9450,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ ++ ++ buck1_reg: regulator@0 { ++ reg = <0>; ++ regulator-compatible = "buck1"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <2187500>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <3125>; ++ }; ++ ++ buck2_reg: regulator@1 { ++ reg = <1>; ++ regulator-compatible = "buck2"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <2187500>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <3125>; ++ }; ++ ++ buck3_reg: regulator@2 { ++ reg = <2>; ++ regulator-compatible = "buck3"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <2187500>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck4_reg: regulator@3 { ++ reg = <3>; ++ regulator-compatible = "buck4"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck5_reg: regulator@4 { ++ reg = <4>; ++ regulator-compatible = "buck5"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ buck6_reg: regulator@5 { ++ reg = <5>; ++ regulator-compatible = "buck6"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo1_reg: regulator@6 { ++ reg = <6>; ++ regulator-compatible = "ldo1"; ++ regulator-min-microvolt = <1600000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo2_reg: regulator@7 { ++ reg = <7>; ++ regulator-compatible = "ldo2"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo3_reg: regulator@8 { ++ reg = <8>; ++ regulator-compatible = "ldo3"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo4_reg: regulator@9 { ++ reg = <9>; ++ regulator-compatible = "ldo4"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo5_reg: regulator@10 { ++ reg = <10>; ++ regulator-compatible = "ldo5"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ }; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++}; ++ ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ usb2422@2c { ++ compatible = "microchip,usb2422"; ++ reg = <0x2c>; ++ reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++ ++&mu { ++ status = "okay"; ++}; ++ ++&fec1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_fec1_gpio>; ++ phy-mode = "rmii"; ++ phy-handle = <ðphy0>; ++ fsl,magic-packet; ++ status = "okay"; ++ ++ phy-reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; ++ phy-reset-duration = <10>; ++ ++ assigned-clocks = <&clk IMX8MM_CLK_ENET_REF_SRC>; ++ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; ++ assigned-clock-rates = <50000000>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ethphy0: ethernet-phy@5 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x5>; ++ clocks = <&clk IMX8MM_CLK_ENET_REF_SRC>; ++ clock-names = "rmii-ref"; ++ }; ++ }; ++}; ++ ++&pcie0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie0>; ++ disable-gpio = <&gpio4 14 GPIO_ACTIVE_LOW>; ++ reset-gpio = <&gpio4 15 GPIO_ACTIVE_LOW>; ++ ext_osc = <0>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++ assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>; ++ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; ++ fsl,uart-has-rtscts; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>; ++ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; ++ fsl,uart-has-rtscts; ++ status = "okay"; ++}; ++ ++&usbotg1 { ++ dr_mode = "host"; ++ vbus-supply = <®_hub_pwr_on>; ++ status = "okay"; ++}; ++ ++&usbotg2 { ++ dr_mode = "host"; ++ vbus-supply = <®_modem_pwr_on>; ++ status = "okay"; ++}; ++ ++&usdhc1 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; ++ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; ++ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; ++ bus-width = <4>; ++ pm-ignore-notify; ++ keep-power-in-suspend; ++ non-removable; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; ++ cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; ++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; ++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&wdog1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_wdog>; ++ fsl,ext-reset-output; ++ status = "okay"; ++}; ++ ++&A53_0 { ++ arm-supply = <&buck2_reg>; ++}; +diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +index e200219ea8bb..333c9fbaf07f 100644 +--- arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi ++++ arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +@@ -65,7 +65,7 @@ + }; + }; + +- memory@40000000 { ++ memory: memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +@@ -76,7 +76,7 @@ + ranges; + + /* global autoconfigured region for contiguous allocations */ +- linux,cma { ++ linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; diff --git a/buildroot/board/tiesse/tgr/kernel-patches/1001-imx8mm-Add-Microchip-USB2422-support.patch b/buildroot/board/tiesse/tgr/kernel-patches/1001-imx8mm-Add-Microchip-USB2422-support.patch new file mode 100644 index 0000000..268807b --- /dev/null +++ b/buildroot/board/tiesse/tgr/kernel-patches/1001-imx8mm-Add-Microchip-USB2422-support.patch @@ -0,0 +1,34 @@ +diff --git drivers/usb/misc/usb251xb.c drivers/usb/misc/usb251xb.c +index 135c91c434bf..a1ca97c07266 100644 +--- drivers/usb/misc/usb251xb.c ++++ drivers/usb/misc/usb251xb.c +@@ -155,6 +155,11 @@ struct usb251xb_data { + char product_str[USB251XB_STRING_BUFSIZE / 2]; /* ASCII string */ + }; + ++static const struct usb251xb_data usb2422_data = { ++ .product_id = 0x2422, ++ .product_str = "USB2422", ++}; ++ + static const struct usb251xb_data usb2512b_data = { + .product_id = 0x2512, + .product_str = "USB2512B", +@@ -492,6 +497,9 @@ static int usb251xb_get_ofdata(struct usb251xb *hub, + + static const struct of_device_id usb251xb_of_match[] = { + { ++ .compatible = "microchip,usb2422", ++ .data = &usb2422_data, ++ }, { + .compatible = "microchip,usb2512b", + .data = &usb2512b_data, + }, { +@@ -567,6 +575,7 @@ static int usb251xb_i2c_probe(struct i2c_client *i2c, + } + + static const struct i2c_device_id usb251xb_id[] = { ++ { "usb2422", 0 }, + { "usb2512b", 0 }, + { "usb2512bi", 0 }, + { "usb2513b", 0 }, diff --git a/buildroot/board/tiesse/tgr/kernel-patches/1002-imx8mm-Add-PCA9450-PMIC-support.patch b/buildroot/board/tiesse/tgr/kernel-patches/1002-imx8mm-Add-PCA9450-PMIC-support.patch new file mode 100644 index 0000000..6e8352f --- /dev/null +++ b/buildroot/board/tiesse/tgr/kernel-patches/1002-imx8mm-Add-PCA9450-PMIC-support.patch @@ -0,0 +1,1516 @@ +diff --git drivers/mfd/Kconfig drivers/mfd/Kconfig +index 997a6172735e..e33bd218301b 100644 +--- drivers/mfd/Kconfig ++++ drivers/mfd/Kconfig +@@ -1818,6 +1818,14 @@ config MFD_BD71837 + if you say yes here you get support for the BD71837 + Power Management chips. + ++config MFD_PCA9450 ++ bool "PCA9450 Power Management chip" ++ depends on I2C=y ++ select MFD_CORE ++ help ++ if you say yes here you get support for the PCA9450 ++ Power Management chips. ++ + menu "Multimedia Capabilities Port drivers" + depends on ARCH_SA1100 + +diff --git drivers/mfd/Makefile drivers/mfd/Makefile +index c6755df735ba..962dcc88d99c 100644 +--- drivers/mfd/Makefile ++++ drivers/mfd/Makefile +@@ -232,3 +232,4 @@ obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o + obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o + obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o + obj-$(CONFIG_MFD_BD71837) += bd71837.o ++obj-$(CONFIG_MFD_PCA9450) += pca9450.o +diff --git drivers/mfd/pca9450.c drivers/mfd/pca9450.c +new file mode 100644 +index 000000000000..85ce6e3eef68 +--- /dev/null ++++ drivers/mfd/pca9450.c +@@ -0,0 +1,304 @@ ++/* ++ * @file pca9450.c -- NXP PCA9450 mfd driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Copyright 2019 NXP. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* @brief pca9450 irq resource */ ++static struct resource pmic_resources[] = { ++ { ++ .start = PCA9450_IRQ, ++ .end = PCA9450_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++/* @brief pca9450 multi function cells */ ++static struct mfd_cell pca9450_mfd_cells[] = { ++ { ++ .name = "pca9450-pmic", ++ .num_resources = ARRAY_SIZE(pmic_resources), ++ .resources = &pmic_resources[0], ++ }, ++}; ++ ++/* @brief pca9450 irqs */ ++static const struct regmap_irq pca9450_irqs[] = { ++ [PCA9450_IRQ] = { ++ .mask = PCA9450_INT_MASK, ++ .reg_offset = 0, ++ }, ++}; ++ ++/* @brief pca9450 irq chip definition */ ++static struct regmap_irq_chip pca9450_irq_chip = { ++ .name = "pca9450", ++ .irqs = pca9450_irqs, ++ .num_irqs = ARRAY_SIZE(pca9450_irqs), ++ .num_regs = 1, ++ .irq_reg_stride = 1, ++ .status_base = PCA9450_INT1, ++ .mask_base = PCA9450_INT1_MSK, ++ .mask_invert = true, ++}; ++ ++/* ++ * @brief pca9450 irq initialize ++ * @param pca9450 pca9450 device to init ++ * @param bdinfo platform init data ++ * @retval 0 probe success ++ * @retval negative error number ++ */ ++static int pca9450_irq_init(struct pca9450 *pca9450, ++ struct pca9450_board *bdinfo) ++{ ++ int irq; ++ int ret = 0; ++ ++ if (!bdinfo) { ++ dev_warn(pca9450->dev, "No interrupt support, no pdata\n"); ++ return -EINVAL; ++ } ++ ++ dev_info(pca9450->dev, "gpio_intr = %d\n", bdinfo->gpio_intr); ++ irq = gpio_to_irq(bdinfo->gpio_intr); ++ ++ pca9450->chip_irq = irq; ++ dev_info(pca9450->dev, "chip_irq=%d\n", pca9450->chip_irq); ++ ret = regmap_add_irq_chip(pca9450->regmap, pca9450->chip_irq, ++ IRQF_ONESHOT | IRQF_TRIGGER_FALLING, bdinfo->irq_base, ++ &pca9450_irq_chip, &pca9450->irq_data); ++ if (ret < 0) ++ dev_warn(pca9450->dev, "Failed to add irq_chip %d\n", ret); ++ ++ return ret; ++} ++ ++/* ++ * @brief pca9450 irq initialize ++ * @param pca9450 pca9450 device to init ++ * @retval 0 probe success ++ * @retval negative error number ++ */ ++static int pca9450_irq_exit(struct pca9450 *pca9450) ++{ ++ if (pca9450->chip_irq > 0) ++ regmap_del_irq_chip(pca9450->chip_irq, pca9450->irq_data); ++ return 0; ++} ++ ++/* ++ * @brief check whether volatile register ++ * @param dev kernel device pointer ++ * @param reg register index ++ */ ++static bool is_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ /* ++ * Caching all regulator registers. ++ */ ++ return true; ++} ++ ++/* @brief regmap configures */ ++static const struct regmap_config pca9450_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .volatile_reg = is_volatile_reg, ++ .max_register = PCA9450_MAX_REGISTER - 1, ++ .cache_type = REGCACHE_RBTREE, ++}; ++ ++#ifdef CONFIG_OF ++static const struct of_device_id pca9450_of_match[] = { ++ { .compatible = "nxp,pca9450", .data = (void *)0}, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, pca9450_of_match); ++ ++/* ++ * @brief parse device tree data of pca9450 ++ * @param client client object provided by system ++ * @param chip_id return chip id back to caller ++ * @return board initialize data ++ */ ++static struct pca9450_board *pca9450_parse_dt(struct i2c_client *client, ++ int *chip_id) ++{ ++ struct device_node *np = client->dev.of_node; ++ struct pca9450_board *board_info; ++ unsigned int prop; ++ const struct of_device_id *match; ++ int r = 0; ++ ++ match = of_match_device(pca9450_of_match, &client->dev); ++ if (!match) { ++ dev_err(&client->dev, "Failed to find matching dt id\n"); ++ return NULL; ++ } ++ ++ chip_id = (int *)match->data; ++ ++ board_info = devm_kzalloc(&client->dev, sizeof(*board_info), ++ GFP_KERNEL); ++ if (!board_info) ++ return NULL; ++ ++ board_info->gpio_intr = of_get_named_gpio(np, "gpio_intr", 0); ++ if (!gpio_is_valid(board_info->gpio_intr)) { ++ dev_err(&client->dev, "no pmic intr pin available\n"); ++ goto err_intr; ++ } ++ ++ r = of_property_read_u32(np, "irq_base", &prop); ++ if (!r) ++ board_info->irq_base = prop; ++ else ++ board_info->irq_base = -1; ++ ++ return board_info; ++ ++err_intr: ++ devm_kfree(&client->dev, board_info); ++ return NULL; ++} ++#endif ++ ++/* ++ * @brief probe pca9450 device ++ * @param i2c client object provided by system ++ * @param id chip id ++ * @retval 0 probe success ++ * @retval negative error number ++ */ ++static int pca9450_i2c_probe(struct i2c_client *i2c, ++ const struct i2c_device_id *id) ++{ ++ struct pca9450 *pca9450; ++ struct pca9450_board *pmic_plat_data; ++ struct pca9450_board *of_pmic_plat_data = NULL; ++ int chip_id = id->driver_data; ++ int ret = 0; ++ ++ pmic_plat_data = dev_get_platdata(&i2c->dev); ++ ++ if (!pmic_plat_data && i2c->dev.of_node) { ++ pmic_plat_data = pca9450_parse_dt(i2c, &chip_id); ++ of_pmic_plat_data = pmic_plat_data; ++ } ++ ++ if (!pmic_plat_data) ++ return -EINVAL; ++ ++ pca9450 = kzalloc(sizeof(struct pca9450), GFP_KERNEL); ++ if (pca9450 == NULL) ++ return -ENOMEM; ++ ++ pca9450->of_plat_data = of_pmic_plat_data; ++ i2c_set_clientdata(i2c, pca9450); ++ pca9450->dev = &i2c->dev; ++ pca9450->i2c_client = i2c; ++ pca9450->id = chip_id; ++ mutex_init(&pca9450->io_mutex); ++ ++ pca9450->regmap = devm_regmap_init_i2c(i2c, &pca9450_regmap_config); ++ if (IS_ERR(pca9450->regmap)) { ++ ret = PTR_ERR(pca9450->regmap); ++ dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret); ++ return ret; ++ } ++ ++ ret = pca9450_reg_read(pca9450, PCA9450_REG_DEV_ID); ++ if (ret < 0) { ++ dev_err(pca9450->dev, "%s(): Read PCA9450_REG_DEVICE failed!\n", ++ __func__); ++ goto err; ++ } ++ dev_info(pca9450->dev, "Device ID=0x%X\n", ret); ++ ++ pca9450_irq_init(pca9450, of_pmic_plat_data); ++ ++ ret = mfd_add_devices(pca9450->dev, -1, ++ pca9450_mfd_cells, ARRAY_SIZE(pca9450_mfd_cells), ++ NULL, 0, ++ regmap_irq_get_domain(pca9450->irq_data)); ++ if (ret < 0) ++ goto err; ++ ++ return ret; ++ ++err: ++ mfd_remove_devices(pca9450->dev); ++ kfree(pca9450); ++ return ret; ++} ++ ++/* ++ * @brief remove pca9450 device ++ * @param i2c client object provided by system ++ * @return 0 ++ */ ++static int pca9450_i2c_remove(struct i2c_client *i2c) ++{ ++ struct pca9450 *pca9450 = i2c_get_clientdata(i2c); ++ ++ pca9450_irq_exit(pca9450); ++ mfd_remove_devices(pca9450->dev); ++ kfree(pca9450); ++ ++ return 0; ++} ++ ++static const struct i2c_device_id pca9450_i2c_id[] = { ++ { "pca9450", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, pca9450_i2c_id); ++ ++static struct i2c_driver pca9450_i2c_driver = { ++ .driver = { ++ .name = "pca9450", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(pca9450_of_match), ++ }, ++ .probe = pca9450_i2c_probe, ++ .remove = pca9450_i2c_remove, ++ .id_table = pca9450_i2c_id, ++}; ++ ++static int __init pca9450_i2c_init(void) ++{ ++ return i2c_add_driver(&pca9450_i2c_driver); ++} ++/* init early so consumer devices can complete system boot */ ++subsys_initcall(pca9450_i2c_init); ++ ++static void __exit pca9450_i2c_exit(void) ++{ ++ i2c_del_driver(&pca9450_i2c_driver); ++} ++module_exit(pca9450_i2c_exit); ++ ++MODULE_AUTHOR("John Lee "); ++MODULE_DESCRIPTION("PCA9450 chip multi-function driver"); ++MODULE_LICENSE("GPL"); +diff --git drivers/regulator/Kconfig drivers/regulator/Kconfig +index 5361947ea726..e5b3c9ffb982 100644 +--- drivers/regulator/Kconfig ++++ drivers/regulator/Kconfig +@@ -983,5 +983,11 @@ config REGULATOR_BD71837 + help + This driver supports BD71837 voltage regulator chips. + ++config REGULATOR_PCA9450 ++ tristate "NXP PCA9450 Power Regulator" ++ depends on MFD_PCA9450 ++ help ++ This driver supports PCA9450 voltage regulator chips. ++ + endif + +diff --git drivers/regulator/Makefile drivers/regulator/Makefile +index 1bddbefbc8e7..0072ad5666f8 100644 +--- drivers/regulator/Makefile ++++ drivers/regulator/Makefile +@@ -126,6 +126,7 @@ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o + obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o + obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o + obj-$(CONFIG_REGULATOR_BD71837) += bd71837-regulator.o ++obj-$(CONFIG_REGULATOR_PCA9450) += pca9450-regulator.o + + + ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG +diff --git drivers/regulator/pca9450-regulator.c drivers/regulator/pca9450-regulator.c +new file mode 100644 +index 000000000000..6b9ce8f34e0e +--- /dev/null ++++ drivers/regulator/pca9450-regulator.c +@@ -0,0 +1,783 @@ ++/* ++ * @file pca9450-regulator.c ROHM PCA9450MWV regulator driver ++ * ++ * Copyright 2019 NXP. ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PCA9450_DVS_BUCK_NUM 3 /* Buck 1/2/3 support DVS */ ++#define PCA9450_DVS0_1 2 ++#define PCA9450_DVS0 1 ++ ++struct pca9450_buck_dvs { ++ u32 voltage[PCA9450_DVS0_1]; ++}; ++ ++/* @brief pca9450 regulator type */ ++struct pca9450_pmic { ++ struct regulator_desc descs[PCA9450_REGULATOR_CNT]; ++ struct pca9450 *mfd; ++ struct device *dev; ++ struct regulator_dev *rdev[PCA9450_REGULATOR_CNT]; ++ struct pca9450_buck_dvs buck_dvs[PCA9450_DVS_BUCK_NUM]; ++ int reg_index; ++}; ++ ++/* ++ * BUCK1/2/3 ++ * BUCK1RAM[1:0] BUCK1 DVS ramp rate setting ++ * 00: 25mV/1usec ++ * 01: 25mV/2usec ++ * 10: 25mV/4usec ++ * 11: 25mV/8usec ++ */ ++static int pca9450_buck123_set_ramp_delay(struct regulator_dev *rdev, ++ int ramp_delay) ++{ ++ struct pca9450_pmic *pmic = rdev_get_drvdata(rdev); ++ struct pca9450 *mfd = pmic->mfd; ++ int id = rdev->desc->id; ++ unsigned int ramp_value = BUCK1_RAMP_3P125MV; ++ unsigned int buckctrl[3] = {PCA9450_BUCK1CTRL, PCA9450_BUCK2CTRL, ++ PCA9450_BUCK3CTRL}; ++ ++ dev_dbg(pmic->dev, "Buck[%d] Set Ramp = %d\n", id + 1, ramp_delay); ++ switch (ramp_delay) { ++ case 1 ... 3125: ++ ramp_value = BUCK1_RAMP_3P125MV; ++ break; ++ case 3126 ... 6250: ++ ramp_value = BUCK1_RAMP_6P25MV; ++ break; ++ case 6251 ... 12500: ++ ramp_value = BUCK1_RAMP_12P5MV; ++ break; ++ case 12501 ... 25000: ++ ramp_value = BUCK1_RAMP_25MV; ++ break; ++ default: ++ ramp_value = BUCK1_RAMP_25MV; ++ } ++ ++ return regmap_update_bits(mfd->regmap, buckctrl[id], ++ BUCK1_RAMP_MASK, ramp_value << 6); ++} ++ ++static struct regulator_ops pca9450_ldo_regulator_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_linear_range, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++}; ++ ++static struct regulator_ops pca9450_fixed_regulator_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_linear, ++}; ++ ++static struct regulator_ops pca9450_buck_regulator_ops = { ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_linear_range, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++}; ++ ++static struct regulator_ops pca9450_buck123_regulator_ops = { ++ .is_enabled = regulator_is_enabled_regmap, ++ .list_voltage = regulator_list_voltage_linear_range, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++ .set_ramp_delay = pca9450_buck123_set_ramp_delay, ++}; ++ ++/* ++ * BUCK1/2/3 ++ * 0.60 to 2.1875V (12.5mV step) ++ */ ++static const struct regulator_linear_range pca9450_buck123_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 12500), ++}; ++ ++/* ++ * BUCK4/5/6 ++ * 0.6V to 3.4V (25mV step) ++ */ ++static const struct regulator_linear_range pca9450_buck456_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(600000, 0x00, 0x70, 25000), ++ REGULATOR_LINEAR_RANGE(3400000, 0x71, 0x7F, 0), ++}; ++ ++/* ++ * LDO1 ++ * 1.6 to 3.3V () ++ */ ++static const struct regulator_linear_range pca9450_ldo1_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(1600000, 0x00, 0x03, 100000), ++ REGULATOR_LINEAR_RANGE(3000000, 0x04, 0x07, 100000), ++}; ++ ++/* ++ * LDO2 ++ * 0.8 to 1.15V (50mV step) ++ */ ++static const struct regulator_linear_range pca9450_ldo2_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(800000, 0x00, 0x07, 50000), ++}; ++ ++/* ++ * LDO3 ++ * 0.8 to 3.3V (100mV step) ++ */ ++static const struct regulator_linear_range pca9450_ldo34_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(800000, 0x00, 0x19, 100000), ++ REGULATOR_LINEAR_RANGE(3300000, 0x1A, 0x1F, 0), ++}; ++ ++/* ++ * LDO5 ++ * 1.8 to 3.3V (100mV step) ++ */ ++static const struct regulator_linear_range pca9450_ldo5_voltage_ranges[] = { ++ REGULATOR_LINEAR_RANGE(1800000, 0x00, 0x0F, 100000), ++}; ++ ++static const struct regulator_desc pca9450_regulators[] = { ++ { ++ .name = "BUCK1", ++ .id = PCA9450_BUCK1, ++ .ops = &pca9450_buck123_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_BUCK1_VOLTAGE_NUM, ++ .linear_ranges = pca9450_buck123_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_buck123_voltage_ranges), ++ .vsel_reg = PCA9450_BUCK1OUT_DVS0, ++ .vsel_mask = BUCK1OUT_DVS0_MASK, ++ .enable_reg = PCA9450_BUCK1CTRL, ++ .enable_mask = BUCK1_ENMODE_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "BUCK2", ++ .id = PCA9450_BUCK2, ++ .ops = &pca9450_buck123_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_BUCK2_VOLTAGE_NUM, ++ .linear_ranges = pca9450_buck123_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_buck123_voltage_ranges), ++ .vsel_reg = PCA9450_BUCK2OUT_DVS0, ++ .vsel_mask = BUCK2OUT_DVS0_MASK, ++ .enable_reg = PCA9450_BUCK2CTRL, ++ .enable_mask = BUCK2_ENMODE_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "BUCK3", ++ .id = PCA9450_BUCK3, ++ .ops = &pca9450_buck123_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_BUCK3_VOLTAGE_NUM, ++ .linear_ranges = pca9450_buck123_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_buck123_voltage_ranges), ++ .vsel_reg = PCA9450_BUCK3OUT_DVS0, ++ .vsel_mask = BUCK3OUT_DVS0_MASK, ++ .enable_reg = PCA9450_BUCK3CTRL, ++ .enable_mask = BUCK3_ENMODE_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "BUCK4", ++ .id = PCA9450_BUCK4, ++ .ops = &pca9450_buck_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_BUCK4_VOLTAGE_NUM, ++ .linear_ranges = pca9450_buck456_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_buck456_voltage_ranges), ++ .vsel_reg = PCA9450_BUCK4OUT, ++ .vsel_mask = BUCK4OUT_MASK, ++ .enable_reg = PCA9450_BUCK4CTRL, ++ .enable_mask = BUCK4_ENMODE_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "BUCK5", ++ .id = PCA9450_BUCK5, ++ .ops = &pca9450_buck_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_BUCK5_VOLTAGE_NUM, ++ .linear_ranges = pca9450_buck456_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_buck456_voltage_ranges), ++ .vsel_reg = PCA9450_BUCK5OUT, ++ .vsel_mask = BUCK5OUT_MASK, ++ .enable_reg = PCA9450_BUCK5CTRL, ++ .enable_mask = BUCK5_ENMODE_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "BUCK6", ++ .id = PCA9450_BUCK6, ++ .ops = &pca9450_buck_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_BUCK6_VOLTAGE_NUM, ++ .linear_ranges = pca9450_buck456_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_buck456_voltage_ranges), ++ .vsel_reg = PCA9450_BUCK6OUT, ++ .vsel_mask = BUCK6OUT_MASK, ++ .enable_reg = PCA9450_BUCK6CTRL, ++ .enable_mask = BUCK6_ENMODE_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "LDO1", ++ .id = PCA9450_LDO1, ++ .ops = &pca9450_ldo_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_LDO1_VOLTAGE_NUM, ++ .linear_ranges = pca9450_ldo1_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_ldo1_voltage_ranges), ++ .vsel_reg = PCA9450_LDO1CTRL, ++ .vsel_mask = LDO1OUT_MASK, ++ .enable_reg = PCA9450_LDO1CTRL, ++ .enable_mask = LDO1_EN_MASK, ++ .owner = THIS_MODULE, ++ }, ++ /* ++ * LDO2 0.9V ++ * Fixed voltage ++ */ ++ { ++ .name = "LDO2", ++ .id = PCA9450_LDO2, ++ .ops = &pca9450_fixed_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_LDO2_VOLTAGE_NUM, ++ .min_uV = 900000, ++ .enable_reg = PCA9450_LDO2CTRL, ++ .enable_mask = LDO2_EN_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "LDO3", ++ .id = PCA9450_LDO3, ++ .ops = &pca9450_ldo_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_LDO3_VOLTAGE_NUM, ++ .linear_ranges = pca9450_ldo34_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_ldo34_voltage_ranges), ++ .vsel_reg = PCA9450_LDO3CTRL, ++ .vsel_mask = LDO3OUT_MASK, ++ .enable_reg = PCA9450_LDO3CTRL, ++ .enable_mask = LDO3_EN_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "LDO4", ++ .id = PCA9450_LDO4, ++ .ops = &pca9450_ldo_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_LDO4_VOLTAGE_NUM, ++ .linear_ranges = pca9450_ldo34_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_ldo34_voltage_ranges), ++ .vsel_reg = PCA9450_LDO4CTRL, ++ .vsel_mask = LDO4OUT_MASK, ++ .enable_reg = PCA9450_LDO4CTRL, ++ .enable_mask = LDO4_EN_MASK, ++ .owner = THIS_MODULE, ++ }, ++ { ++ .name = "LDO5", ++ .id = PCA9450_LDO5, ++ .ops = &pca9450_ldo_regulator_ops, ++ .type = REGULATOR_VOLTAGE, ++ .n_voltages = PCA9450_LDO5_VOLTAGE_NUM, ++ .linear_ranges = pca9450_ldo5_voltage_ranges, ++ .n_linear_ranges = ARRAY_SIZE(pca9450_ldo5_voltage_ranges), ++ .vsel_reg = PCA9450_LDO5CTRL_H, ++ .vsel_mask = LDO5HOUT_MASK, ++ .enable_reg = PCA9450_LDO5CTRL_H, ++ .enable_mask = LDO5H_EN_MASK, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++#ifdef CONFIG_OF ++ ++static struct of_regulator_match pca9450_matches[] = { ++ { .name = "buck1", }, ++ { .name = "buck2", }, ++ { .name = "buck3", }, ++ { .name = "buck4", }, ++ { .name = "buck5", }, ++ { .name = "buck6", }, ++ { .name = "ldo1", }, ++ { .name = "ldo2", }, ++ { .name = "ldo3", }, ++ { .name = "ldo4", }, ++ { .name = "ldo5", }, ++}; ++ ++/* ++ * @brief parse pca9450 regulator device tree ++ * @param pdev platform device of pca9450 regulator ++ * @param pca9450_reg_matches return regualtor matches ++ * @retval 0 parse success ++ * @retval NULL parse fail ++ */ ++static int pca9450_parse_dt_reg_data( ++ struct platform_device *pdev, ++ struct of_regulator_match **reg_matches) ++{ ++ struct device_node *np, *regulators; ++ struct of_regulator_match *matches; ++ int ret, count; ++ ++ np = of_node_get(pdev->dev.parent->of_node); ++ regulators = of_find_node_by_name(np, "regulators"); ++ if (!regulators) { ++ dev_err(&pdev->dev, "regulator node not found\n"); ++ return -EINVAL; ++ } ++ ++ count = ARRAY_SIZE(pca9450_matches); ++ matches = pca9450_matches; ++ ++ ret = of_regulator_match(&pdev->dev, regulators, matches, count); ++ of_node_put(regulators); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", ++ ret); ++ return ret; ++ } ++ ++ *reg_matches = matches; ++ ++ return 0; ++} ++#else ++static inline int pca9450_parse_dt_reg_data( ++ struct platform_device *pdev, ++ struct of_regulator_match **reg_matches) ++{ ++ *reg_matches = NULL; ++ return 0; ++} ++#endif ++ ++/* @brief directly set raw value to chip register, format: 'register value' */ ++static ssize_t pca9450_sysfs_set_registers(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, ++ size_t count) ++{ ++ struct pca9450_pmic *pmic = dev_get_drvdata(dev); ++ ssize_t ret = 0; ++ unsigned int reg; ++ unsigned int val; ++ ++ ret = sscanf(buf, "%x %x", ®, &val); ++ if (ret < 1) { ++ pmic->reg_index = -1; ++ dev_err(pmic->dev, "registers set: \n"); ++ return count; ++ } ++ ++ if (ret == 1 && reg < PCA9450_MAX_REGISTER) { ++ pmic->reg_index = reg; ++ dev_info(pmic->dev, "registers set: reg=0x%x\n", reg); ++ return count; ++ } ++ ++ if (reg >= PCA9450_MAX_REGISTER) { ++ dev_err(pmic->dev, "reg=%d out of Max=%d\n", reg, ++ PCA9450_MAX_REGISTER); ++ return -EINVAL; ++ } ++ dev_info(pmic->dev, "registers set: reg=0x%x, val=0x%x\n", reg, val); ++ ret = pca9450_reg_write(pmic->mfd, reg, val); ++ if (ret < 0) ++ return ret; ++ return count; ++} ++ ++/* @brief print value of chip register, format: 'register=value' */ ++static ssize_t pca9450_sysfs_print_reg(struct pca9450_pmic *pmic, ++ u8 reg, ++ char *buf) ++{ ++ int ret = pca9450_reg_read(pmic->mfd, reg); ++ ++ if (ret < 0) ++ return sprintf(buf, "%#.2x=error %d\n", reg, ret); ++ return sprintf(buf, "[0x%.2X] = %.2X\n", reg, ret); ++} ++ ++/* ++ * @brief show all raw values of chip register, format per line: ++ * 'register=value' ++ */ ++static ssize_t pca9450_sysfs_show_registers(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct pca9450_pmic *pmic = dev_get_drvdata(dev); ++ ssize_t ret = 0; ++ int i; ++ ++ dev_info(pmic->dev, "register: index[0x%x]\n", pmic->reg_index); ++ if (pmic->reg_index >= 0) ++ ret += pca9450_sysfs_print_reg(pmic, pmic->reg_index, ++ buf + ret); ++ else ++ for (i = 0; i < PCA9450_MAX_REGISTER; i++) ++ ret += pca9450_sysfs_print_reg(pmic, i, buf + ret); ++ ++ return ret; ++} ++ ++static DEVICE_ATTR(registers, 0644, ++ pca9450_sysfs_show_registers, pca9450_sysfs_set_registers); ++ ++/* @brief device sysfs attribute table, about o */ ++static struct attribute *clk_attributes[] = { ++ &dev_attr_registers.attr, ++ NULL ++}; ++ ++static const struct attribute_group clk_attr_group = { ++ .attrs = clk_attributes, ++}; ++ ++/*----------------------------------------------------------------------*/ ++#ifdef CONFIG_OF ++/* ++ * @brief buck1/2 dvs enable/voltage from device tree ++ * @param pdev platform device pointer ++ * @param buck_dvs pointer ++ * @return void ++ */ ++static void of_pca9450_buck_dvs(struct platform_device *pdev, ++ struct pca9450_buck_dvs *buck_dvs) ++{ ++ struct device_node *pmic_np; ++ ++ pmic_np = of_node_get(pdev->dev.parent->of_node); ++ if (!pmic_np) { ++ dev_err(&pdev->dev, "could not find pmic sub-node\n"); ++ return; ++ } ++ if (of_get_property(pmic_np, "pca9450,pmic-buck1-uses-i2c-dvs", NULL)) { ++ if (of_property_read_u32_array(pmic_np, ++ "pca9450,pmic-buck1-dvs-voltage", ++ &buck_dvs[0].voltage[0], ++ PCA9450_DVS0_1)) { ++ dev_err(&pdev->dev, "buck1 voltages not specified\n"); ++ } ++ } ++ ++ if (of_get_property(pmic_np, "pca9450,pmic-buck2-uses-i2c-dvs", NULL)) { ++ if (of_property_read_u32_array(pmic_np, ++ "pca9450,pmic-buck2-dvs-voltage", ++ &buck_dvs[1].voltage[0], ++ PCA9450_DVS0_1)) { ++ dev_err(&pdev->dev, "buck2 voltages not specified\n"); ++ } ++ } ++ ++ if (of_get_property(pmic_np, "pca9450,pmic-buck3-uses-i2c-dvs", NULL)) { ++ if (of_property_read_u32_array(pmic_np, ++ "pca9450,pmic-buck3-dvs-voltage", ++ &buck_dvs[2].voltage[0], ++ PCA9450_DVS0)) { ++ dev_err(&pdev->dev, "buck3 voltages not specified\n"); ++ } ++ } ++} ++#else ++static void of_pca9450_buck_dvs(struct platform_device *pdev, ++ struct pca9450_buck_dvs *buck_dvs) ++{ ++ buck_dvs[0].voltage[0] = BUCK1OUT_DVS0_DEFAULT; ++ buck_dvs[0].voltage[1] = BUCK1OUT_DVS1_DEFAULT; ++ buck_dvs[1].voltage[0] = BUCK2OUT_DVS0_DEFAULT; ++ buck_dvs[1].voltage[1] = BUCK2OUT_DVS1_DEFAULT; ++ buck_dvs[2].voltage[0] = BUCK3OUT_DVS0_DEFAULT; ++ buck_dvs[2].voltage[1] = 0; /* Not supported */ ++} ++#endif ++ ++static int pca9450_buck123_dvs_init(struct pca9450_pmic *pmic) ++{ ++ struct pca9450 *pca9450 = pmic->mfd; ++ struct pca9450_buck_dvs *buck_dvs = &pmic->buck_dvs[0]; ++ int i, ret, val, selector = 0; ++ u8 reg_dvs0, reg_dvs1; ++ u8 reg_dvs0_msk, reg_dvs1_msk; ++ ++ for (i = 0; i < PCA9450_DVS_BUCK_NUM; i++, buck_dvs++) { ++ switch (i) { ++ case 0: ++ default: ++ reg_dvs0 = PCA9450_BUCK1OUT_DVS0; ++ reg_dvs0_msk = BUCK1OUT_DVS0_MASK; ++ reg_dvs1 = PCA9450_BUCK1OUT_DVS1; ++ reg_dvs1_msk = BUCK1OUT_DVS1_MASK; ++ break; ++ case 1: ++ reg_dvs0 = PCA9450_BUCK2OUT_DVS0; ++ reg_dvs0_msk = BUCK2OUT_DVS0_MASK; ++ reg_dvs1 = PCA9450_BUCK2OUT_DVS1; ++ reg_dvs1_msk = BUCK2OUT_DVS1_MASK; ++ break; ++ case 2: ++ reg_dvs0 = PCA9450_BUCK3OUT_DVS0; ++ reg_dvs0_msk = BUCK3OUT_DVS0_MASK; ++ reg_dvs1 = PCA9450_BUCK3OUT_DVS1; ++ reg_dvs1_msk = BUCK3OUT_DVS1_MASK; ++ break; ++ } ++ ++ dev_dbg(pmic->dev, "Buck%d: DVS0-DVS1[%d - %d].\n", i+1, ++ buck_dvs->voltage[0], buck_dvs->voltage[1]); ++ if (reg_dvs0 > 0) { ++ selector = regulator_map_voltage_iterate(pmic->rdev[i], ++ buck_dvs->voltage[0], ++ buck_dvs->voltage[0]); ++ if (selector < 0) { ++ dev_dbg(pmic->dev, ++ "not found selector for DVS0 [%d]\n", ++ buck_dvs->voltage[0]); ++ } else { ++ val = (selector & reg_dvs0_msk); ++ ret = pca9450_reg_write(pca9450, reg_dvs0, val); ++ if (ret < 0) ++ return ret; ++ } ++ } ++ if (reg_dvs1 > 0) { ++ selector = regulator_map_voltage_iterate(pmic->rdev[i], ++ buck_dvs->voltage[1], ++ buck_dvs->voltage[1]); ++ if (selector < 0) { ++ dev_dbg(pmic->dev, ++ "not found selector for DVS1 [%d]\n", ++ buck_dvs->voltage[1]); ++ } else { ++ val = (selector & reg_dvs1_msk); ++ ret = pca9450_reg_write(pca9450, reg_dvs1, val); ++ if (ret < 0) ++ return ret; ++ } ++ } ++ } ++ return 0; ++} ++ ++/* ++ * @brief pca9450 pmic interrupt ++ * @param irq system irq ++ * @param pwrsys pca9450 power device of system ++ * @retval IRQ_HANDLED success ++ * @retval IRQ_NONE error ++ */ ++static irqreturn_t pca9450_pmic_interrupt(int irq, void *pwrsys) ++{ ++ struct device *dev = pwrsys; ++ struct pca9450 *mfd = dev_get_drvdata(dev->parent); ++ int reg; ++ ++ reg = pca9450_reg_read(mfd, PCA9450_INT1); ++ if (reg < 0) ++ return IRQ_NONE; ++ ++ if (reg & IRQ_PWRON) ++ dev_dbg(dev, "IRQ_PWRON\n"); ++ if (reg & IRQ_WDOGB) ++ dev_dbg(dev, "IRQ_WDOGB\n"); ++ if (reg & IRQ_VR_FLT1) ++ dev_dbg(dev, "IRQ_VR_FLT1\n"); ++ if (reg & IRQ_VR_FLT2) ++ dev_dbg(dev, "IRQ_VR_FLT2\n"); ++ if (reg & IRQ_LOWVSYS) ++ dev_dbg(dev, "IRQ_LOWVSYS\n"); ++ if (reg & IRQ_THERM_105) ++ dev_dbg(dev, "IRQ_THERM_105\n"); ++ if (reg & IRQ_THERM_125) ++ dev_dbg(dev, "IRQ_THERM_125\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * @brief probe pca9450 regulator device ++ * @param pdev pca9450 regulator platform device ++ * @retval 0 success ++ * @retval negative fail ++ */ ++static int pca9450_probe(struct platform_device *pdev) ++{ ++ struct pca9450_pmic *pmic; ++ struct pca9450_board *pdata; ++ struct regulator_config config = {}; ++ struct pca9450 *pca9450 = dev_get_drvdata(pdev->dev.parent); ++ struct of_regulator_match *matches = NULL; ++ int i = 0, err, irq = 0, ret = 0; ++ ++ pmic = kzalloc(sizeof(*pmic), GFP_KERNEL); ++ if (!pmic) ++ return -ENOMEM; ++ ++ memcpy(pmic->descs, pca9450_regulators, sizeof(pmic->descs)); ++ ++ pmic->dev = &pdev->dev; ++ pmic->mfd = pca9450; ++ platform_set_drvdata(pdev, pmic); ++ pdata = dev_get_platdata(pca9450->dev); ++ ++ if (!pdata && pca9450->dev->of_node) { ++ pca9450_parse_dt_reg_data(pdev, &matches); ++ if (matches == NULL) { ++ dev_err(&pdev->dev, "Platform data not found\n"); ++ return -EINVAL; ++ } ++ } ++ ++ /* Get buck dvs parameters */ ++ of_pca9450_buck_dvs(pdev, &pmic->buck_dvs[0]); ++ ++ for (i = 0; i < PCA9450_REGULATOR_CNT; i++) { ++ struct regulator_init_data *init_data; ++ struct regulator_desc *desc; ++ struct regulator_dev *rdev; ++ ++ desc = &pmic->descs[i]; ++ desc->name = pca9450_matches[i].name; ++ ++ if (pdata) ++ init_data = pdata->init_data[i]; ++ else ++ init_data = pca9450_matches[i].init_data; ++ ++ config.dev = pmic->dev; ++ config.init_data = init_data; ++ config.driver_data = pmic; ++ config.regmap = pca9450->regmap; ++ if (matches) ++ config.of_node = matches[i].of_node; ++ dev_dbg(config.dev, "regulator register name '%s'\n", ++ desc->name); ++ ++ rdev = regulator_register(desc, &config); ++ if (IS_ERR(rdev)) { ++ dev_err(pca9450->dev, ++ "failed to register %s regulator\n", ++ desc->name); ++ err = PTR_ERR(rdev); ++ goto err; ++ } ++ pmic->rdev[i] = rdev; ++ } ++ ++ /* Init sysfs registers */ ++ pmic->reg_index = -1; ++ ++ err = sysfs_create_group(&pdev->dev.kobj, &clk_attr_group); ++ if (err != 0) { ++ dev_err(&pdev->dev, "Failed to create sysfs: %d\n", err); ++ goto err; ++ } ++ ++ /* Init Buck1/2/3 dvs */ ++ err = pca9450_buck123_dvs_init(pmic); ++ if (err != 0) { ++ dev_err(&pdev->dev, "Failed to buck123 dvs: %d\n", err); ++ goto err; ++ } ++ ++ /* Add Interrupt */ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) { ++ dev_warn(&pdev->dev, "platform irq error # %d\n", irq); ++ return -ENXIO; ++ } ++ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, ++ pca9450_pmic_interrupt, ++ IRQF_TRIGGER_LOW | IRQF_EARLY_RESUME, ++ dev_name(&pdev->dev), &pdev->dev); ++ if (ret < 0) ++ dev_err(&pdev->dev, "IRQ %d is not free.\n", irq); ++ ++ /* Un-mask IRQ Interrupt */ ++ ret = pca9450_reg_write(pca9450, PCA9450_INT1_MSK, 0); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Write 'PCA9450_REG_MIRQ': failed!\n"); ++ ret = -EIO; ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ while (--i >= 0) ++ regulator_unregister(pmic->rdev[i]); ++ ++ kfree(pmic); ++ return err; ++} ++ ++/* ++ * @brief remove pca9450 regulator device ++ * @param pdev pca9450 regulator platform device ++ * @return 0 ++ */ ++static int __exit pca9450_remove(struct platform_device *pdev) ++{ ++ struct pca9450_pmic *pmic = platform_get_drvdata(pdev); ++ int i; ++ ++ sysfs_remove_group(&pdev->dev.kobj, &clk_attr_group); ++ ++ for (i = 0; i < PCA9450_REGULATOR_CNT; i++) ++ regulator_unregister(pmic->rdev[i]); ++ ++ kfree(pmic); ++ return 0; ++} ++ ++static struct platform_driver pca9450_driver = { ++ .driver = { ++ .name = "pca9450-pmic", ++ .owner = THIS_MODULE, ++ }, ++ .probe = pca9450_probe, ++ .remove = pca9450_remove, ++}; ++module_platform_driver(pca9450_driver); ++ ++MODULE_DESCRIPTION("PCA9450 voltage regulator driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:pca9450-pmic"); +diff --git include/linux/mfd/pca9450.h include/linux/mfd/pca9450.h +new file mode 100644 +index 000000000000..b689c2dd3b94 +--- /dev/null ++++ include/linux/mfd/pca9450.h +@@ -0,0 +1,355 @@ ++/** ++ * @file pca9450.h NXP PCA9450 header file ++ * ++ * Copyright 2019 NXP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_MFD_PCA9450_H ++#define __LINUX_MFD_PCA9450_H ++ ++#include ++ ++enum { ++ PCA9450_BUCK1 = 0, ++ PCA9450_BUCK2, ++ PCA9450_BUCK3, ++ PCA9450_BUCK4, ++ PCA9450_BUCK5, ++ PCA9450_BUCK6, ++ PCA9450_LDO1, ++ PCA9450_LDO2, ++ PCA9450_LDO3, ++ PCA9450_LDO4, ++ PCA9450_LDO5, ++ PCA9450_REGULATOR_CNT, ++}; ++ ++#define PCA9450_SUPPLY_STATE_ENABLED 0x1 ++ ++#define PCA9450_BUCK1_VOLTAGE_NUM 0x80 ++#define PCA9450_BUCK2_VOLTAGE_NUM 0x80 ++#define PCA9450_BUCK3_VOLTAGE_NUM 0x80 ++#define PCA9450_BUCK4_VOLTAGE_NUM 0x80 ++ ++#define PCA9450_BUCK5_VOLTAGE_NUM 0x80 ++#define PCA9450_BUCK6_VOLTAGE_NUM 0x80 ++ ++#define PCA9450_LDO1_VOLTAGE_NUM 0x08 ++#define PCA9450_LDO2_VOLTAGE_NUM 0x08 ++#define PCA9450_LDO3_VOLTAGE_NUM 0x20 ++#define PCA9450_LDO4_VOLTAGE_NUM 0x20 ++#define PCA9450_LDO5_VOLTAGE_NUM 0x10 ++ ++enum { ++ PCA9450_REG_DEV_ID = 0x00, ++ PCA9450_INT1 = 0x01, ++ PCA9450_INT1_MSK = 0x02, ++ PCA9450_STATUS1 = 0x03, ++ PCA9450_STATUS2 = 0x04, ++ PCA9450_PWRON_STAT = 0x05, ++ PCA9450_SW_RST = 0x06, ++ PCA9450_PWR_CTRL = 0x07, ++ PCA9450_RESET_CTRL = 0x08, ++ PCA9450_CONFIG1 = 0x09, ++ PCA9450_CONFIG2 = 0x0A, ++ PCA9450_BUCK123_DVS = 0x0C, ++ PCA9450_BUCK1OUT_LIMIT = 0x0D, ++ PCA9450_BUCK2OUT_LIMIT = 0x0E, ++ PCA9450_BUCK3OUT_LIMIT = 0x0F, ++ PCA9450_BUCK1CTRL = 0x10, ++ PCA9450_BUCK1OUT_DVS0 = 0x11, ++ PCA9450_BUCK1OUT_DVS1 = 0x12, ++ PCA9450_BUCK2CTRL = 0x13, ++ PCA9450_BUCK2OUT_DVS0 = 0x14, ++ PCA9450_BUCK2OUT_DVS1 = 0x15, ++ PCA9450_BUCK3CTRL = 0x16, ++ PCA9450_BUCK3OUT_DVS0 = 0x17, ++ PCA9450_BUCK3OUT_DVS1 = 0x18, ++ PCA9450_BUCK4CTRL = 0x19, ++ PCA9450_BUCK4OUT = 0x1A, ++ PCA9450_BUCK5CTRL = 0x1B, ++ PCA9450_BUCK5OUT = 0x1C, ++ PCA9450_BUCK6CTRL = 0x1D, ++ PCA9450_BUCK6OUT = 0x1E, ++ PCA9450_LDO_AD_CTRL = 0x20, ++ PCA9450_LDO1CTRL = 0x21, ++ PCA9450_LDO2CTRL = 0x22, ++ PCA9450_LDO3CTRL = 0x23, ++ PCA9450_LDO4CTRL = 0x24, ++ PCA9450_LDO5CTRL_L = 0x25, ++ PCA9450_LDO5CTRL_H = 0x26, ++ PCA9450_LOADSW_CTRL = 0x2A, ++ PCA9450_VRFLT1_STS = 0x2B, ++ PCA9450_VRFLT2_STS = 0x2C, ++ PCA9450_VRFLT1_MASK = 0x2D, ++ PCA9450_VRFLT2_MASK = 0x2E, ++ PCA9450_MAX_REGISTER = 0x2F, ++}; ++ ++/* PCA9450 BUCK ENMODE bits */ ++#define BUCK_ENMODE_OFF 0x00 ++#define BUCK_ENMODE_ONREQ 0x01 ++#define BUCK_ENMODE_ONREQ_STBYREQ 0x02 ++#define BUCK_ENMODE_ON 0x03 ++ ++/* PCA9450_REG_BUCK1_CTRL bits */ ++#define BUCK1_RAMP_MASK 0xC0 ++#define BUCK1_RAMP_25MV 0x0 ++#define BUCK1_RAMP_12P5MV 0x1 ++#define BUCK1_RAMP_6P25MV 0x2 ++#define BUCK1_RAMP_3P125MV 0x3 ++#define BUCK1_DVS_CTRL 0x10 ++#define BUCK1_AD 0x08 ++#define BUCK1_FPWM 0x04 ++#define BUCK1_ENMODE_MASK 0x03 ++ ++/* PCA9450_REG_BUCK2_CTRL bits */ ++#define BUCK2_RAMP_MASK 0xC0 ++#define BUCK2_RAMP_25MV 0x0 ++#define BUCK2_RAMP_12P5MV 0x1 ++#define BUCK2_RAMP_6P25MV 0x2 ++#define BUCK2_RAMP_3P125MV 0x3 ++#define BUCK2_DVS_CTRL 0x10 ++#define BUCK2_AD 0x08 ++#define BUCK2_FPWM 0x04 ++#define BUCK2_ENMODE_MASK 0x03 ++ ++/* PCA9450_REG_BUCK3_CTRL bits */ ++#define BUCK3_RAMP_MASK 0xC0 ++#define BUCK3_RAMP_25MV 0x0 ++#define BUCK3_RAMP_12P5MV 0x1 ++#define BUCK3_RAMP_6P25MV 0x2 ++#define BUCK3_RAMP_3P125MV 0x3 ++#define BUCK3_DVS_CTRL 0x10 ++#define BUCK3_AD 0x08 ++#define BUCK3_FPWM 0x04 ++#define BUCK3_ENMODE_MASK 0x03 ++ ++/* PCA9450_REG_BUCK4_CTRL bits */ ++#define BUCK4_AD 0x08 ++#define BUCK4_FPWM 0x04 ++#define BUCK4_ENMODE_MASK 0x03 ++ ++/* PCA9450_REG_BUCK5_CTRL bits */ ++#define BUCK5_AD 0x08 ++#define BUCK5_FPWM 0x04 ++#define BUCK5_ENMODE_MASK 0x03 ++ ++/* PCA9450_REG_BUCK6_CTRL bits */ ++#define BUCK6_AD 0x08 ++#define BUCK6_FPWM 0x04 ++#define BUCK6_ENMODE_MASK 0x03 ++ ++/* PCA9450_BUCK1OUT_DVS0 bits */ ++#define BUCK1OUT_DVS0_MASK 0x7F ++#define BUCK1OUT_DVS0_DEFAULT 0x14 ++ ++/* PCA9450_BUCK1OUT_DVS1 bits */ ++#define BUCK1OUT_DVS1_MASK 0x7F ++#define BUCK1OUT_DVS1_DEFAULT 0x14 ++ ++/* PCA9450_BUCK2OUT_DVS0 bits */ ++#define BUCK2OUT_DVS0_MASK 0x7F ++#define BUCK2OUT_DVS0_DEFAULT 0x14 ++ ++/* PCA9450_BUCK2OUT_DVS1 bits */ ++#define BUCK2OUT_DVS1_MASK 0x7F ++#define BUCK2OUT_DVS1_DEFAULT 0x14 ++ ++/* PCA9450_BUCK3OUT_DVS0 bits */ ++#define BUCK3OUT_DVS0_MASK 0x7F ++#define BUCK3OUT_DVS0_DEFAULT 0x14 ++ ++/* PCA9450_BUCK3OUT_DVS1 bits */ ++#define BUCK3OUT_DVS1_MASK 0x7F ++#define BUCK3OUT_DVS1_DEFAULT 0x14 ++ ++/* PCA9450_REG_BUCK4OUT bits */ ++#define BUCK4OUT_MASK 0x7F ++#define BUCK4OUT_DEFAULT 0x6C ++ ++/* PCA9450_REG_BUCK5OUT bits */ ++#define BUCK5OUT_MASK 0x7F ++#define BUCK5OUT_DEFAULT 0x30 ++ ++/* PCA9450_REG_BUCK6OUT bits */ ++#define BUCK6OUT_MASK 0x7F ++#define BUCK6OUT_DEFAULT 0x14 ++ ++/* PCA9450_REG_IRQ bits */ ++#define IRQ_PWRON 0x80 ++#define IRQ_WDOGB 0x40 ++#define IRQ_VR_FLT1 0x10 ++#define IRQ_VR_FLT2 0x08 ++#define IRQ_LOWVSYS 0x04 ++#define IRQ_THERM_105 0x02 ++#define IRQ_THERM_125 0x01 ++ ++/* PCA9450 interrupt masks */ ++enum { ++ PCA9450_INT_MASK = 0xDF, ++}; ++/* PCA9450 interrupt irqs */ ++enum { ++ PCA9450_IRQ = 0x0, ++}; ++ ++/* PCA9450_REG_LDO1_VOLT bits */ ++#define LDO1_EN_MASK 0xC0 ++#define LDO1OUT_MASK 0x07 ++ ++/* PCA9450_REG_LDO2_VOLT bits */ ++#define LDO2_EN_MASK 0xC0 ++#define LDO2OUT_MASK 0x07 ++ ++/* PCA9450_REG_LDO3_VOLT bits */ ++#define LDO3_EN_MASK 0xC0 ++#define LDO3OUT_MASK 0x0F ++ ++/* PCA9450_REG_LDO4_VOLT bits */ ++#define LDO4_EN_MASK 0xC0 ++#define LDO4OUT_MASK 0x0F ++ ++/* PCA9450_REG_LDO5_VOLT bits */ ++#define LDO5L_EN_MASK 0xC0 ++#define LDO5LOUT_MASK 0x0F ++ ++#define LDO5H_EN_MASK 0xC0 ++#define LDO5HOUT_MASK 0x0F ++ ++/* ++ * @brief Board platform data may be used to initialize regulators. ++ */ ++ ++struct pca9450_board { ++ struct regulator_init_data *init_data[PCA9450_REGULATOR_CNT]; ++ int gpio_intr; ++ int irq_base; ++}; ++ ++/* ++ * @brief pca9450 sub-driver chip access routines ++ */ ++ ++struct pca9450 { ++ struct device *dev; ++ struct i2c_client *i2c_client; ++ struct regmap *regmap; ++ struct mutex io_mutex; ++ unsigned int id; ++ ++ /* IRQ Handling */ ++ int chip_irq; ++ struct regmap_irq_chip_data *irq_data; ++ ++ /* Client devices */ ++ struct pca9450_pmic *pmic; ++ struct pca9450_power *power; ++ ++ struct pca9450_board *of_plat_data; ++}; ++ ++static inline int pca9450_chip_id(struct pca9450 *pca9450) ++{ ++ return pca9450->id; ++} ++ ++/* ++ * @brief pca9450_reg_read ++ * read single register's value of pca9450 ++ * @param pca9450 device to read ++ * @param reg register address ++ * @return register value if success ++ * error number if fail ++ */ ++static inline int pca9450_reg_read(struct pca9450 *pca9450, u8 reg) ++{ ++ int r, val; ++ ++ r = regmap_read(pca9450->regmap, reg, &val); ++ if (r < 0) ++ return r; ++ ++ return val; ++} ++ ++/* ++ * @brief pca9450_reg_write ++ * write single register of pca9450 ++ * @param pca9450 device to write ++ * @param reg register address ++ * @param val value to write ++ * @retval 0 if success ++ * @retval negative error number if fail ++ */ ++ ++static inline int pca9450_reg_write(struct pca9450 *pca9450, u8 reg, ++ unsigned int val) ++{ ++ return regmap_write(pca9450->regmap, reg, val); ++} ++ ++/* ++ * @brief pca9450_set_bits ++ * set bits in one register of pca9450 ++ * @param pca9450 device to read ++ * @param reg register address ++ * @param mask mask bits ++ * @retval 0 if success ++ * @retval negative error number if fail ++ */ ++static inline int pca9450_set_bits(struct pca9450 *pca9450, u8 reg, u8 mask) ++{ ++ return regmap_update_bits(pca9450->regmap, reg, mask, mask); ++} ++ ++/* ++ * @brief pca9450_clear_bits ++ * clear bits in one register of pca9450 ++ * @param pca9450 device to read ++ * @param reg register address ++ * @param mask mask bits ++ * @retval 0 if success ++ * @retval negative error number if fail ++ */ ++ ++static inline int pca9450_clear_bits(struct pca9450 *pca9450, u8 reg, ++ u8 mask) ++{ ++ return regmap_update_bits(pca9450->regmap, reg, mask, 0); ++} ++ ++/* ++ * @brief pca9450_update_bits ++ * update bits in one register of pca9450 ++ * @param pca9450 device to read ++ * @param reg register address ++ * @param mask mask bits ++ * @param val value to update ++ * @retval 0 if success ++ * @retval negative error number if fail ++ */ ++ ++static inline int pca9450_update_bits(struct pca9450 *pca9450, u8 reg, ++ u8 mask, u8 val) ++{ ++ return regmap_update_bits(pca9450->regmap, reg, mask, val); ++} ++ ++/* ++ * @brief pca9450 platform data type ++ */ ++struct pca9450_gpo_plat_data { ++ u32 drv; ++ int gpio_base; ++}; ++ ++u8 ext_pca9450_reg_read8(u8 reg); ++int ext_pca9450_reg_write8(int reg, u8 val); ++#endif /* __LINUX_MFD_PCA9450_H */ diff --git a/buildroot/board/tiesse/tgr/linux.config b/buildroot/board/tiesse/tgr/linux.config new file mode 100644 index 0000000..1f2bf4c --- /dev/null +++ b/buildroot/board/tiesse/tgr/linux.config @@ -0,0 +1,871 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_BPF_SYSCALL=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_ALPINE=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_IPROC=y +CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_LG1K=y +CONFIG_ARCH_HISI=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MESON=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SEATTLE=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_R8A7795=y +CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_STRATIX10=y +CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_SPRD=y +CONFIG_ARCH_THUNDER=y +CONFIG_ARCH_THUNDER2=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_XGENE=y +CONFIG_ARCH_ZX=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ARCH_FSL_IMX8QM=y +CONFIG_ARCH_FSL_IMX8QP=y +CONFIG_ARCH_FSL_IMX8QXP=y +CONFIG_ARCH_FSL_IMX8MQ=y +CONFIG_ARCH_FSL_IMX8MM=y +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCI_IOV=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCI_AARDVARK=y +CONFIG_PCIE_RCAR=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCIE_ROCKCHIP=m +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NUMA=y +CONFIG_PREEMPT=y +CONFIG_KSM=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_XEN=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_COMPAT=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_BIG_LITTLE_CPUFREQ=y +CONFIG_ARM_IMX8_CPUFREQ=y +CONFIG_ARM_IMX8MQ_CPUFREQ=y +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_BPF_JIT=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +# CONFIG_BT_HS is not set +# CONFIG_BT_LE is not set +CONFIG_BT_LEDS=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211_DEBUG=y +CONFIG_MAC80211=y +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_DEBUG_MENU=y +CONFIG_MAC80211_NOINLINE=y +CONFIG_MAC80211_VERBOSE_DEBUG=y +CONFIG_MAC80211_MLME_DEBUG=y +CONFIG_MAC80211_STA_DEBUG=y +CONFIG_MAC80211_HT_DEBUG=y +CONFIG_MAC80211_OCB_DEBUG=y +CONFIG_MAC80211_IBSS_DEBUG=y +CONFIG_MAC80211_PS_DEBUG=y +CONFIG_MAC80211_MPL_DEBUG=y +CONFIG_MAC80211_MPATH_DEBUG=y +CONFIG_MAC80211_MHWMP_DEBUG=y +CONFIG_MAC80211_MESH_SYNC_DEBUG=y +CONFIG_MAC80211_MESH_CSA_DEBUG=y +CONFIG_MAC80211_MESH_PS_DEBUG=y +CONFIG_MAC80211_TDLS_DEBUG=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_ARM_CCI400_PMU=y +CONFIG_ARM_CCI5xx_PMU=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SLRAM=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_FSL_FLEXSPI=y +CONFIG_MTD_UBI=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=y +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=m +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_SRAM=y +CONFIG_EEPROM_AT25=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_MVEBU=y +CONFIG_AHCI_XGENE=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_SATA_RCAR=y +CONFIG_PATA_PLATFORM=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_VXLAN=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_AMD_XGBE=y +CONFIG_NET_XGENE=y +CONFIG_MACB=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVNETA=y +CONFIG_MVPP2=y +CONFIG_SKY2=y +CONFIG_QCOM_EMAC=m +CONFIG_RAVB=y +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_STMMAC_ETH=m +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_AT803X_PHY=y +CONFIG_MARVELL_PHY=m +CONFIG_MESON_GXL_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_NXP_TJA110X_PHY=y +CONFIG_REALTEK_PHY=m +CONFIG_ROCKCHIP_PHY=y +CONFIG_PPP=y +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_HOSTAP=y +CONFIG_RTL_CARDS=m +# CONFIG_WLAN_VENDOR_TI is not set +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX_SC_PWRKEY=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_HISI_POWERKEY=y +CONFIG_INPUT_MPL3115=y +CONFIG_INPUT_ISL29023=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MESON=y +CONFIG_SERIAL_MESON_CONSOLE=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=11 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_MVEBU_UART=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_BCM2835=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_MESON=y +CONFIG_I2C_MV64XXX=y +CONFIG_I2C_PXA=y +CONFIG_I2C_QUP=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y +CONFIG_I2C_SH_MOBILE=y +CONFIG_I2C_TEGRA=y +CONFIG_I2C_UNIPHIER_F=y +CONFIG_I2C_RCAR=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_XEN_I2C_BACKEND=y +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_MESON_SPICC=m +CONFIG_SPI_MESON_SPIFC=m +CONFIG_SPI_ORION=y +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_QUP=y +CONFIG_SPI_S3C64XX=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_MSM8994=y +CONFIG_PINCTRL_MSM8996=y +CONFIG_PINCTRL_QDF2XXX=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_RCAR=y +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_XGENE_SB=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_MAX77620=y +CONFIG_POWER_AVS=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_INA2XX=m +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX8M_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_ROCKCHIP_THERMAL=m +CONFIG_EXYNOS_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_S3C2410_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX8_WDT=y +CONFIG_MESON_GXBB_WATCHDOG=m +CONFIG_MESON_WATCHDOG=m +CONFIG_RENESAS_WDT=y +CONFIG_UNIPHIER_WATCHDOG=y +CONFIG_BCM2835_WDT=y +CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_CROS_EC_SPI=y +CONFIG_MFD_EXYNOS_LPASS=m +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_HI655X_PMIC=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_RK808=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_BD71837=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_HI655X=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_BD71837=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_GMSL_MAX9286=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m +CONFIG_VIDEO_SAMSUNG_S5P_MFC=m +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m +CONFIG_VIDEO_RENESAS_FCP=m +CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX_DCSS_CORE=y +CONFIG_IMX_LCDIF_CORE=y +CONFIG_DRM=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_EXYNOS=m +CONFIG_DRM_EXYNOS5433_DECON=y +CONFIG_DRM_EXYNOS7_DECON=y +CONFIG_DRM_EXYNOS_DSI=y +# CONFIG_DRM_EXYNOS_DP is not set +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_DRM_EXYNOS_MIC=y +CONFIG_DRM_ROCKCHIP=m +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_DRM_RCAR_DU=m +CONFIG_DRM_RCAR_LVDS=y +CONFIG_DRM_RCAR_VSP=y +CONFIG_DRM_MSM=m +CONFIG_DRM_TEGRA=m +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_NWL_DSI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_HDP=y +CONFIG_IMX_HDP_CEC=y +CONFIG_DRM_VC4=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y +CONFIG_DRM_MESON=m +CONFIG_FB_IMX64=y +CONFIG_FB_IMX64_DEBUG=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_MXC_DISP_FRAMEWORK=y +CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP855X=m +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_SOC_FSL_ACM=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_AK4458=y +CONFIG_SND_SOC_IMX_AK5558=y +CONFIG_SND_SOC_IMX_AK4497=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_WM8524=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_MICFIL=y +CONFIG_SND_SOC_IMX_RPMSG=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_AMIX=y +CONFIG_SND_SOC_IMX_CDNHDMI=y +CONFIG_SND_SOC_IMX_DSP=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_RCAR=y +CONFIG_SND_SOC_AK4613=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_TEGRA=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_RENESAS_USBHS=m +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_HUB_USB251XB=y +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_GPIO_VBUS=y +CONFIG_USB_QCOM_8X16_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_FSL_UTP=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_GADGET_UAC1=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_MESON_GX=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SPI=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SUNXI=y +CONFIG_MMC_BCM2835=y +CONFIG_MMC_SDHCI_XENON=y +# CONFIG_MXC_GPU_VIV is not set +CONFIG_MXC_MLB150=y +CONFIG_MXC_SIM=y +CONFIG_MXC_EMVSIM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_S3C=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_TEGRA=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_RTC_DRV_XGENE=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=m +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_K3_DMA=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_PL330_DMA=y +CONFIG_TEGRA20_APB_DMA=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_RCAR_DMAC=y +CONFIG_UIO=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_ION=y +CONFIG_ION_SYSTEM_HEAP=y +CONFIG_ION_CMA_HEAP=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_CLK_QORIQ=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_IPQ_GCC_8074=y +CONFIG_MSM_GCC_8916=y +CONFIG_MSM_GCC_8994=y +CONFIG_MSM_MMCC_8996=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_CLKSRC_IMX_SYS_CNT=y +CONFIG_ARM_MHU=y +CONFIG_PLATFORM_MHU=y +CONFIG_BCM2835_MBOX=y +CONFIG_HI6220_MBOX=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_ARCH_MXC_ARM64=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_ARCH_TEGRA_132_SOC=y +CONFIG_ARCH_TEGRA_210_SOC=y +CONFIG_ARCH_TEGRA_186_SOC=y +CONFIG_EXTCON_PTN5150=y +CONFIG_IIO=y +CONFIG_EXYNOS_ADC=y +CONFIG_IMX8QXP_ADC=y +CONFIG_ROCKCHIP_SARADC=m +CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_FSL_FTM=y +CONFIG_PWM_IMX=y +CONFIG_PWM_MESON=m +CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_SAMSUNG=y +CONFIG_PWM_TEGRA=m +CONFIG_PHY_XGENE=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_HI6220_USB=y +CONFIG_PHY_RCAR_GEN3_USB2=y +CONFIG_PHY_ROCKCHIP_EMMC=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_PCIE=m +CONFIG_PHY_TEGRA_XUSB=y +CONFIG_QCOM_L2_PMU=y +CONFIG_QCOM_L3_PMU=y +CONFIG_IMX8_DDR_PERF=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_SCU_OCOTP=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_ACPI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y +CONFIG_SECURITY=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CHACHA20POLY1305=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA512_ARM64=m +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_CRC32_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_AES_ARM64_BS=m + diff --git a/buildroot/board/tiesse/tgr/wireless-patches/0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch b/buildroot/board/tiesse/tgr/wireless-patches/0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch new file mode 100755 index 0000000..725ac76 --- /dev/null +++ b/buildroot/board/tiesse/tgr/wireless-patches/0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch @@ -0,0 +1,91 @@ +From 16573cbb9c82218f93741a9bc873242c012ac061 Mon Sep 17 00:00:00 2001 +From: Hangtian Zhu +Date: Thu, 14 Jun 2018 11:10:05 +0800 +Subject: [PATCH 22/23] MLK-18491-02 qcacld-2.0: fix the overflow of bounce + buffer + +Patch a41baa51cbc5("MLK-18491 qcacld-2.0: avoid overflow of bounce buffer") +is not reasonable to fix overflow of bounce buffer issue. + +The patch is released by Qualcomm to fix the issue. +(Case Number:03515221) + +Signed-off-by: Hangtian Zhu +--- + CORE/SERVICES/HTC/htc.c | 2 +- + CORE/SERVICES/HTC/htc_send.c | 28 ++++++++++++++-------------- + 2 files changed, 15 insertions(+), 15 deletions(-) + +diff --git a/CORE/SERVICES/HTC/htc.c b/CORE/SERVICES/HTC/htc.c +index 1e2450d..09936a0 100644 +--- a/CORE/SERVICES/HTC/htc.c ++++ b/CORE/SERVICES/HTC/htc.c +@@ -657,7 +657,7 @@ static void ResetEndpointStates(HTC_TARGET *target) + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBufferHoldQueue); + pEndpoint->target = target; + //pEndpoint->TxCreditFlowEnabled = (A_BOOL)htc_credit_flow; +- pEndpoint->TxCreditFlowEnabled = (A_BOOL)0; ++ pEndpoint->TxCreditFlowEnabled = (A_BOOL)1; + adf_os_atomic_init(&pEndpoint->TxProcessCount); + } + } +diff --git a/CORE/SERVICES/HTC/htc_send.c b/CORE/SERVICES/HTC/htc_send.c +index 1a3dd28..19d8065 100644 +--- a/CORE/SERVICES/HTC/htc_send.c ++++ b/CORE/SERVICES/HTC/htc_send.c +@@ -105,12 +105,12 @@ void HTCGetControlEndpointTxHostCredits(HTC_HANDLE HTCHandle, int *credits) + + static INLINE void RestoreTxPacket(HTC_TARGET *target, HTC_PACKET *pPacket) + { ++ adf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket); + if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) { +- adf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket); + adf_nbuf_unmap(target->osdev, netbuf, ADF_OS_DMA_TO_DEVICE); +- adf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR)); + pPacket->PktInfo.AsTx.Flags &= ~HTC_TX_PACKET_FLAG_FIXUP_NETBUF; + } ++ adf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR)); + + } + +@@ -641,12 +641,11 @@ static A_STATUS HTCIssuePackets(HTC_TARGET *target, + * that is already mapped, or a non-data netbuf that needs to be + * mapped. + */ +- if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) { +- adf_nbuf_map( +- target->osdev, +- GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), +- ADF_OS_DMA_TO_DEVICE); +- } ++ pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF; ++ adf_nbuf_map( ++ target->osdev, ++ GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), ++ ADF_OS_DMA_TO_DEVICE); + } + LOCK_HTC_TX(target); + /* store in look up queue to match completions */ +@@ -1261,12 +1260,13 @@ A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue) + * mapped. This only applies to non-data frames, since data frames + * were already mapped as they entered into the driver. + */ +- adf_nbuf_map( +- target->osdev, +- GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), +- ADF_OS_DMA_TO_DEVICE); +- +- pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF; ++ if(!IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) { ++ pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF; ++ adf_nbuf_map( ++ target->osdev, ++ GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket), ++ ADF_OS_DMA_TO_DEVICE); ++ } + } HTC_PACKET_QUEUE_ITERATE_END; + + HTCTrySend(target,pEndpoint,pPktQueue); +-- +1.9.1 + diff --git a/firmware/qca6174/bdwlan30.bin b/firmware/qca6174/bdwlan30.bin new file mode 100644 index 0000000..117cacd Binary files /dev/null and b/firmware/qca6174/bdwlan30.bin differ diff --git a/firmware/qca6174/otp30.bin b/firmware/qca6174/otp30.bin new file mode 100644 index 0000000..84a40e3 Binary files /dev/null and b/firmware/qca6174/otp30.bin differ diff --git a/firmware/qca6174/qwlan30.bin b/firmware/qca6174/qwlan30.bin new file mode 100644 index 0000000..818e081 Binary files /dev/null and b/firmware/qca6174/qwlan30.bin differ diff --git a/firmware/qca6174/utf30.bin b/firmware/qca6174/utf30.bin new file mode 100644 index 0000000..cfbfb2d Binary files /dev/null and b/firmware/qca6174/utf30.bin differ diff --git a/firmware/wlan/qca6174/qcom_cfg.ini b/firmware/wlan/qca6174/qcom_cfg.ini new file mode 100644 index 0000000..d297e8d --- /dev/null +++ b/firmware/wlan/qca6174/qcom_cfg.ini @@ -0,0 +1,403 @@ +# This file allows user to override the factory + +# defaults for the WLAN Driver + +#Host module debug +vosTraceEnableHDD=0 +vosTraceEnableWDA=0 +vosTraceEnableWDI=0 +vosTraceEnableSME=0 +vosTraceEnablePE=0 +vosTraceEnableWMA=0 +vosTraceEnableVOSS=0 +gEnableLogp=1 + +#Prioritize user(hostapd, iw,) specified country +gCountryCodePriority=1 + +#Host logging +gMulticastHostFwMsgs=0 + +#packetlog +gEnablePacketLog=0 + +#Enable firmware uart print +gEnablefwprint=0 + +#Enable firmware log +gEnablefwlog=0 + +# Disable FW log function by default +gFwDebugLogType=0 +gFwDebugModuleLoglevel=0,0 + +# Generic + +# Phy Mode (auto, b, g, n, etc) +# Valid values are 0-9, with 0 = Auto, 4 = 11n, 9 = 11ac +# 1 = 11abg, 2 = 11b, 3 = 11g, 5 = 11g only, 6 = 11n only +# 7 = 11b only 8 = 11ac only. +gDot11Mode=0 + +# VHT Tx/Rx MCS values +# Valid values are 0,1,2. If commented out, the default value is 0. +# 0=MCS0-7, 1=MCS0-8, 2=MCS0-9 +gVhtRxMCS=2 +gVhtTxMCS=2 + +# VHT Tx/Rx MCS values for 2x2 +# Valid values are 0,1,2. If commented out, the default value is 0. +# 0=MCS0-7, 1=MCS0-8, 2=MCS0-9 +gEnable2x2=1 +gVhtRxMCS2x2=2 +gVhtTxMCS2x2=2 + +gVhtChannelWidth=2 + +#Short Guard Interval Enable/disable +gShortGI20Mhz=1 +gShortGI40Mhz=1 + +#Channel Bonding +gChannelBondingMode5GHz=1 + +# 1=enable STBC; 0=disable STBC +gEnableRXSTBC=1 + +# 1=enable tx STBC; 0=disable +gEnableTXSTBC=1 + +# 1=enable rx LDPC; 0=disable +gEnableRXLDPC=1 + +#If set to 0, MCC is not allowed. +gEnableMCCMode=1 + +# Enable or Disable MCC Adaptive Scheduler at the FW +# 1=Enable (default), 0=Disable +gEnableMCCAdaptiveScheduler=1 + +# Enable BMPS or not +gEnableBmps=1 + +# Enable IMPS or not +gEnableImps=1 + +# Enable/Disable Idle Scan +gEnableIdleScan=0 + +#Data Inactivity Timeout when in powersave (in ms) +gDataInactivityTimeout=200 + +# Increase sleep duration (seconds) during IMPS +# 0 implies no periodic wake up from IMPS. Periodic wakeup is +# unnecessary if Idle Scan is disabled. +gImpsModSleepTime=0 + +# Enable suspend or not +# 1: Enable standby, 2: Enable Deep sleep, 3: Enable Mcast/Bcast Filter +gEnableSuspend=3 + + +#Enable/Disable UAPSD for SoftAP +gEnableApUapsd=1 + +# UAPSD service interval for VO,VI, BE, BK traffic +InfraUapsdVoSrvIntv=0 +InfraUapsdViSrvIntv=0 +InfraUapsdBeSrvIntv=0 +InfraUapsdBkSrvIntv=0 + +# Flag to allow STA send AddTspec even when ACM is Off +gAddTSWhenACMIsOff=1 + +# Beacon filtering frequency (unit in beacon intervals) +gNthBeaconFilter=50 + +# Enable WAPI or not +WAPIIsEnabled=0 +# Flags to filter Mcast abd Bcast RX packets. +# Value 0: No filtering, 1: Filter all Multicast. +# 2: Filter all Broadcast. 3: Filter all Mcast abd Bcast +McastBcastFilter=3 + +#Flag to enable HostARPOffload feature or not +hostArpOffload=0 + +#Flag to enable TCPChkSumOffld feature or not +gEnableTCPChkSumOffld=0 + +#Flag to enable HostNSOffload feature or not +hostNSOffload=1 +gActiveModeOffload=1 + +#Flag to enable IPChkSumOffld feature or not +gEnableIPChecksumOffload=0 + +# 802.11n Protection flag +gEnableApProt=1 + +#Enable OBSS protection +gEnableApOBSSProt=1 + +# Fixed Rate +gFixedRate=0 + +# RTS threshold +RTSThreshold=192000 + +# Intra-BSS forward +gDisableIntraBssFwd=0 + +# WMM Enable/Disable +WmmIsEnabled=0 + +# 802.11d support +g11dSupportEnabled=1 + +# 802.11h support +g11hSupportEnabled=1 + +# ESE Support and fast transition +EseEnabled=0 +ImplicitQosIsEnabled=0 +gNeighborScanTimerPeriod=200 + +gNeighborLookupThreshold=76 +gNeighborReassocThreshold=81 + +gNeighborScanChannelMinTime=20 +gNeighborScanChannelMaxTime=30 +gMaxNeighborReqTries=3 + +gEnableFastRoamInConcurrency=1 + +# CSR Roaming Enable(1) Disable(0) +gRoamingTime=0 + +# Roaming Preference +gRoamPrefer5GHz=1 +gSelect5GHzMargin=20 + +# Legacy (non-ESE, non-802.11r) Fast Roaming Support +# To enable, set FastRoamEnabled=1 +# To disable, set FastRoamEnabled=0 +FastRoamEnabled=1 + +#Check if the AP to which we are roaming is better than current AP in terms of RSSI. +#Checking is disabled if set to Zero.Otherwise it will use this value as to how better +#the RSSI of the new/roamable AP should be for roaming +RoamRssiDiff=3 + +# If the RSSI of any available candidate is better than currently associated +# AP by at least gImmediateRoamRssiDiff, then being to roam immediately (without +# registering for reassoc threshold). +# NOTE: Value of 0 means that we would register for reassoc threshold. +gImmediateRoamRssiDiff=10 + +# To enable, set gRoamIntraBand=1 (Roaming within band) +# To disable, set gRoamIntraBand=0 (Roaming across band) +gRoamIntraBand=0 + +# SAP Country code +# Default Country Code is 2 bytes, 3rd byte is optional indoor or out door. +# Example +# US Indoor, USI +# Korea Outdoor, KRO +# Japan without optional byte, JP +# France without optional byte, FR +#gAPCntryCode=US + +#Auto Shutdown Value in seconds. A value of 0 means Auto shutoff is disabled +gAPAutoShutOff=0 + +# SAP auto channel selection configuration +# 0 = disable auto channel selection +# 1 = enable auto channel selection, channel provided by supplicant will be ignored +gApAutoChannelSelection=0 + +#Preferred band (both or 2.4 only or 5 only) +BandCapability=0 + +#Beacon Early Termination (1 = enable the BET feature, 0 = disable) +enableBeaconEarlyTermination=0 +beaconEarlyTerminationWakeInterval=3 + +#SOFTAP Channel Range selection +gAPChannelSelectStartChannel=1 +gAPChannelSelectEndChannel=11 + +#SOFTAP Channel Range selection Operating band +# 0:2.4GHZ 1: LOW-5GHZ 2:MID-5GHZ 3:HIGH-5GHZ 4: 4.9HZ BAND +gAPChannelSelectOperatingBand=0 + +# Listen Energy Detect Mode Configuration +# Valid values 0-128 +# 128 means disable Energy Detect feature +# 0-9 are threshold code and 7 is recommended value from system if feature is to be enabled. +# 10-128 are reserved. +# The EDET threshold mapping is as follows in 3dB step: +# 0 = -60 dBm +# 1 = -63 dBm +# 2 = -66 dBm +# ... +# 7 = -81 dBm +# 8 = -84 dBm +# 9 = -87 dBm + +# Note: Any of these settings are valid. Setting 0 would yield the highest power saving (in a noisy environment) at the cost of more range. The range impact is approximately #calculated as: + +# +# Range Loss (dB) = EDET threshold level (dBm) + 97 dBm. +# +gEnablePhyAgcListenMode=128 + +#Enable Keep alive with non-zero period value +gStaKeepAlivePeriod = 30 +#Say gGoKeepAlivePeriod(5 seconds) and gGoLinkMonitorPeriod(10 seconds). +#For every 10 seconds DUT send Qos Null frame(i.e., Keep Alive frame if link is idle for last 10 seconds.) +#For both active and power save clients. + +#Power save clients: DUT set TIM bit from 10th second onwards and till client honors TIM bit. +#If doesn't honor for 5 seconds then DUT remove client. + +#Active clients: DUT send Qos Null frame for 10th seconds onwards if it is not success still we try on +#11th second if not tries on 12th and so on till 15th second. Hence before disconnection DUT will send 5 NULL frames. +#Hence in any case DUT will detect client got removed in (10+5) seconds. i.e., (gGoKeepAlivePeriod + gGoLinkMonitorPeriod).. + +#gGoLinkMonitorPeriod/ gApLinkMonitorPeriod is period where link is idle and it is period +#where we send NULL frame. +gApLinkMonitorPeriod = 10 +gGoLinkMonitorPeriod = 10 + +#gGoKeepAlivePeriod/gApKeepAlivePeriod is time to spend to check whether frame are succeed to send or not. +#Hence total effective detection time is gGoLinkMonitorPeriod+ gGoKeepAlivePeriod/gApLinkMonitorPeriod+ gApKeepAlivePeriod. +gGoKeepAlivePeriod = 20 +gApKeepAlivePeriod = 20 + +#If set will start with active scan after driver load, otherwise will start with +#passive scan to find out the domain +gEnableBypass11d=1 + +#If set to 0, will not scan DFS channels +gEnableDFSChnlScan=1 + +# Enable Automatic Tx Power control +gEnableAutomaticTxPowerControl=1 + +# 0 for OLPC 1 for CLPC and SCPC +gEnableCloseLoop=1 + +# Scan Timing Parameters +gPassiveMaxChannelTime=110 +gPassiveMinChannelTime=60 +gActiveMaxChannelTime=40 +gActiveMinChannelTime=20 + +# Enable Active mode offload +gEnableActiveModeOffload=1 + +#Enable Scan Results Aging based on timer +#Timer value is in seconds +#If Set to 0 it will not enable the feature +gScanAgingTime=0 + +#Enable Power saving mechanism Based on Android Framework +#If set to 0 Driver internally control the Power saving mechanism +#If set to 1 Android Framwrok control the Power saving mechanism +isAndroidPsEn=0 + +#disable LDPC in STA mode if the AP is TXBF capable +gDisableLDPCWithTxbfAP=0 + +#Enable thermal mitigation +gThermalMitigationEnable=1 +gThermalTempMinLevel1=90 +gThermalTempMaxLevel0=110 +gThermalTempMaxLevel1=115 +gThrottlePeriod=100 + +#List of Country codes for which 11ac needs to be disabled +#Each country code must be delimited by comma(,) +gListOfNon11acCountryCode=RU,UA,ZA + +#Maxium Channel time in msec +gMaxMediumTime = 6000 + +#FlexConnect Power Factor +#Default is set to 0 (disable) +gFlexConnectPowerFactor=0 + +#Disable split scan, the FW will take care of it +gNumChanCombinedConc=60 + +#Enable Power Save offload +gEnablePowerSaveOffload=1 + +gEnableWoW=1 + +#Enable or Disable p2p device address administered +isP2pDeviceAddrAdministrated=0 + +#Disable scan_pno by default +gPNOScanSupport=0 + +#Enable TDLS +gEnableTDLSSupport=1 + +# Regulatory Setting; 0=STRICT; 1=CUSTOM +gRegulatoryChangeCountry=1 + +# Enable or Disable Rx thread +# 1=Enable (default), 0=Disable +gEnableRxThread=0 + +# Enable or Disable FW self-recovery +# Currently, It's for USB only. +# 1=Enable, 0=Disable (default) +gEnableFwSelfRecovery=0 +gEnableSelfRecovery=0 +gEnableForceTargetAssert=0 +# Enable or Disable SAP suspend +# 1=Enable (default), 0=Disable +gEnableSapSuspend=0 + +# Enable TxBF +gTxBFEnable=1 + +# Enable or Disable WOW Pulse feature +# 1 = Enable, 0 = Disable (default) +gwow_pulse_support = 0 + +#P2P Listen offload +gEnableP2pListenOffload=1 + +# gEnableSAPAuthOffload: Enable Software AP Authentication Offload feature +# 1=Enable, 0=Disable (default) +gEnableSAPAuthOffload=0 + +# Sifs burst feature configuration +gEnableSifsBurst=1 +gSoftApMaxPeers=32 + +gVhtMpduLen=2 +# FW reorder +gReorderOffloadSupported=1 +# DFS Master Capability +gEnableDFSMasterCap=1 + +#Fine tuned TxFlow parameters +TxFlowLowWaterMark=300 +TxFlowHighWaterMarkOffset=94 + +# PTA +gCoexPtaConfigEnable=0 +gCoexPtaConfigParam=0 +gEnableNanSupport=0 + +#ETSI +gStaLocalEDCAForETSI=0 +#TxBF in 20MHz +gEnableTxBFin20MHz=1 +END +# Note: Configuration parser would not read anything past the END marker