5197 lines
137 KiB
Diff
5197 lines
137 KiB
Diff
Index: u-boot-imx/arch/arm/dts/Makefile
|
|
===================================================================
|
|
--- u-boot-imx.orig/arch/arm/dts/Makefile
|
|
+++ u-boot-imx/arch/arm/dts/Makefile
|
|
@@ -468,7 +468,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-e
|
|
fsl-imx8mm-ddr3l-val.dtb \
|
|
fsl-imx8mm-ddr4-evk.dtb \
|
|
fsl-imx8mm-ddr4-val.dtb \
|
|
- fsl-imx8mm-evk.dtb
|
|
+ fsl-imx8mm-evk.dtb \
|
|
+ fsl-imx8mm-tgr.dtb
|
|
|
|
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8dx-17x17-val.dtb \
|
|
fsl-imx8qm-ddr4-arm2.dtb \
|
|
Index: u-boot-imx/arch/arm/dts/fsl-imx8mm-tgr.dts
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/arch/arm/dts/fsl-imx8mm-tgr.dts
|
|
@@ -0,0 +1,466 @@
|
|
+/*
|
|
+ * Copyright 2018 NXP
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License
|
|
+ * as published by the Free Software Foundation; either version 2
|
|
+ * of the License, or (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "fsl-imx8mm.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Tiesse TGR";
|
|
+ compatible = "fsl,imx8mm-tgr", "fsl,imx8mm";
|
|
+
|
|
+ chosen {
|
|
+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
|
|
+ stdout-patch = &uart2;
|
|
+ };
|
|
+
|
|
+ reg_usdhc2_vmmc: regulator-usdhc2 {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "VSD_3V3";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
|
+ enable-active-high;
|
|
+ startup-delay-us = <100>;
|
|
+ off-on-delay-us = <12000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&iomuxc {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_hog_1>;
|
|
+
|
|
+ imx8mm-evk {
|
|
+ pinctrl_hog_1: hoggrp-1 {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x10
|
|
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x10
|
|
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x10
|
|
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x10
|
|
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x10
|
|
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x10
|
|
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x80
|
|
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x10
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_fec1: fec1grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
|
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
|
+ MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
|
|
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
|
|
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
|
|
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
|
|
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
|
|
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
|
|
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
|
|
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_flexspi0: flexspi0grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
|
|
+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
|
|
+
|
|
+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
|
|
+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
|
|
+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
|
|
+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c1: i2c1grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
|
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c2: i2c2grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
|
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c3: i2c3grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
|
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c1_gpio: i2c1grp-gpio {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
|
|
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
|
|
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
|
|
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pmic: pmicirq {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_uart2: uart1grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
|
|
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2: usdhc2grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
|
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
|
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
|
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
|
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
|
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
|
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
|
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
|
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
|
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
|
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
|
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
|
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
|
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
|
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
|
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
|
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
|
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
|
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc3: usdhc3grp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
|
|
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
|
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
|
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
|
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
|
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
|
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_wdog: wdoggrp {
|
|
+ fsl,pins = <
|
|
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
|
+ >;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ clock-frequency = <400000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c1>;
|
|
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
|
+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
|
|
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+
|
|
+ pmic: pca9450@25 {
|
|
+ reg = <0x25>;
|
|
+ compatible = "nxp,pca9450b";
|
|
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
|
|
+ pinctrl-0 = <&pinctrl_pmic>;
|
|
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
|
+
|
|
+ gpo {
|
|
+ nxp,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
|
|
+ };
|
|
+
|
|
+ regulators {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ pca9450,pmic-buck2-uses-i2c-dvs;
|
|
+ pca9450,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
|
|
+
|
|
+ buck1_reg: regulator@0 {
|
|
+ reg = <0>;
|
|
+ regulator-compatible = "buck1";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <2187500>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ regulator-ramp-delay = <3125>;
|
|
+ };
|
|
+
|
|
+ buck2_reg: regulator@1 {
|
|
+ reg = <1>;
|
|
+ regulator-compatible = "buck2";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <2187500>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ regulator-ramp-delay = <3125>;
|
|
+ };
|
|
+
|
|
+ buck3_reg: regulator@2 {
|
|
+ reg = <2>;
|
|
+ regulator-compatible = "buck3";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <2187500>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ buck4_reg: regulator@3 {
|
|
+ reg = <3>;
|
|
+ regulator-compatible = "buck4";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <3400000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ buck5_reg: regulator@4 {
|
|
+ reg = <4>;
|
|
+ regulator-compatible = "buck5";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <3400000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ buck6_reg: regulator@5 {
|
|
+ reg = <5>;
|
|
+ regulator-compatible = "buck6";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <3400000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ ldo1_reg: regulator@6 {
|
|
+ reg = <6>;
|
|
+ regulator-compatible = "ldo1";
|
|
+ regulator-min-microvolt = <1600000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ ldo2_reg: regulator@7 {
|
|
+ reg = <7>;
|
|
+ regulator-compatible = "ldo2";
|
|
+ regulator-min-microvolt = <800000>;
|
|
+ regulator-max-microvolt = <1150000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ ldo3_reg: regulator@8 {
|
|
+ reg = <8>;
|
|
+ regulator-compatible = "ldo3";
|
|
+ regulator-min-microvolt = <800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ ldo4_reg: regulator@9 {
|
|
+ reg = <9>;
|
|
+ regulator-compatible = "ldo4";
|
|
+ regulator-min-microvolt = <800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ ldo5_reg: regulator@10 {
|
|
+ reg = <10>;
|
|
+ regulator-compatible = "ldo5";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ clock-frequency = <400000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c2>;
|
|
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
|
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
|
|
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c3 {
|
|
+ clock-frequency = <100000>;
|
|
+ pinctrl-names = "default", "gpio";
|
|
+ pinctrl-0 = <&pinctrl_i2c3>;
|
|
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
|
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
|
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&flexspi0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_flexspi0>;
|
|
+ status = "okay";
|
|
+
|
|
+ flash0: n25q256a@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "spi-flash";
|
|
+ spi-max-frequency = <29000000>;
|
|
+ spi-nor,ddr-quad-read-dummy = <8>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&fec1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_fec1>;
|
|
+ phy-mode = "rmii";
|
|
+ phy-handle = <ðphy0>;
|
|
+ fsl,magic-packet;
|
|
+ status = "okay";
|
|
+
|
|
+ mdio {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ ethphy0: ethernet-phy@5 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <0x5>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart2 { /* console */
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart2>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usdhc2 {
|
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
|
+ bus-width = <4>;
|
|
+ non-removable;
|
|
+ vmmc-supply = <®_usdhc2_vmmc>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usdhc3 {
|
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
+ pinctrl-0 = <&pinctrl_usdhc3>;
|
|
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
+ bus-width = <8>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&wdog1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_wdog>;
|
|
+ fsl,ext-reset-output;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&A53_0 {
|
|
+ arm-supply = <&buck2_reg>;
|
|
+};
|
|
+
|
|
+&usbotg1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg2 {
|
|
+ status = "okay";
|
|
+};
|
|
Index: u-boot-imx/arch/arm/mach-imx/imx8m/Kconfig
|
|
===================================================================
|
|
--- u-boot-imx.orig/arch/arm/mach-imx/imx8m/Kconfig
|
|
+++ u-boot-imx/arch/arm/mach-imx/imx8m/Kconfig
|
|
@@ -60,6 +60,12 @@ config TARGET_IMX8MM_EVK
|
|
select SUPPORT_SPL
|
|
select IMX8M_LPDDR4
|
|
|
|
+config TARGET_TGR
|
|
+ bool "Tiesse imx8mm TGR board"
|
|
+ select IMX8MM
|
|
+ select SUPPORT_SPL
|
|
+ select IMX8M_LPDDR4
|
|
+
|
|
config TARGET_IMX8MM_DDR4_EVK
|
|
bool "imx8mm DDR4 EVK board"
|
|
select IMX8MM
|
|
@@ -76,6 +82,7 @@ source "board/freescale/imx8mq_arm2/Kcon
|
|
source "board/freescale/imx8mq_phanbell/Kconfig"
|
|
source "board/freescale/imx8mq_aiy/Kconfig"
|
|
source "board/freescale/imx8mm_evk/Kconfig"
|
|
+source "board/tiesse/tgr/Kconfig"
|
|
source "board/freescale/imx8mm_val/Kconfig"
|
|
|
|
endif
|
|
Index: u-boot-imx/board/tiesse/tgr/Kconfig
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/board/tiesse/tgr/Kconfig
|
|
@@ -0,0 +1,14 @@
|
|
+if TARGET_TGR
|
|
+
|
|
+config SYS_BOARD
|
|
+ default "tgr"
|
|
+
|
|
+config SYS_VENDOR
|
|
+ default "tiesse"
|
|
+
|
|
+config SYS_CONFIG_NAME
|
|
+ default "tgr"
|
|
+
|
|
+source "board/freescale/common/Kconfig"
|
|
+
|
|
+endif
|
|
Index: u-boot-imx/board/tiesse/tgr/Makefile
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/board/tiesse/tgr/Makefile
|
|
@@ -0,0 +1,13 @@
|
|
+#
|
|
+# Copyright 2018 NXP
|
|
+#
|
|
+# SPDX-License-Identifier: GPL-2.0+
|
|
+#
|
|
+
|
|
+obj-y += tgr.o
|
|
+
|
|
+ifdef CONFIG_SPL_BUILD
|
|
+obj-y += spl.o
|
|
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
|
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
|
|
+endif
|
|
Index: u-boot-imx/board/tiesse/tgr/ddr4_timing.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/board/tiesse/tgr/ddr4_timing.c
|
|
@@ -0,0 +1,1482 @@
|
|
+/*
|
|
+ * Copyright 2018 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <common.h>
|
|
+#include <asm/arch/ddr.h>
|
|
+#include <asm/arch/imx8m_ddr.h>
|
|
+
|
|
+struct dram_cfg_param ddr4_ddrc_cfg[] = {
|
|
+ /* Start to config, default 2400mbps */
|
|
+ { DDRC_MSTR(0), 0x81040010 },
|
|
+ { DDRC_PWRCTL(0), 0x000000aa },
|
|
+ { DDRC_PWRTMG(0), 0x00221306 },
|
|
+ { DDRC_RFSHCTL0(0), 0x00c0a070 },
|
|
+ { DDRC_RFSHCTL1(0), 0x00010008 },
|
|
+ { DDRC_RFSHCTL3(0), 0x00000000 },
|
|
+ { DDRC_RFSHTMG(0), 0x004980f4 },
|
|
+ { DDRC_CRCPARCTL0(0), 0x00000000 },
|
|
+ { DDRC_CRCPARCTL1(0), 0x00001010 },
|
|
+ { DDRC_INIT0(0), 0xc0030002 },
|
|
+ { DDRC_INIT1(0), 0x00020009 },
|
|
+ { DDRC_INIT2(0), 0x0000350f },
|
|
+ { DDRC_INIT3(0), (0xa34 << 16) | 0x105 },
|
|
+ { DDRC_INIT4(0), (0x1028 << 16) | 0x200 },
|
|
+ { DDRC_INIT5(0), 0x001103cb },
|
|
+ { DDRC_INIT6(0), (0x200 << 16) | 0x200 },
|
|
+ { DDRC_INIT7(0), 0x814 },
|
|
+ { DDRC_DIMMCTL(0), 0x00000032 },
|
|
+ { DDRC_RANKCTL(0), 0x00000fc7 },
|
|
+ { DDRC_DRAMTMG0(0), 0x14132813 },
|
|
+ { DDRC_DRAMTMG1(0), 0x0004051b },
|
|
+ { DDRC_DRAMTMG2(0), 0x0808030f },
|
|
+ { DDRC_DRAMTMG3(0), 0x0000400c },
|
|
+ { DDRC_DRAMTMG4(0), 0x08030409 },
|
|
+ { DDRC_DRAMTMG5(0), 0x0e090504 },
|
|
+ { DDRC_DRAMTMG6(0), 0x05030000 },
|
|
+ { DDRC_DRAMTMG7(0), 0x0000090e },
|
|
+ { DDRC_DRAMTMG8(0), 0x0606700c },
|
|
+ { DDRC_DRAMTMG9(0), 0x0002040c },
|
|
+ { DDRC_DRAMTMG10(0), 0x000f0c07 },
|
|
+ { DDRC_DRAMTMG11(0), 0x1809011d },
|
|
+ { DDRC_DRAMTMG12(0), 0x0000000d },
|
|
+ { DDRC_DRAMTMG13(0), 0x2b000000 },
|
|
+ { DDRC_DRAMTMG14(0), 0x000000a4 },
|
|
+ { DDRC_DRAMTMG15(0), 0x00000000 },
|
|
+ { DDRC_DRAMTMG17(0), 0x00250078 },
|
|
+ { DDRC_ZQCTL0(0), 0x51000040 },
|
|
+ { DDRC_ZQCTL1(0), 0x00000070 },
|
|
+ { DDRC_ZQCTL2(0), 0x00000000 },
|
|
+ { DDRC_DFITMG0(0), 0x038b820b },
|
|
+ { DDRC_DFITMG1(0), 0x02020103 },
|
|
+ { DDRC_DFILPCFG0(0), 0x07f04011 },
|
|
+ { DDRC_DFILPCFG1(0), 0x000000b0 },
|
|
+ { DDRC_DFIUPD0(0), 0xe0400018 },
|
|
+ { DDRC_DFIUPD1(0), 0x0048005a },
|
|
+ { DDRC_DFIUPD2(0), 0x80000000 },
|
|
+ { DDRC_DFIMISC(0), 0x00000001 },
|
|
+ { DDRC_DFITMG2(0), 0x00000b0b },
|
|
+ { DDRC_DFITMG3(0), 0x00000001 },
|
|
+ { DDRC_DBICTL(0), 0x00000000 },
|
|
+ { DDRC_DFIPHYMSTR(0), 0x00000000 },
|
|
+
|
|
+ /* MT40A512M16 addr map */
|
|
+ { DDRC_ADDRMAP0(0), 0x0000001F },
|
|
+ { DDRC_ADDRMAP1(0), 0x003F0909 },
|
|
+ { DDRC_ADDRMAP2(0), 0x01010100 },
|
|
+ { DDRC_ADDRMAP3(0), 0x01010101 },
|
|
+ { DDRC_ADDRMAP4(0), 0x00001f1f },
|
|
+ { DDRC_ADDRMAP5(0), 0x07070707 },
|
|
+ { DDRC_ADDRMAP6(0), 0x07070707 },
|
|
+ { DDRC_ADDRMAP7(0), 0x00000f0f },
|
|
+ { DDRC_ADDRMAP8(0), 0x00003F01 },
|
|
+ { DDRC_ADDRMAP9(0), 0x0a020b06 },
|
|
+ { DDRC_ADDRMAP10(0), 0x0a0a0a0a },
|
|
+ { DDRC_ADDRMAP11(0), 0x00000000 },
|
|
+
|
|
+ { DDRC_ODTCFG(0), 0x07000600 },
|
|
+ { DDRC_ODTMAP(0), 0x0001 },
|
|
+
|
|
+ /* P1 400mts */
|
|
+ { DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 },
|
|
+ { DDRC_FREQ1_RFSHTMG(0), 0x0018001a },
|
|
+ { DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 },
|
|
+ { DDRC_FREQ1_INIT4(0), (0x1000 << 16) },
|
|
+ { DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 },
|
|
+ { DDRC_FREQ1_INIT7(0), 0x14 },
|
|
+ { DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */
|
|
+ { DDRC_FREQ1_DRAMTMG1(0), 0x00030314 },
|
|
+ { DDRC_FREQ1_DRAMTMG2(0), 0x0505040a },
|
|
+ { DDRC_FREQ1_DRAMTMG3(0), 0x0000400c },
|
|
+ { DDRC_FREQ1_DRAMTMG4(0), 0x06040307 },
|
|
+ { DDRC_FREQ1_DRAMTMG5(0), 0x090d0202 },
|
|
+ { DDRC_FREQ1_DRAMTMG6(0), 0x0a070008 },
|
|
+ { DDRC_FREQ1_DRAMTMG7(0), 0x00000d09 },
|
|
+ { DDRC_FREQ1_DRAMTMG8(0), 0x08084b09 },
|
|
+ { DDRC_FREQ1_DRAMTMG9(0), 0x00020308 },
|
|
+ { DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06 },
|
|
+ { DDRC_FREQ1_DRAMTMG11(0), 0x12060111 },
|
|
+ { DDRC_FREQ1_DRAMTMG12(0), 0x00000008 },
|
|
+ { DDRC_FREQ1_DRAMTMG13(0), 0x21000000 },
|
|
+ { DDRC_FREQ1_DRAMTMG14(0), 0x00000000 },
|
|
+ { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
|
|
+ { DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d },
|
|
+ { DDRC_FREQ1_ZQCTL0(0), 0x51000040 },
|
|
+ { DDRC_FREQ1_DFITMG0(0), 0x03858204 },
|
|
+ { DDRC_FREQ1_DFITMG1(0), 0x00020103 },
|
|
+ { DDRC_FREQ1_DFITMG2(0), 0x00000504 },
|
|
+ { DDRC_FREQ1_DFITMG3(0), 0x00000001 },
|
|
+ { DDRC_FREQ1_ODTCFG(0), 0x07000601 },
|
|
+
|
|
+ /* p2 100mts */
|
|
+ { DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 },
|
|
+ { DDRC_FREQ2_RFSHTMG(0), 0x0006000e }, /* tREFI=7.8us */
|
|
+ { DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 },
|
|
+ { DDRC_FREQ2_INIT4(0), (0x1000 << 16) },
|
|
+ { DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 },
|
|
+ { DDRC_FREQ2_INIT7(0), 0x14 },
|
|
+ { DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 }, /* t_ras_max=9*7.8us, t_ras_min=35ns */
|
|
+ { DDRC_FREQ2_DRAMTMG1(0), 0x00030314 },
|
|
+ { DDRC_FREQ2_DRAMTMG2(0), 0x0505040a },
|
|
+ { DDRC_FREQ2_DRAMTMG3(0), 0x0000400c },
|
|
+ { DDRC_FREQ2_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */
|
|
+ { DDRC_FREQ2_DRAMTMG5(0), 0x090d0202 },
|
|
+ { DDRC_FREQ2_DRAMTMG6(0), 0x0a070008 },
|
|
+ { DDRC_FREQ2_DRAMTMG7(0), 0x00000d09 },
|
|
+ { DDRC_FREQ2_DRAMTMG8(0), 0x08084b09 },
|
|
+ { DDRC_FREQ2_DRAMTMG9(0), 0x00020308 },
|
|
+ { DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06 },
|
|
+ { DDRC_FREQ2_DRAMTMG11(0), 0x12060111 },
|
|
+ { DDRC_FREQ2_DRAMTMG12(0), 0x00000008 },
|
|
+ { DDRC_FREQ2_DRAMTMG13(0), 0x21000000 },
|
|
+ { DDRC_FREQ2_DRAMTMG14(0), 0x00000000 },
|
|
+ { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 },
|
|
+ { DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d },
|
|
+ { DDRC_FREQ2_ZQCTL0(0), 0x51000040 },
|
|
+ { DDRC_FREQ2_DFITMG0(0), 0x03858204 },
|
|
+ { DDRC_FREQ2_DFITMG1(0), 0x00020103 },
|
|
+ { DDRC_FREQ2_DFITMG2(0), 0x00000504 },
|
|
+ { DDRC_FREQ2_DFITMG3(0), 0x00000001 },
|
|
+ { DDRC_FREQ2_ODTCFG(0), 0x07000601 },
|
|
+};
|
|
+
|
|
+/* PHY Initialize Configuration */
|
|
+struct dram_cfg_param ddr4_ddrphy_cfg[] = {
|
|
+ { 0x1005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
|
|
+ { 0x1015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
|
|
+ { 0x1105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
|
|
+ { 0x1115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
|
|
+ { 0x1205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
|
|
+ { 0x1215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
|
|
+ { 0x1305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
|
|
+ { 0x1315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
|
|
+
|
|
+ { 0x11005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */
|
|
+ { 0x11015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */
|
|
+ { 0x11105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */
|
|
+ { 0x11115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */
|
|
+ { 0x11205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */
|
|
+ { 0x11215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */
|
|
+ { 0x11305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */
|
|
+ { 0x11315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */
|
|
+
|
|
+ { 0x21005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */
|
|
+ { 0x21015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */
|
|
+ { 0x21105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */
|
|
+ { 0x21115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */
|
|
+ { 0x21205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */
|
|
+ { 0x21215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */
|
|
+ { 0x21305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */
|
|
+ { 0x21315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */
|
|
+
|
|
+ { 0x55, 0x355 }, /* DWC_DDRPHYA_ANIB0_ATxSlewRate */
|
|
+ { 0x1055, 0x355 }, /* DWC_DDRPHYA_ANIB1_ATxSlewRate */
|
|
+ { 0x2055, 0x355 }, /* DWC_DDRPHYA_ANIB2_ATxSlewRate */
|
|
+ { 0x3055, 0x355 }, /* DWC_DDRPHYA_ANIB3_ATxSlewRate */
|
|
+ { 0x4055, 0x55 }, /* DWC_DDRPHYA_ANIB4_ATxSlewRate */
|
|
+ { 0x5055, 0x55 }, /* DWC_DDRPHYA_ANIB5_ATxSlewRate */
|
|
+ { 0x6055, 0x355 }, /* DWC_DDRPHYA_ANIB6_ATxSlewRate */
|
|
+ { 0x7055, 0x355 }, /* DWC_DDRPHYA_ANIB7_ATxSlewRate */
|
|
+ { 0x8055, 0x355 }, /* DWC_DDRPHYA_ANIB8_ATxSlewRate */
|
|
+ { 0x9055, 0x355 }, /* DWC_DDRPHYA_ANIB9_ATxSlewRate */
|
|
+
|
|
+ { 0x200c5, 0xa }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
|
|
+ { 0x1200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */
|
|
+ { 0x2200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */
|
|
+
|
|
+ { 0x2002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
|
|
+ { 0x12002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */
|
|
+ { 0x22002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */
|
|
+
|
|
+ { 0x20024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
|
|
+ { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
|
|
+
|
|
+ { 0x120024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */
|
|
+ { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
|
|
+
|
|
+ { 0x220024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */
|
|
+ { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
|
|
+
|
|
+ { 0x20056, 0x6 },/* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
|
|
+ { 0x120056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */
|
|
+ { 0x220056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */
|
|
+
|
|
+ { 0x1004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
|
|
+ { 0x1014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
|
|
+ { 0x1104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
|
|
+ { 0x1114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
|
|
+ { 0x1204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
|
|
+ { 0x1214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
|
|
+ { 0x1304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
|
|
+ { 0x1314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
|
|
+
|
|
+ { 0x11004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */
|
|
+ { 0x11014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */
|
|
+ { 0x11104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */
|
|
+ { 0x11114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */
|
|
+ { 0x11204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */
|
|
+ { 0x11214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */
|
|
+ { 0x11304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */
|
|
+ { 0x11314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */
|
|
+
|
|
+ { 0x21004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */
|
|
+ { 0x21014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */
|
|
+ { 0x21104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */
|
|
+ { 0x21114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */
|
|
+ { 0x21204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */
|
|
+ { 0x21214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */
|
|
+ { 0x21304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */
|
|
+ { 0x21314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */
|
|
+
|
|
+ { 0x10049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
|
|
+ { 0x10149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
|
|
+ { 0x11049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
|
|
+ { 0x11149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
|
|
+ { 0x12049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
|
|
+ { 0x12149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
|
|
+ { 0x13049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
|
|
+ { 0x13149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
|
|
+
|
|
+ { 0x110049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */
|
|
+ { 0x110149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */
|
|
+ { 0x111049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */
|
|
+ { 0x111149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */
|
|
+ { 0x112049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */
|
|
+ { 0x112149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */
|
|
+ { 0x113049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */
|
|
+ { 0x113149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */
|
|
+
|
|
+ { 0x210049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */
|
|
+ { 0x210149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */
|
|
+ { 0x211049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */
|
|
+ { 0x211149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */
|
|
+ { 0x212049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */
|
|
+ { 0x212149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */
|
|
+ { 0x213049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */
|
|
+ { 0x213149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */
|
|
+
|
|
+ { 0x43, 0x63 }, /* DWC_DDRPHYA_ANIB0_ATxImpedance */
|
|
+ { 0x1043, 0x63 }, /* DWC_DDRPHYA_ANIB1_ATxImpedance */
|
|
+ { 0x2043, 0x63 }, /* DWC_DDRPHYA_ANIB2_ATxImpedance */
|
|
+ { 0x3043, 0x63 }, /* DWC_DDRPHYA_ANIB3_ATxImpedance */
|
|
+ { 0x4043, 0x63 }, /* DWC_DDRPHYA_ANIB4_ATxImpedance */
|
|
+ { 0x5043, 0x63 }, /* DWC_DDRPHYA_ANIB5_ATxImpedance */
|
|
+ { 0x6043, 0x63 }, /* DWC_DDRPHYA_ANIB6_ATxImpedance */
|
|
+ { 0x7043, 0x63 }, /* DWC_DDRPHYA_ANIB7_ATxImpedance */
|
|
+ { 0x8043, 0x63 }, /* DWC_DDRPHYA_ANIB8_ATxImpedance */
|
|
+ { 0x9043, 0x63 }, /* DWC_DDRPHYA_ANIB9_ATxImpedance */
|
|
+
|
|
+ { 0x20018, 0x5 }, /* DWC_DDRPHYA_MASTER0_DfiMode */
|
|
+ { 0x20075, 0x2 }, /* DWC_DDRPHYA_MASTER0_DfiCAMode */
|
|
+ { 0x20050, 0x0 }, /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */
|
|
+ { 0x20008, 0x258 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
|
|
+ { 0x120008, 0x64 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */
|
|
+ { 0x220008, 0x19 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */
|
|
+ { 0x20088, 0x9 }, /* DWC_DDRPHYA_MASTER0_CalRate */
|
|
+
|
|
+ { 0x200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
|
|
+ { 0x10043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
|
|
+ { 0x10143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
|
|
+ { 0x11043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
|
|
+ { 0x11143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
|
|
+ { 0x12043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
|
|
+ { 0x12143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
|
|
+ { 0x13043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
|
|
+ { 0x13143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
|
|
+
|
|
+ { 0x1200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */
|
|
+ { 0x110043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */
|
|
+ { 0x110143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */
|
|
+ { 0x111043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */
|
|
+ { 0x111143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */
|
|
+ { 0x112043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */
|
|
+ { 0x112143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */
|
|
+ { 0x113043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */
|
|
+ { 0x113143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */
|
|
+
|
|
+ { 0x2200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */
|
|
+ { 0x210043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */
|
|
+ { 0x210143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */
|
|
+ { 0x211043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */
|
|
+ { 0x211143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */
|
|
+ { 0x212043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */
|
|
+ { 0x212143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */
|
|
+ { 0x213043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */
|
|
+ { 0x213143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */
|
|
+
|
|
+ { 0x2005b, 0x7529 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl */
|
|
+ { 0x2005c, 0x0 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */
|
|
+ { 0x200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
|
|
+ { 0x1200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */
|
|
+ { 0x2200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */
|
|
+ { 0x20019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
|
|
+ { 0x120019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */
|
|
+ { 0x220019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */
|
|
+
|
|
+ { 0x200f0, 0x5665 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
|
|
+ { 0x200f1, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
|
|
+ { 0x200f2, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
|
|
+ { 0x200f3, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
|
|
+ { 0x200f4, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
|
|
+ { 0x200f5, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
|
|
+ { 0x200f6, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
|
|
+ { 0x200f7, 0xf000 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
|
|
+ { 0x20025, 0x0 }, /* DWC_DDRPHYA_MASTER0_MasterX4Config */
|
|
+ { 0x2002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
|
|
+ { 0x12002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */
|
|
+ { 0x22002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */
|
|
+ { 0x200c7, 0x21 }, /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */
|
|
+ { 0x200ca, 0x24 }, /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */
|
|
+};
|
|
+
|
|
+/* ddr phy trained csr */
|
|
+struct dram_cfg_param ddr4_ddrphy_trained_csr[] = {
|
|
+ { 0x200b2, 0x0 },
|
|
+ { 0x1200b2, 0x0 },
|
|
+ { 0x2200b2, 0x0 },
|
|
+ { 0x200cb, 0x0 },
|
|
+ { 0x10043, 0x0 },
|
|
+ { 0x110043, 0x0 },
|
|
+ { 0x210043, 0x0 },
|
|
+ { 0x10143, 0x0 },
|
|
+ { 0x110143, 0x0 },
|
|
+ { 0x210143, 0x0 },
|
|
+ { 0x11043, 0x0 },
|
|
+ { 0x111043, 0x0 },
|
|
+ { 0x211043, 0x0 },
|
|
+ { 0x11143, 0x0 },
|
|
+ { 0x111143, 0x0 },
|
|
+ { 0x211143, 0x0 },
|
|
+ { 0x12043, 0x0 },
|
|
+ { 0x112043, 0x0 },
|
|
+ { 0x212043, 0x0 },
|
|
+ { 0x12143, 0x0 },
|
|
+ { 0x112143, 0x0 },
|
|
+ { 0x212143, 0x0 },
|
|
+ { 0x13043, 0x0 },
|
|
+ { 0x113043, 0x0 },
|
|
+ { 0x213043, 0x0 },
|
|
+ { 0x13143, 0x0 },
|
|
+ { 0x113143, 0x0 },
|
|
+ { 0x213143, 0x0 },
|
|
+ { 0x80, 0x0 },
|
|
+ { 0x100080, 0x0 },
|
|
+ { 0x200080, 0x0 },
|
|
+ { 0x1080, 0x0 },
|
|
+ { 0x101080, 0x0 },
|
|
+ { 0x201080, 0x0 },
|
|
+ { 0x2080, 0x0 },
|
|
+ { 0x102080, 0x0 },
|
|
+ { 0x202080, 0x0 },
|
|
+ { 0x3080, 0x0 },
|
|
+ { 0x103080, 0x0 },
|
|
+ { 0x203080, 0x0 },
|
|
+ { 0x4080, 0x0 },
|
|
+ { 0x104080, 0x0 },
|
|
+ { 0x204080, 0x0 },
|
|
+ { 0x5080, 0x0 },
|
|
+ { 0x105080, 0x0 },
|
|
+ { 0x205080, 0x0 },
|
|
+ { 0x6080, 0x0 },
|
|
+ { 0x106080, 0x0 },
|
|
+ { 0x206080, 0x0 },
|
|
+ { 0x7080, 0x0 },
|
|
+ { 0x107080, 0x0 },
|
|
+ { 0x207080, 0x0 },
|
|
+ { 0x8080, 0x0 },
|
|
+ { 0x108080, 0x0 },
|
|
+ { 0x208080, 0x0 },
|
|
+ { 0x9080, 0x0 },
|
|
+ { 0x109080, 0x0 },
|
|
+ { 0x209080, 0x0 },
|
|
+ { 0x10080, 0x0 },
|
|
+ { 0x110080, 0x0 },
|
|
+ { 0x210080, 0x0 },
|
|
+ { 0x10180, 0x0 },
|
|
+ { 0x110180, 0x0 },
|
|
+ { 0x210180, 0x0 },
|
|
+ { 0x11080, 0x0 },
|
|
+ { 0x111080, 0x0 },
|
|
+ { 0x211080, 0x0 },
|
|
+ { 0x11180, 0x0 },
|
|
+ { 0x111180, 0x0 },
|
|
+ { 0x211180, 0x0 },
|
|
+ { 0x12080, 0x0 },
|
|
+ { 0x112080, 0x0 },
|
|
+ { 0x212080, 0x0 },
|
|
+ { 0x12180, 0x0 },
|
|
+ { 0x112180, 0x0 },
|
|
+ { 0x212180, 0x0 },
|
|
+ { 0x13080, 0x0 },
|
|
+ { 0x113080, 0x0 },
|
|
+ { 0x213080, 0x0 },
|
|
+ { 0x13180, 0x0 },
|
|
+ { 0x113180, 0x0 },
|
|
+ { 0x213180, 0x0 },
|
|
+ { 0x10081, 0x0 },
|
|
+ { 0x110081, 0x0 },
|
|
+ { 0x210081, 0x0 },
|
|
+ { 0x10181, 0x0 },
|
|
+ { 0x110181, 0x0 },
|
|
+ { 0x210181, 0x0 },
|
|
+ { 0x11081, 0x0 },
|
|
+ { 0x111081, 0x0 },
|
|
+ { 0x211081, 0x0 },
|
|
+ { 0x11181, 0x0 },
|
|
+ { 0x111181, 0x0 },
|
|
+ { 0x211181, 0x0 },
|
|
+ { 0x12081, 0x0 },
|
|
+ { 0x112081, 0x0 },
|
|
+ { 0x212081, 0x0 },
|
|
+ { 0x12181, 0x0 },
|
|
+ { 0x112181, 0x0 },
|
|
+ { 0x212181, 0x0 },
|
|
+ { 0x13081, 0x0 },
|
|
+ { 0x113081, 0x0 },
|
|
+ { 0x213081, 0x0 },
|
|
+ { 0x13181, 0x0 },
|
|
+ { 0x113181, 0x0 },
|
|
+ { 0x213181, 0x0 },
|
|
+ { 0x100d0, 0x0 },
|
|
+ { 0x1100d0, 0x0 },
|
|
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|
|
+ { 0x220011, 0x0 },
|
|
+ { 0x100ae, 0x0 },
|
|
+ { 0x1100ae, 0x0 },
|
|
+ { 0x2100ae, 0x0 },
|
|
+ { 0x100af, 0x0 },
|
|
+ { 0x1100af, 0x0 },
|
|
+ { 0x2100af, 0x0 },
|
|
+ { 0x110ae, 0x0 },
|
|
+ { 0x1110ae, 0x0 },
|
|
+ { 0x2110ae, 0x0 },
|
|
+ { 0x110af, 0x0 },
|
|
+ { 0x1110af, 0x0 },
|
|
+ { 0x2110af, 0x0 },
|
|
+ { 0x120ae, 0x0 },
|
|
+ { 0x1120ae, 0x0 },
|
|
+ { 0x2120ae, 0x0 },
|
|
+ { 0x120af, 0x0 },
|
|
+ { 0x1120af, 0x0 },
|
|
+ { 0x2120af, 0x0 },
|
|
+ { 0x130ae, 0x0 },
|
|
+ { 0x1130ae, 0x0 },
|
|
+ { 0x2130ae, 0x0 },
|
|
+ { 0x130af, 0x0 },
|
|
+ { 0x1130af, 0x0 },
|
|
+ { 0x2130af, 0x0 },
|
|
+ { 0x20020, 0x0 },
|
|
+ { 0x120020, 0x0 },
|
|
+ { 0x220020, 0x0 },
|
|
+ { 0x100a0, 0x0 },
|
|
+ { 0x100a1, 0x0 },
|
|
+ { 0x100a2, 0x0 },
|
|
+ { 0x100a3, 0x0 },
|
|
+ { 0x100a4, 0x0 },
|
|
+ { 0x100a5, 0x0 },
|
|
+ { 0x100a6, 0x0 },
|
|
+ { 0x100a7, 0x0 },
|
|
+ { 0x110a0, 0x0 },
|
|
+ { 0x110a1, 0x0 },
|
|
+ { 0x110a2, 0x0 },
|
|
+ { 0x110a3, 0x0 },
|
|
+ { 0x110a4, 0x0 },
|
|
+ { 0x110a5, 0x0 },
|
|
+ { 0x110a6, 0x0 },
|
|
+ { 0x110a7, 0x0 },
|
|
+ { 0x120a0, 0x0 },
|
|
+ { 0x120a1, 0x0 },
|
|
+ { 0x120a2, 0x0 },
|
|
+ { 0x120a3, 0x0 },
|
|
+ { 0x120a4, 0x0 },
|
|
+ { 0x120a5, 0x0 },
|
|
+ { 0x120a6, 0x0 },
|
|
+ { 0x120a7, 0x0 },
|
|
+ { 0x130a0, 0x0 },
|
|
+ { 0x130a1, 0x0 },
|
|
+ { 0x130a2, 0x0 },
|
|
+ { 0x130a3, 0x0 },
|
|
+ { 0x130a4, 0x0 },
|
|
+ { 0x130a5, 0x0 },
|
|
+ { 0x130a6, 0x0 },
|
|
+ { 0x130a7, 0x0 },
|
|
+ { 0x2007c, 0x0 },
|
|
+ { 0x12007c, 0x0 },
|
|
+ { 0x22007c, 0x0 },
|
|
+ { 0x2007d, 0x0 },
|
|
+ { 0x12007d, 0x0 },
|
|
+ { 0x22007d, 0x0 },
|
|
+ { 0x400fd, 0x0 },
|
|
+ { 0x400c0, 0x0 },
|
|
+ { 0x90201, 0x0 },
|
|
+ { 0x190201, 0x0 },
|
|
+ { 0x290201, 0x0 },
|
|
+ { 0x90202, 0x0 },
|
|
+ { 0x190202, 0x0 },
|
|
+ { 0x290202, 0x0 },
|
|
+ { 0x90203, 0x0 },
|
|
+ { 0x190203, 0x0 },
|
|
+ { 0x290203, 0x0 },
|
|
+ { 0x90204, 0x0 },
|
|
+ { 0x190204, 0x0 },
|
|
+ { 0x290204, 0x0 },
|
|
+ { 0x90205, 0x0 },
|
|
+ { 0x190205, 0x0 },
|
|
+ { 0x290205, 0x0 },
|
|
+ { 0x90206, 0x0 },
|
|
+ { 0x190206, 0x0 },
|
|
+ { 0x290206, 0x0 },
|
|
+ { 0x90207, 0x0 },
|
|
+ { 0x190207, 0x0 },
|
|
+ { 0x290207, 0x0 },
|
|
+ { 0x90208, 0x0 },
|
|
+ { 0x190208, 0x0 },
|
|
+ { 0x290208, 0x0 },
|
|
+ { 0x10062, 0x0 },
|
|
+ { 0x10162, 0x0 },
|
|
+ { 0x10262, 0x0 },
|
|
+ { 0x10362, 0x0 },
|
|
+ { 0x10462, 0x0 },
|
|
+ { 0x10562, 0x0 },
|
|
+ { 0x10662, 0x0 },
|
|
+ { 0x10762, 0x0 },
|
|
+ { 0x10862, 0x0 },
|
|
+ { 0x11062, 0x0 },
|
|
+ { 0x11162, 0x0 },
|
|
+ { 0x11262, 0x0 },
|
|
+ { 0x11362, 0x0 },
|
|
+ { 0x11462, 0x0 },
|
|
+ { 0x11562, 0x0 },
|
|
+ { 0x11662, 0x0 },
|
|
+ { 0x11762, 0x0 },
|
|
+ { 0x11862, 0x0 },
|
|
+ { 0x12062, 0x0 },
|
|
+ { 0x12162, 0x0 },
|
|
+ { 0x12262, 0x0 },
|
|
+ { 0x12362, 0x0 },
|
|
+ { 0x12462, 0x0 },
|
|
+ { 0x12562, 0x0 },
|
|
+ { 0x12662, 0x0 },
|
|
+ { 0x12762, 0x0 },
|
|
+ { 0x12862, 0x0 },
|
|
+ { 0x13062, 0x0 },
|
|
+ { 0x13162, 0x0 },
|
|
+ { 0x13262, 0x0 },
|
|
+ { 0x13362, 0x0 },
|
|
+ { 0x13462, 0x0 },
|
|
+ { 0x13562, 0x0 },
|
|
+ { 0x13662, 0x0 },
|
|
+ { 0x13762, 0x0 },
|
|
+ { 0x13862, 0x0 },
|
|
+ { 0x20077, 0x0 },
|
|
+ { 0x10001, 0x0 },
|
|
+ { 0x11001, 0x0 },
|
|
+ { 0x12001, 0x0 },
|
|
+ { 0x13001, 0x0 },
|
|
+ { 0x10040, 0x0 },
|
|
+ { 0x10140, 0x0 },
|
|
+ { 0x10240, 0x0 },
|
|
+ { 0x10340, 0x0 },
|
|
+ { 0x10440, 0x0 },
|
|
+ { 0x10540, 0x0 },
|
|
+ { 0x10640, 0x0 },
|
|
+ { 0x10740, 0x0 },
|
|
+ { 0x10840, 0x0 },
|
|
+ { 0x10030, 0x0 },
|
|
+ { 0x10130, 0x0 },
|
|
+ { 0x10230, 0x0 },
|
|
+ { 0x10330, 0x0 },
|
|
+ { 0x10430, 0x0 },
|
|
+ { 0x10530, 0x0 },
|
|
+ { 0x10630, 0x0 },
|
|
+ { 0x10730, 0x0 },
|
|
+ { 0x10830, 0x0 },
|
|
+ { 0x11040, 0x0 },
|
|
+ { 0x11140, 0x0 },
|
|
+ { 0x11240, 0x0 },
|
|
+ { 0x11340, 0x0 },
|
|
+ { 0x11440, 0x0 },
|
|
+ { 0x11540, 0x0 },
|
|
+ { 0x11640, 0x0 },
|
|
+ { 0x11740, 0x0 },
|
|
+ { 0x11840, 0x0 },
|
|
+ { 0x11030, 0x0 },
|
|
+ { 0x11130, 0x0 },
|
|
+ { 0x11230, 0x0 },
|
|
+ { 0x11330, 0x0 },
|
|
+ { 0x11430, 0x0 },
|
|
+ { 0x11530, 0x0 },
|
|
+ { 0x11630, 0x0 },
|
|
+ { 0x11730, 0x0 },
|
|
+ { 0x11830, 0x0 },
|
|
+ { 0x12040, 0x0 },
|
|
+ { 0x12140, 0x0 },
|
|
+ { 0x12240, 0x0 },
|
|
+ { 0x12340, 0x0 },
|
|
+ { 0x12440, 0x0 },
|
|
+ { 0x12540, 0x0 },
|
|
+ { 0x12640, 0x0 },
|
|
+ { 0x12740, 0x0 },
|
|
+ { 0x12840, 0x0 },
|
|
+ { 0x12030, 0x0 },
|
|
+ { 0x12130, 0x0 },
|
|
+ { 0x12230, 0x0 },
|
|
+ { 0x12330, 0x0 },
|
|
+ { 0x12430, 0x0 },
|
|
+ { 0x12530, 0x0 },
|
|
+ { 0x12630, 0x0 },
|
|
+ { 0x12730, 0x0 },
|
|
+ { 0x12830, 0x0 },
|
|
+ { 0x13040, 0x0 },
|
|
+ { 0x13140, 0x0 },
|
|
+ { 0x13240, 0x0 },
|
|
+ { 0x13340, 0x0 },
|
|
+ { 0x13440, 0x0 },
|
|
+ { 0x13540, 0x0 },
|
|
+ { 0x13640, 0x0 },
|
|
+ { 0x13740, 0x0 },
|
|
+ { 0x13840, 0x0 },
|
|
+ { 0x13030, 0x0 },
|
|
+ { 0x13130, 0x0 },
|
|
+ { 0x13230, 0x0 },
|
|
+ { 0x13330, 0x0 },
|
|
+ { 0x13430, 0x0 },
|
|
+ { 0x13530, 0x0 },
|
|
+ { 0x13630, 0x0 },
|
|
+ { 0x13730, 0x0 },
|
|
+ { 0x13830, 0x0 },
|
|
+};
|
|
+
|
|
+/* P0 message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr4_fsp0_cfg[] = {
|
|
+ { 0x20060, 0x2 },
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54000, 0x0 },
|
|
+ { 0x54001, 0x0 },
|
|
+ { 0x54002, 0x0 },
|
|
+ { 0x54003, 0x960 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x0 },
|
|
+ { 0x54006, 0x25e },
|
|
+ { 0x54007, 0x2000 },
|
|
+ { 0x54008, 0x101 },
|
|
+ { 0x54009, 0x0 },
|
|
+ { 0x5400a, 0x0 },
|
|
+ { 0x5400b, 0x31f },
|
|
+ { 0x5400c, 0xc8 },
|
|
+ { 0x5400d, 0x0 },
|
|
+ { 0x5400e, 0x0 },
|
|
+ { 0x5400f, 0x0 },
|
|
+ { 0x54010, 0x0 },
|
|
+ { 0x54011, 0x0 },
|
|
+ { 0x54012, 0x1 },
|
|
+ { 0x5402f, 0xa34 },
|
|
+ { 0x54030, 0x105 },
|
|
+ { 0x54031, 0x1028 },
|
|
+ { 0x54032, 0x200 },
|
|
+ { 0x54033, 0x200 },
|
|
+ { 0x54034, 0x200 },
|
|
+ { 0x54035, 0x814 },
|
|
+ { 0x54036, 0x101 },
|
|
+ { 0x54037, 0x0 },
|
|
+ { 0x54038, 0x0 },
|
|
+ { 0x54039, 0x0 },
|
|
+ { 0x5403a, 0x0 },
|
|
+ { 0x5403b, 0x0 },
|
|
+ { 0x5403c, 0x0 },
|
|
+ { 0x5403d, 0x0 },
|
|
+ { 0x5403e, 0x0 },
|
|
+ { 0x5403f, 0x1221 },
|
|
+ { 0x541fc, 0x100 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+/* P1 message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr4_fsp1_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54000, 0x0 },
|
|
+ { 0x54001, 0x0 },
|
|
+ { 0x54002, 0x101 },
|
|
+ { 0x54003, 0x190 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x0 },
|
|
+ { 0x54006, 0x25e },
|
|
+ { 0x54007, 0x2000 },
|
|
+ { 0x54008, 0x101 },
|
|
+ { 0x54009, 0x0 },
|
|
+ { 0x5400a, 0x0 },
|
|
+ { 0x5400b, 0x21f },
|
|
+ { 0x5400c, 0xc8 },
|
|
+ { 0x5400d, 0x0 },
|
|
+ { 0x5400e, 0x0 },
|
|
+ { 0x5400f, 0x0 },
|
|
+ { 0x54010, 0x0 },
|
|
+ { 0x54011, 0x0 },
|
|
+ { 0x54012, 0x1 },
|
|
+ { 0x5402f, 0x204 },
|
|
+ { 0x54030, 0x104 },
|
|
+ { 0x54031, 0x1000 },
|
|
+ { 0x54032, 0x0 },
|
|
+ { 0x54033, 0x200 },
|
|
+ { 0x54034, 0x200 },
|
|
+ { 0x54035, 0x14 },
|
|
+ { 0x54036, 0x101 },
|
|
+ { 0x54037, 0x0 },
|
|
+ { 0x54038, 0x0 },
|
|
+ { 0x54039, 0x0 },
|
|
+ { 0x5403a, 0x0 },
|
|
+ { 0x5403b, 0x0 },
|
|
+ { 0x5403c, 0x0 },
|
|
+ { 0x5403d, 0x0 },
|
|
+ { 0x5403e, 0x0 },
|
|
+ { 0x5403f, 0x1221 },
|
|
+ { 0x541fc, 0x100 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+/* P2 message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr4_fsp2_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54000, 0x0 },
|
|
+ { 0x54001, 0x0 },
|
|
+ { 0x54002, 0x102 },
|
|
+ { 0x54003, 0x64 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x0 },
|
|
+ { 0x54006, 0x25e },
|
|
+ { 0x54007, 0x2000 },
|
|
+ { 0x54008, 0x101 },
|
|
+ { 0x54009, 0x0 },
|
|
+ { 0x5400a, 0x0 },
|
|
+ { 0x5400b, 0x21f },
|
|
+ { 0x5400c, 0xc8 },
|
|
+ { 0x5400d, 0x0 },
|
|
+ { 0x5400e, 0x0 },
|
|
+ { 0x5400f, 0x0 },
|
|
+ { 0x54010, 0x0 },
|
|
+ { 0x54011, 0x0 },
|
|
+ { 0x54012, 0x1 },
|
|
+ { 0x5402f, 0x204 },
|
|
+ { 0x54030, 0x104 },
|
|
+ { 0x54031, 0x1000 },
|
|
+ { 0x54032, 0x0 },
|
|
+ { 0x54033, 0x200 },
|
|
+ { 0x54034, 0x200 },
|
|
+ { 0x54035, 0x14 },
|
|
+ { 0x54036, 0x101 },
|
|
+ { 0x54037, 0x0 },
|
|
+ { 0x54038, 0x0 },
|
|
+ { 0x54039, 0x0 },
|
|
+ { 0x5403a, 0x0 },
|
|
+ { 0x5403b, 0x0 },
|
|
+ { 0x5403c, 0x0 },
|
|
+ { 0x5403d, 0x0 },
|
|
+ { 0x5403e, 0x0 },
|
|
+ { 0x5403f, 0x1221 },
|
|
+ { 0x541fc, 0x100 },
|
|
+ { 0xd0000, 0x1 },
|
|
+
|
|
+};
|
|
+
|
|
+/* P0 2D message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr4_fsp0_2d_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54000, 0x0 },
|
|
+ { 0x54001, 0x0 },
|
|
+ { 0x54002, 0x0 },
|
|
+ { 0x54003, 0x960 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x0 },
|
|
+ { 0x54006, 0x25e },
|
|
+ { 0x54007, 0x2000 },
|
|
+ { 0x54008, 0x101 },
|
|
+ { 0x54009, 0x0 },
|
|
+ { 0x5400a, 0x0 },
|
|
+ { 0x5400b, 0x61 },
|
|
+ { 0x5400c, 0xc8 },
|
|
+ { 0x5400d, 0x100 },
|
|
+ { 0x5400e, 0x1f7f },
|
|
+ { 0x5400f, 0x0 },
|
|
+ { 0x54010, 0x0 },
|
|
+ { 0x54011, 0x0 },
|
|
+ { 0x54012, 0x1 },
|
|
+ { 0x5402f, 0xa34 },
|
|
+ { 0x54030, 0x105 },
|
|
+ { 0x54031, 0x1028 },
|
|
+ { 0x54032, 0x200 },
|
|
+ { 0x54033, 0x200 },
|
|
+ { 0x54034, 0x200 },
|
|
+ { 0x54035, 0x814 },
|
|
+ { 0x54036, 0x101 },
|
|
+ { 0x54037, 0x0 },
|
|
+ { 0x54038, 0x0 },
|
|
+ { 0x54039, 0x0 },
|
|
+ { 0x5403a, 0x0 },
|
|
+ { 0x5403b, 0x0 },
|
|
+ { 0x5403c, 0x0 },
|
|
+ { 0x5403d, 0x0 },
|
|
+ { 0x5403e, 0x0 },
|
|
+ { 0x5403f, 0x1221 },
|
|
+ { 0x541fc, 0x100 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+/* DRAM PHY init engine image */
|
|
+struct dram_cfg_param ddr4_phy_pie[] = {
|
|
+ { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
|
|
+ { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
|
|
+ { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
|
|
+ { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
|
|
+ { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
|
|
+ { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
|
|
+ { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
|
|
+ { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
|
|
+ { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
|
|
+ { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
|
|
+ { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
|
|
+ { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
|
|
+ { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
|
|
+ { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
|
|
+ { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
|
|
+ { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
|
|
+ { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
|
|
+ { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
|
|
+ { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
|
|
+ { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
|
|
+ { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
|
|
+ { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
|
|
+ { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
|
|
+ { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
|
|
+ { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
|
|
+ { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
|
|
+ { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
|
|
+ { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
|
|
+ { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
|
|
+ { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
|
|
+ { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
|
|
+ { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
|
|
+ { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
|
|
+ { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
|
|
+ { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
|
|
+ { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
|
|
+ { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
|
|
+ { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
|
|
+ { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
|
|
+ { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
|
|
+ { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
|
|
+ { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
|
|
+ { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
|
|
+ { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
|
|
+ { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
|
|
+ { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
|
|
+ { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
|
|
+ { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
|
|
+ { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
|
|
+ { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
|
|
+ { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
|
|
+ { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
|
|
+ { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
|
|
+ { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
|
|
+ { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
|
|
+ { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
|
|
+ { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
|
|
+ { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
|
|
+ { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
|
|
+ { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
|
|
+ { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
|
|
+ { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
|
|
+ { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
|
|
+ { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
|
|
+ { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
|
|
+ { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
|
|
+ { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
|
|
+ { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
|
|
+ { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
|
|
+ { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
|
|
+ { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
|
|
+ { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
|
|
+ { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
|
|
+ { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
|
|
+ { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
|
|
+ { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
|
|
+ { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
|
|
+ { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
|
|
+ { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
|
|
+ { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
|
|
+ { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
|
|
+ { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
|
|
+ { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
|
|
+ { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
|
|
+ { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
|
|
+ { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
|
|
+ { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
|
|
+ { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
|
|
+ { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
|
|
+ { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
|
|
+ { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
|
|
+ { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
|
|
+ { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
|
|
+ { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
|
|
+ { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
|
|
+ { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
|
|
+ { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
|
|
+ { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
|
|
+ { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
|
|
+ { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
|
|
+ { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
|
|
+ { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
|
|
+ { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
|
|
+ { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
|
|
+ { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
|
|
+ { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
|
|
+ { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
|
|
+ { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
|
|
+ { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
|
|
+ { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
|
|
+ { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
|
|
+ { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
|
|
+ { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
|
|
+ { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
|
|
+ { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
|
|
+ { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
|
|
+ { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
|
|
+ { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
|
|
+ { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
|
|
+ { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
|
|
+ { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
|
|
+ { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
|
|
+ { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
|
|
+ { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
|
|
+ { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
|
|
+ { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
|
|
+ { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
|
|
+ { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
|
|
+ { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
|
|
+ { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
|
|
+ { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
|
|
+ { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
|
|
+ { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
|
|
+ { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
|
|
+ { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
|
|
+ { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
|
|
+ { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
|
|
+ { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
|
|
+ { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
|
|
+ { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
|
|
+ { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
|
|
+ { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
|
|
+ { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
|
|
+ { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
|
|
+ { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
|
|
+ { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
|
|
+ { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
|
|
+ { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
|
|
+ { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
|
|
+ { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
|
|
+ { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
|
|
+ { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
|
|
+ { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
|
|
+ { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
|
|
+ { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
|
|
+ { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
|
|
+ { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
|
|
+ { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
|
|
+ { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
|
|
+ { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
|
|
+ { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
|
|
+ { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
|
|
+ { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
|
|
+ { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
|
|
+ { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
|
|
+ { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
|
|
+ { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
|
|
+ { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
|
|
+ { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
|
|
+ { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
|
|
+ { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
|
|
+ { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
|
|
+ { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
|
|
+ { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
|
|
+ { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
|
|
+ { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
|
|
+ { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
|
|
+ { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
|
|
+ { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
|
|
+ { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
|
|
+ { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
|
|
+ { 0x2000b, 0x4b }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
|
|
+ { 0x2000c, 0x96 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
|
|
+ { 0x2000d, 0x5dc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
|
|
+ { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
|
|
+ { 0x12000b, 0xc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
|
|
+ { 0x12000c, 0x19 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
|
|
+ { 0x12000d, 0xfa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
|
|
+ { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
|
|
+ { 0x22000b, 0x3 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
|
|
+ { 0x22000c, 0x6 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
|
|
+ { 0x22000d, 0x3e }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
|
|
+ { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
|
|
+ { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
|
|
+ { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
|
|
+ { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
|
|
+ { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
|
|
+ { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
|
|
+ { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
|
|
+ { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
|
|
+ { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
|
|
+ { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
|
|
+ { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
|
|
+};
|
|
+
|
|
+struct dram_fsp_msg ddr4_dram_fsp_msg[] = {
|
|
+ {
|
|
+ /* P0 3000mts 1D */
|
|
+ .drate = 2400,
|
|
+ .fw_type = FW_1D_IMAGE,
|
|
+ .fsp_cfg = ddr4_fsp0_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_cfg),
|
|
+ },
|
|
+ {
|
|
+ /* P1 400mts 1D */
|
|
+ .drate = 400,
|
|
+ .fw_type = FW_1D_IMAGE,
|
|
+ .fsp_cfg = ddr4_fsp1_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp1_cfg),
|
|
+ },
|
|
+ {
|
|
+ /* P2 100mts 1D */
|
|
+ .drate = 100,
|
|
+ .fw_type = FW_1D_IMAGE,
|
|
+ .fsp_cfg = ddr4_fsp2_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp2_cfg),
|
|
+ },
|
|
+ {
|
|
+ /* P0 3000mts 2D */
|
|
+ .drate = 2400,
|
|
+ .fw_type = FW_2D_IMAGE,
|
|
+ .fsp_cfg = ddr4_fsp0_2d_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_2d_cfg),
|
|
+ },
|
|
+};
|
|
+
|
|
+/* ddr4 timing config params on EVK board */
|
|
+struct dram_timing_info dram_timing = {
|
|
+ .ddrc_cfg = ddr4_ddrc_cfg,
|
|
+ .ddrc_cfg_num = ARRAY_SIZE(ddr4_ddrc_cfg),
|
|
+ .ddrphy_cfg = ddr4_ddrphy_cfg,
|
|
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr4_ddrphy_cfg),
|
|
+ .fsp_msg = ddr4_dram_fsp_msg,
|
|
+ .fsp_msg_num = ARRAY_SIZE(ddr4_dram_fsp_msg),
|
|
+ .ddrphy_trained_csr = ddr4_ddrphy_trained_csr,
|
|
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr4_ddrphy_trained_csr),
|
|
+ .ddrphy_pie = ddr4_phy_pie,
|
|
+ .ddrphy_pie_num = ARRAY_SIZE(ddr4_phy_pie),
|
|
+};
|
|
Index: u-boot-imx/board/tiesse/tgr/lpddr4_timing.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/board/tiesse/tgr/lpddr4_timing.c
|
|
@@ -0,0 +1,1855 @@
|
|
+/*
|
|
+ * Copyright 2018-2019 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ *
|
|
+ * Generated code from MX8M_DDR_tool
|
|
+ */
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <asm/arch/imx8m_ddr.h>
|
|
+
|
|
+struct dram_cfg_param ddr_ddrc_cfg[] = {
|
|
+ /* Initialize DDRC registers */
|
|
+ { 0x3d400304, 0x1 },
|
|
+ { 0x3d400030, 0x1 },
|
|
+ { 0x3d400000, 0xa1080020 },
|
|
+ { 0x3d400020, 0x223 },
|
|
+ { 0x3d400024, 0x16e3600 },
|
|
+ { 0x3d400064, 0x5b00d2 },
|
|
+ { 0x3d4000d0, 0xc00305ba },
|
|
+ { 0x3d4000d4, 0x940000 },
|
|
+ { 0x3d4000dc, 0xd4002d },
|
|
+ { 0x3d4000e0, 0x310000 },
|
|
+ { 0x3d4000e8, 0x66004d },
|
|
+ { 0x3d4000ec, 0x16004d },
|
|
+ { 0x3d400100, 0x191e1920 },
|
|
+ { 0x3d400104, 0x60630 },
|
|
+ { 0x3d40010c, 0xb0b000 },
|
|
+ { 0x3d400110, 0xe04080e },
|
|
+ { 0x3d400114, 0x2040c0c },
|
|
+ { 0x3d400118, 0x1010007 },
|
|
+ { 0x3d40011c, 0x401 },
|
|
+ { 0x3d400130, 0x20600 },
|
|
+ { 0x3d400134, 0xc100002 },
|
|
+ { 0x3d400138, 0xd8 },
|
|
+ { 0x3d400144, 0x96004b },
|
|
+ { 0x3d400180, 0x2ee0017 },
|
|
+ { 0x3d400184, 0x2605b8e },
|
|
+ { 0x3d400188, 0x0 },
|
|
+ { 0x3d400190, 0x497820a },
|
|
+ { 0x3d400194, 0x80303 },
|
|
+ { 0x3d4001b4, 0x170a },
|
|
+ { 0x3d4001a0, 0xe0400018 },
|
|
+ { 0x3d4001a4, 0xdf00e4 },
|
|
+ { 0x3d4001a8, 0x80000000 },
|
|
+ { 0x3d4001b0, 0x11 },
|
|
+ { 0x3d4001c0, 0x1 },
|
|
+ { 0x3d4001c4, 0x0 },
|
|
+ { 0x3d4000f4, 0xc99 },
|
|
+ { 0x3d400108, 0x70e1617 },
|
|
+ { 0x3d400200, 0x1f },
|
|
+ { 0x3d40020c, 0x0 },
|
|
+ { 0x3d400210, 0x1f1f },
|
|
+ { 0x3d400204, 0x80808 },
|
|
+ { 0x3d400214, 0x7070707 },
|
|
+ { 0x3d400218, 0x7070707 },
|
|
+
|
|
+ /* performance setting */
|
|
+ { 0x3d400250, 0x29001701 },
|
|
+ { 0x3d400254, 0x2c },
|
|
+ { 0x3d40025c, 0x4000030 },
|
|
+ { 0x3d400264, 0x900093e7 },
|
|
+ { 0x3d40026c, 0x2005574 },
|
|
+ { 0x3d400400, 0x111 },
|
|
+ { 0x3d400408, 0x72ff },
|
|
+ { 0x3d400494, 0x2100e07 },
|
|
+ { 0x3d400498, 0x620096 },
|
|
+ { 0x3d40049c, 0x1100e07 },
|
|
+ { 0x3d4004a0, 0xc8012c },
|
|
+
|
|
+ /* P1: 400mts */
|
|
+ { 0x3d402020, 0x21 },
|
|
+ { 0x3d402024, 0x30d400 },
|
|
+ { 0x3d402050, 0x20d040 },
|
|
+ { 0x3d402064, 0xc001c },
|
|
+ { 0x3d4020dc, 0x840000 },
|
|
+ { 0x3d4020e0, 0x310000 },
|
|
+ { 0x3d4020e8, 0x66004d },
|
|
+ { 0x3d4020ec, 0x16004d },
|
|
+ { 0x3d402100, 0xa040305 },
|
|
+ { 0x3d402104, 0x30407 },
|
|
+ { 0x3d402108, 0x203060b },
|
|
+ { 0x3d40210c, 0x505000 },
|
|
+ { 0x3d402110, 0x2040202 },
|
|
+ { 0x3d402114, 0x2030202 },
|
|
+ { 0x3d402118, 0x1010004 },
|
|
+ { 0x3d40211c, 0x301 },
|
|
+ { 0x3d402130, 0x20300 },
|
|
+ { 0x3d402134, 0xa100002 },
|
|
+ { 0x3d402138, 0x1d },
|
|
+ { 0x3d402144, 0x14000a },
|
|
+ { 0x3d402180, 0x640004 },
|
|
+ { 0x3d402190, 0x3818200 },
|
|
+ { 0x3d402194, 0x80303 },
|
|
+ { 0x3d4021b4, 0x100 },
|
|
+
|
|
+ /* p2: 100mts */
|
|
+ { 0x3d403020, 0x21 },
|
|
+ { 0x3d403024, 0xc3500 },
|
|
+ { 0x3d403050, 0x20d040 },
|
|
+ { 0x3d403064, 0x30007 },
|
|
+ { 0x3d4030dc, 0x840000 },
|
|
+ { 0x3d4030e0, 0x310000 },
|
|
+ { 0x3d4030e8, 0x66004d },
|
|
+ { 0x3d4030ec, 0x16004d },
|
|
+ { 0x3d403100, 0xa010102 },
|
|
+ { 0x3d403104, 0x30404 },
|
|
+ { 0x3d403108, 0x203060b },
|
|
+ { 0x3d40310c, 0x505000 },
|
|
+ { 0x3d403110, 0x2040202 },
|
|
+ { 0x3d403114, 0x2030202 },
|
|
+ { 0x3d403118, 0x1010004 },
|
|
+ { 0x3d40311c, 0x301 },
|
|
+ { 0x3d403130, 0x20300 },
|
|
+ { 0x3d403134, 0xa100002 },
|
|
+ { 0x3d403138, 0x8 },
|
|
+ { 0x3d403144, 0x50003 },
|
|
+ { 0x3d403180, 0x190004 },
|
|
+ { 0x3d403190, 0x3818200 },
|
|
+ { 0x3d403194, 0x80303 },
|
|
+ { 0x3d4031b4, 0x100 },
|
|
+
|
|
+ /* default boot point */
|
|
+ { 0x3d400028, 0x0 },
|
|
+};
|
|
+
|
|
+/* PHY Initialize Configuration */
|
|
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
|
|
+ { 0x100a0, 0x0 },
|
|
+ { 0x100a1, 0x1 },
|
|
+ { 0x100a2, 0x2 },
|
|
+ { 0x100a3, 0x3 },
|
|
+ { 0x100a4, 0x4 },
|
|
+ { 0x100a5, 0x5 },
|
|
+ { 0x100a6, 0x6 },
|
|
+ { 0x100a7, 0x7 },
|
|
+ { 0x110a0, 0x0 },
|
|
+ { 0x110a1, 0x1 },
|
|
+ { 0x110a2, 0x3 },
|
|
+ { 0x110a3, 0x4 },
|
|
+ { 0x110a4, 0x5 },
|
|
+ { 0x110a5, 0x2 },
|
|
+ { 0x110a6, 0x7 },
|
|
+ { 0x110a7, 0x6 },
|
|
+ { 0x120a0, 0x0 },
|
|
+ { 0x120a1, 0x1 },
|
|
+ { 0x120a2, 0x3 },
|
|
+ { 0x120a3, 0x2 },
|
|
+ { 0x120a4, 0x5 },
|
|
+ { 0x120a5, 0x4 },
|
|
+ { 0x120a6, 0x7 },
|
|
+ { 0x120a7, 0x6 },
|
|
+ { 0x130a0, 0x0 },
|
|
+ { 0x130a1, 0x1 },
|
|
+ { 0x130a2, 0x2 },
|
|
+ { 0x130a3, 0x3 },
|
|
+ { 0x130a4, 0x4 },
|
|
+ { 0x130a5, 0x5 },
|
|
+ { 0x130a6, 0x6 },
|
|
+ { 0x130a7, 0x7 },
|
|
+ { 0x1005f, 0x1ff },
|
|
+ { 0x1015f, 0x1ff },
|
|
+ { 0x1105f, 0x1ff },
|
|
+ { 0x1115f, 0x1ff },
|
|
+ { 0x1205f, 0x1ff },
|
|
+ { 0x1215f, 0x1ff },
|
|
+ { 0x1305f, 0x1ff },
|
|
+ { 0x1315f, 0x1ff },
|
|
+ { 0x11005f, 0x1ff },
|
|
+ { 0x11015f, 0x1ff },
|
|
+ { 0x11105f, 0x1ff },
|
|
+ { 0x11115f, 0x1ff },
|
|
+ { 0x11205f, 0x1ff },
|
|
+ { 0x11215f, 0x1ff },
|
|
+ { 0x11305f, 0x1ff },
|
|
+ { 0x11315f, 0x1ff },
|
|
+ { 0x21005f, 0x1ff },
|
|
+ { 0x21015f, 0x1ff },
|
|
+ { 0x21105f, 0x1ff },
|
|
+ { 0x21115f, 0x1ff },
|
|
+ { 0x21205f, 0x1ff },
|
|
+ { 0x21215f, 0x1ff },
|
|
+ { 0x21305f, 0x1ff },
|
|
+ { 0x21315f, 0x1ff },
|
|
+ { 0x55, 0x1ff },
|
|
+ { 0x1055, 0x1ff },
|
|
+ { 0x2055, 0x1ff },
|
|
+ { 0x3055, 0x1ff },
|
|
+ { 0x4055, 0x1ff },
|
|
+ { 0x5055, 0x1ff },
|
|
+ { 0x6055, 0x1ff },
|
|
+ { 0x7055, 0x1ff },
|
|
+ { 0x8055, 0x1ff },
|
|
+ { 0x9055, 0x1ff },
|
|
+ { 0x200c5, 0x19 },
|
|
+ { 0x1200c5, 0x7 },
|
|
+ { 0x2200c5, 0x7 },
|
|
+ { 0x2002e, 0x2 },
|
|
+ { 0x12002e, 0x2 },
|
|
+ { 0x22002e, 0x2 },
|
|
+ { 0x90204, 0x0 },
|
|
+ { 0x190204, 0x0 },
|
|
+ { 0x290204, 0x0 },
|
|
+ { 0x20024, 0x1ab },
|
|
+ { 0x2003a, 0x0 },
|
|
+ { 0x120024, 0x1ab },
|
|
+ { 0x2003a, 0x0 },
|
|
+ { 0x220024, 0x1ab },
|
|
+ { 0x2003a, 0x0 },
|
|
+ { 0x20056, 0x3 },
|
|
+ { 0x120056, 0xa },
|
|
+ { 0x220056, 0xa },
|
|
+ { 0x1004d, 0xe00 },
|
|
+ { 0x1014d, 0xe00 },
|
|
+ { 0x1104d, 0xe00 },
|
|
+ { 0x1114d, 0xe00 },
|
|
+ { 0x1204d, 0xe00 },
|
|
+ { 0x1214d, 0xe00 },
|
|
+ { 0x1304d, 0xe00 },
|
|
+ { 0x1314d, 0xe00 },
|
|
+ { 0x11004d, 0xe00 },
|
|
+ { 0x11014d, 0xe00 },
|
|
+ { 0x11104d, 0xe00 },
|
|
+ { 0x11114d, 0xe00 },
|
|
+ { 0x11204d, 0xe00 },
|
|
+ { 0x11214d, 0xe00 },
|
|
+ { 0x11304d, 0xe00 },
|
|
+ { 0x11314d, 0xe00 },
|
|
+ { 0x21004d, 0xe00 },
|
|
+ { 0x21014d, 0xe00 },
|
|
+ { 0x21104d, 0xe00 },
|
|
+ { 0x21114d, 0xe00 },
|
|
+ { 0x21204d, 0xe00 },
|
|
+ { 0x21214d, 0xe00 },
|
|
+ { 0x21304d, 0xe00 },
|
|
+ { 0x21314d, 0xe00 },
|
|
+ { 0x10049, 0xeba },
|
|
+ { 0x10149, 0xeba },
|
|
+ { 0x11049, 0xeba },
|
|
+ { 0x11149, 0xeba },
|
|
+ { 0x12049, 0xeba },
|
|
+ { 0x12149, 0xeba },
|
|
+ { 0x13049, 0xeba },
|
|
+ { 0x13149, 0xeba },
|
|
+ { 0x110049, 0xeba },
|
|
+ { 0x110149, 0xeba },
|
|
+ { 0x111049, 0xeba },
|
|
+ { 0x111149, 0xeba },
|
|
+ { 0x112049, 0xeba },
|
|
+ { 0x112149, 0xeba },
|
|
+ { 0x113049, 0xeba },
|
|
+ { 0x113149, 0xeba },
|
|
+ { 0x210049, 0xeba },
|
|
+ { 0x210149, 0xeba },
|
|
+ { 0x211049, 0xeba },
|
|
+ { 0x211149, 0xeba },
|
|
+ { 0x212049, 0xeba },
|
|
+ { 0x212149, 0xeba },
|
|
+ { 0x213049, 0xeba },
|
|
+ { 0x213149, 0xeba },
|
|
+ { 0x43, 0x63 },
|
|
+ { 0x1043, 0x63 },
|
|
+ { 0x2043, 0x63 },
|
|
+ { 0x3043, 0x63 },
|
|
+ { 0x4043, 0x63 },
|
|
+ { 0x5043, 0x63 },
|
|
+ { 0x6043, 0x63 },
|
|
+ { 0x7043, 0x63 },
|
|
+ { 0x8043, 0x63 },
|
|
+ { 0x9043, 0x63 },
|
|
+ { 0x20018, 0x3 },
|
|
+ { 0x20075, 0x4 },
|
|
+ { 0x20050, 0x0 },
|
|
+ { 0x20008, 0x2ee },
|
|
+ { 0x120008, 0x64 },
|
|
+ { 0x220008, 0x19 },
|
|
+ { 0x20088, 0x9 },
|
|
+ { 0x200b2, 0xdc },
|
|
+ { 0x10043, 0x5a1 },
|
|
+ { 0x10143, 0x5a1 },
|
|
+ { 0x11043, 0x5a1 },
|
|
+ { 0x11143, 0x5a1 },
|
|
+ { 0x12043, 0x5a1 },
|
|
+ { 0x12143, 0x5a1 },
|
|
+ { 0x13043, 0x5a1 },
|
|
+ { 0x13143, 0x5a1 },
|
|
+ { 0x1200b2, 0xdc },
|
|
+ { 0x110043, 0x5a1 },
|
|
+ { 0x110143, 0x5a1 },
|
|
+ { 0x111043, 0x5a1 },
|
|
+ { 0x111143, 0x5a1 },
|
|
+ { 0x112043, 0x5a1 },
|
|
+ { 0x112143, 0x5a1 },
|
|
+ { 0x113043, 0x5a1 },
|
|
+ { 0x113143, 0x5a1 },
|
|
+ { 0x2200b2, 0xdc },
|
|
+ { 0x210043, 0x5a1 },
|
|
+ { 0x210143, 0x5a1 },
|
|
+ { 0x211043, 0x5a1 },
|
|
+ { 0x211143, 0x5a1 },
|
|
+ { 0x212043, 0x5a1 },
|
|
+ { 0x212143, 0x5a1 },
|
|
+ { 0x213043, 0x5a1 },
|
|
+ { 0x213143, 0x5a1 },
|
|
+ { 0x200fa, 0x1 },
|
|
+ { 0x1200fa, 0x1 },
|
|
+ { 0x2200fa, 0x1 },
|
|
+ { 0x20019, 0x1 },
|
|
+ { 0x120019, 0x1 },
|
|
+ { 0x220019, 0x1 },
|
|
+ { 0x200f0, 0x660 },
|
|
+ { 0x200f1, 0x0 },
|
|
+ { 0x200f2, 0x4444 },
|
|
+ { 0x200f3, 0x8888 },
|
|
+ { 0x200f4, 0x5665 },
|
|
+ { 0x200f5, 0x0 },
|
|
+ { 0x200f6, 0x0 },
|
|
+ { 0x200f7, 0xf000 },
|
|
+ { 0x20025, 0x0 },
|
|
+ { 0x2002d, 0x0 },
|
|
+ { 0x12002d, 0x0 },
|
|
+ { 0x22002d, 0x0 },
|
|
+ { 0x200c7, 0x21 },
|
|
+ { 0x1200c7, 0x21 },
|
|
+ { 0x2200c7, 0x21 },
|
|
+ { 0x200ca, 0x24 },
|
|
+ { 0x1200ca, 0x24 },
|
|
+ { 0x2200ca, 0x24 },
|
|
+};
|
|
+
|
|
+/* ddr phy trained csr */
|
|
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
|
|
+ { 0x200b2, 0x0 },
|
|
+ { 0x1200b2, 0x0 },
|
|
+ { 0x2200b2, 0x0 },
|
|
+ { 0x200cb, 0x0 },
|
|
+ { 0x10043, 0x0 },
|
|
+ { 0x110043, 0x0 },
|
|
+ { 0x210043, 0x0 },
|
|
+ { 0x10143, 0x0 },
|
|
+ { 0x110143, 0x0 },
|
|
+ { 0x210143, 0x0 },
|
|
+ { 0x11043, 0x0 },
|
|
+ { 0x111043, 0x0 },
|
|
+ { 0x211043, 0x0 },
|
|
+ { 0x11143, 0x0 },
|
|
+ { 0x111143, 0x0 },
|
|
+ { 0x211143, 0x0 },
|
|
+ { 0x12043, 0x0 },
|
|
+ { 0x112043, 0x0 },
|
|
+ { 0x212043, 0x0 },
|
|
+ { 0x12143, 0x0 },
|
|
+ { 0x112143, 0x0 },
|
|
+ { 0x212143, 0x0 },
|
|
+ { 0x13043, 0x0 },
|
|
+ { 0x113043, 0x0 },
|
|
+ { 0x213043, 0x0 },
|
|
+ { 0x13143, 0x0 },
|
|
+ { 0x113143, 0x0 },
|
|
+ { 0x213143, 0x0 },
|
|
+ { 0x80, 0x0 },
|
|
+ { 0x100080, 0x0 },
|
|
+ { 0x200080, 0x0 },
|
|
+ { 0x1080, 0x0 },
|
|
+ { 0x101080, 0x0 },
|
|
+ { 0x201080, 0x0 },
|
|
+ { 0x2080, 0x0 },
|
|
+ { 0x102080, 0x0 },
|
|
+ { 0x202080, 0x0 },
|
|
+ { 0x3080, 0x0 },
|
|
+ { 0x103080, 0x0 },
|
|
+ { 0x203080, 0x0 },
|
|
+ { 0x4080, 0x0 },
|
|
+ { 0x104080, 0x0 },
|
|
+ { 0x204080, 0x0 },
|
|
+ { 0x5080, 0x0 },
|
|
+ { 0x105080, 0x0 },
|
|
+ { 0x205080, 0x0 },
|
|
+ { 0x6080, 0x0 },
|
|
+ { 0x106080, 0x0 },
|
|
+ { 0x206080, 0x0 },
|
|
+ { 0x7080, 0x0 },
|
|
+ { 0x107080, 0x0 },
|
|
+ { 0x207080, 0x0 },
|
|
+ { 0x8080, 0x0 },
|
|
+ { 0x108080, 0x0 },
|
|
+ { 0x208080, 0x0 },
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|
|
+ { 0x2128c1, 0x0 },
|
|
+ { 0x130c1, 0x0 },
|
|
+ { 0x1130c1, 0x0 },
|
|
+ { 0x2130c1, 0x0 },
|
|
+ { 0x131c1, 0x0 },
|
|
+ { 0x1131c1, 0x0 },
|
|
+ { 0x2131c1, 0x0 },
|
|
+ { 0x132c1, 0x0 },
|
|
+ { 0x1132c1, 0x0 },
|
|
+ { 0x2132c1, 0x0 },
|
|
+ { 0x133c1, 0x0 },
|
|
+ { 0x1133c1, 0x0 },
|
|
+ { 0x2133c1, 0x0 },
|
|
+ { 0x134c1, 0x0 },
|
|
+ { 0x1134c1, 0x0 },
|
|
+ { 0x2134c1, 0x0 },
|
|
+ { 0x135c1, 0x0 },
|
|
+ { 0x1135c1, 0x0 },
|
|
+ { 0x2135c1, 0x0 },
|
|
+ { 0x136c1, 0x0 },
|
|
+ { 0x1136c1, 0x0 },
|
|
+ { 0x2136c1, 0x0 },
|
|
+ { 0x137c1, 0x0 },
|
|
+ { 0x1137c1, 0x0 },
|
|
+ { 0x2137c1, 0x0 },
|
|
+ { 0x138c1, 0x0 },
|
|
+ { 0x1138c1, 0x0 },
|
|
+ { 0x2138c1, 0x0 },
|
|
+ { 0x10020, 0x0 },
|
|
+ { 0x110020, 0x0 },
|
|
+ { 0x210020, 0x0 },
|
|
+ { 0x11020, 0x0 },
|
|
+ { 0x111020, 0x0 },
|
|
+ { 0x211020, 0x0 },
|
|
+ { 0x12020, 0x0 },
|
|
+ { 0x112020, 0x0 },
|
|
+ { 0x212020, 0x0 },
|
|
+ { 0x13020, 0x0 },
|
|
+ { 0x113020, 0x0 },
|
|
+ { 0x213020, 0x0 },
|
|
+ { 0x20072, 0x0 },
|
|
+ { 0x20073, 0x0 },
|
|
+ { 0x20074, 0x0 },
|
|
+ { 0x100aa, 0x0 },
|
|
+ { 0x110aa, 0x0 },
|
|
+ { 0x120aa, 0x0 },
|
|
+ { 0x130aa, 0x0 },
|
|
+ { 0x20010, 0x0 },
|
|
+ { 0x120010, 0x0 },
|
|
+ { 0x220010, 0x0 },
|
|
+ { 0x20011, 0x0 },
|
|
+ { 0x120011, 0x0 },
|
|
+ { 0x220011, 0x0 },
|
|
+ { 0x100ae, 0x0 },
|
|
+ { 0x1100ae, 0x0 },
|
|
+ { 0x2100ae, 0x0 },
|
|
+ { 0x100af, 0x0 },
|
|
+ { 0x1100af, 0x0 },
|
|
+ { 0x2100af, 0x0 },
|
|
+ { 0x110ae, 0x0 },
|
|
+ { 0x1110ae, 0x0 },
|
|
+ { 0x2110ae, 0x0 },
|
|
+ { 0x110af, 0x0 },
|
|
+ { 0x1110af, 0x0 },
|
|
+ { 0x2110af, 0x0 },
|
|
+ { 0x120ae, 0x0 },
|
|
+ { 0x1120ae, 0x0 },
|
|
+ { 0x2120ae, 0x0 },
|
|
+ { 0x120af, 0x0 },
|
|
+ { 0x1120af, 0x0 },
|
|
+ { 0x2120af, 0x0 },
|
|
+ { 0x130ae, 0x0 },
|
|
+ { 0x1130ae, 0x0 },
|
|
+ { 0x2130ae, 0x0 },
|
|
+ { 0x130af, 0x0 },
|
|
+ { 0x1130af, 0x0 },
|
|
+ { 0x2130af, 0x0 },
|
|
+ { 0x20020, 0x0 },
|
|
+ { 0x120020, 0x0 },
|
|
+ { 0x220020, 0x0 },
|
|
+ { 0x100a0, 0x0 },
|
|
+ { 0x100a1, 0x0 },
|
|
+ { 0x100a2, 0x0 },
|
|
+ { 0x100a3, 0x0 },
|
|
+ { 0x100a4, 0x0 },
|
|
+ { 0x100a5, 0x0 },
|
|
+ { 0x100a6, 0x0 },
|
|
+ { 0x100a7, 0x0 },
|
|
+ { 0x110a0, 0x0 },
|
|
+ { 0x110a1, 0x0 },
|
|
+ { 0x110a2, 0x0 },
|
|
+ { 0x110a3, 0x0 },
|
|
+ { 0x110a4, 0x0 },
|
|
+ { 0x110a5, 0x0 },
|
|
+ { 0x110a6, 0x0 },
|
|
+ { 0x110a7, 0x0 },
|
|
+ { 0x120a0, 0x0 },
|
|
+ { 0x120a1, 0x0 },
|
|
+ { 0x120a2, 0x0 },
|
|
+ { 0x120a3, 0x0 },
|
|
+ { 0x120a4, 0x0 },
|
|
+ { 0x120a5, 0x0 },
|
|
+ { 0x120a6, 0x0 },
|
|
+ { 0x120a7, 0x0 },
|
|
+ { 0x130a0, 0x0 },
|
|
+ { 0x130a1, 0x0 },
|
|
+ { 0x130a2, 0x0 },
|
|
+ { 0x130a3, 0x0 },
|
|
+ { 0x130a4, 0x0 },
|
|
+ { 0x130a5, 0x0 },
|
|
+ { 0x130a6, 0x0 },
|
|
+ { 0x130a7, 0x0 },
|
|
+ { 0x2007c, 0x0 },
|
|
+ { 0x12007c, 0x0 },
|
|
+ { 0x22007c, 0x0 },
|
|
+ { 0x2007d, 0x0 },
|
|
+ { 0x12007d, 0x0 },
|
|
+ { 0x22007d, 0x0 },
|
|
+ { 0x400fd, 0x0 },
|
|
+ { 0x400c0, 0x0 },
|
|
+ { 0x90201, 0x0 },
|
|
+ { 0x190201, 0x0 },
|
|
+ { 0x290201, 0x0 },
|
|
+ { 0x90202, 0x0 },
|
|
+ { 0x190202, 0x0 },
|
|
+ { 0x290202, 0x0 },
|
|
+ { 0x90203, 0x0 },
|
|
+ { 0x190203, 0x0 },
|
|
+ { 0x290203, 0x0 },
|
|
+ { 0x90204, 0x0 },
|
|
+ { 0x190204, 0x0 },
|
|
+ { 0x290204, 0x0 },
|
|
+ { 0x90205, 0x0 },
|
|
+ { 0x190205, 0x0 },
|
|
+ { 0x290205, 0x0 },
|
|
+ { 0x90206, 0x0 },
|
|
+ { 0x190206, 0x0 },
|
|
+ { 0x290206, 0x0 },
|
|
+ { 0x90207, 0x0 },
|
|
+ { 0x190207, 0x0 },
|
|
+ { 0x290207, 0x0 },
|
|
+ { 0x90208, 0x0 },
|
|
+ { 0x190208, 0x0 },
|
|
+ { 0x290208, 0x0 },
|
|
+ { 0x10062, 0x0 },
|
|
+ { 0x10162, 0x0 },
|
|
+ { 0x10262, 0x0 },
|
|
+ { 0x10362, 0x0 },
|
|
+ { 0x10462, 0x0 },
|
|
+ { 0x10562, 0x0 },
|
|
+ { 0x10662, 0x0 },
|
|
+ { 0x10762, 0x0 },
|
|
+ { 0x10862, 0x0 },
|
|
+ { 0x11062, 0x0 },
|
|
+ { 0x11162, 0x0 },
|
|
+ { 0x11262, 0x0 },
|
|
+ { 0x11362, 0x0 },
|
|
+ { 0x11462, 0x0 },
|
|
+ { 0x11562, 0x0 },
|
|
+ { 0x11662, 0x0 },
|
|
+ { 0x11762, 0x0 },
|
|
+ { 0x11862, 0x0 },
|
|
+ { 0x12062, 0x0 },
|
|
+ { 0x12162, 0x0 },
|
|
+ { 0x12262, 0x0 },
|
|
+ { 0x12362, 0x0 },
|
|
+ { 0x12462, 0x0 },
|
|
+ { 0x12562, 0x0 },
|
|
+ { 0x12662, 0x0 },
|
|
+ { 0x12762, 0x0 },
|
|
+ { 0x12862, 0x0 },
|
|
+ { 0x13062, 0x0 },
|
|
+ { 0x13162, 0x0 },
|
|
+ { 0x13262, 0x0 },
|
|
+ { 0x13362, 0x0 },
|
|
+ { 0x13462, 0x0 },
|
|
+ { 0x13562, 0x0 },
|
|
+ { 0x13662, 0x0 },
|
|
+ { 0x13762, 0x0 },
|
|
+ { 0x13862, 0x0 },
|
|
+ { 0x20077, 0x0 },
|
|
+ { 0x10001, 0x0 },
|
|
+ { 0x11001, 0x0 },
|
|
+ { 0x12001, 0x0 },
|
|
+ { 0x13001, 0x0 },
|
|
+ { 0x10040, 0x0 },
|
|
+ { 0x10140, 0x0 },
|
|
+ { 0x10240, 0x0 },
|
|
+ { 0x10340, 0x0 },
|
|
+ { 0x10440, 0x0 },
|
|
+ { 0x10540, 0x0 },
|
|
+ { 0x10640, 0x0 },
|
|
+ { 0x10740, 0x0 },
|
|
+ { 0x10840, 0x0 },
|
|
+ { 0x10030, 0x0 },
|
|
+ { 0x10130, 0x0 },
|
|
+ { 0x10230, 0x0 },
|
|
+ { 0x10330, 0x0 },
|
|
+ { 0x10430, 0x0 },
|
|
+ { 0x10530, 0x0 },
|
|
+ { 0x10630, 0x0 },
|
|
+ { 0x10730, 0x0 },
|
|
+ { 0x10830, 0x0 },
|
|
+ { 0x11040, 0x0 },
|
|
+ { 0x11140, 0x0 },
|
|
+ { 0x11240, 0x0 },
|
|
+ { 0x11340, 0x0 },
|
|
+ { 0x11440, 0x0 },
|
|
+ { 0x11540, 0x0 },
|
|
+ { 0x11640, 0x0 },
|
|
+ { 0x11740, 0x0 },
|
|
+ { 0x11840, 0x0 },
|
|
+ { 0x11030, 0x0 },
|
|
+ { 0x11130, 0x0 },
|
|
+ { 0x11230, 0x0 },
|
|
+ { 0x11330, 0x0 },
|
|
+ { 0x11430, 0x0 },
|
|
+ { 0x11530, 0x0 },
|
|
+ { 0x11630, 0x0 },
|
|
+ { 0x11730, 0x0 },
|
|
+ { 0x11830, 0x0 },
|
|
+ { 0x12040, 0x0 },
|
|
+ { 0x12140, 0x0 },
|
|
+ { 0x12240, 0x0 },
|
|
+ { 0x12340, 0x0 },
|
|
+ { 0x12440, 0x0 },
|
|
+ { 0x12540, 0x0 },
|
|
+ { 0x12640, 0x0 },
|
|
+ { 0x12740, 0x0 },
|
|
+ { 0x12840, 0x0 },
|
|
+ { 0x12030, 0x0 },
|
|
+ { 0x12130, 0x0 },
|
|
+ { 0x12230, 0x0 },
|
|
+ { 0x12330, 0x0 },
|
|
+ { 0x12430, 0x0 },
|
|
+ { 0x12530, 0x0 },
|
|
+ { 0x12630, 0x0 },
|
|
+ { 0x12730, 0x0 },
|
|
+ { 0x12830, 0x0 },
|
|
+ { 0x13040, 0x0 },
|
|
+ { 0x13140, 0x0 },
|
|
+ { 0x13240, 0x0 },
|
|
+ { 0x13340, 0x0 },
|
|
+ { 0x13440, 0x0 },
|
|
+ { 0x13540, 0x0 },
|
|
+ { 0x13640, 0x0 },
|
|
+ { 0x13740, 0x0 },
|
|
+ { 0x13840, 0x0 },
|
|
+ { 0x13030, 0x0 },
|
|
+ { 0x13130, 0x0 },
|
|
+ { 0x13230, 0x0 },
|
|
+ { 0x13330, 0x0 },
|
|
+ { 0x13430, 0x0 },
|
|
+ { 0x13530, 0x0 },
|
|
+ { 0x13630, 0x0 },
|
|
+ { 0x13730, 0x0 },
|
|
+ { 0x13830, 0x0 },
|
|
+};
|
|
+/* P0 message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr_fsp0_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54003, 0xbb8 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x2228 },
|
|
+ { 0x54006, 0x11 },
|
|
+ { 0x54008, 0x131f },
|
|
+ { 0x54009, 0xc8 },
|
|
+ { 0x5400b, 0x2 },
|
|
+ { 0x5400d, 0x100 },
|
|
+ { 0x54012, 0x110 },
|
|
+ { 0x54019, 0x2dd4 },
|
|
+ { 0x5401a, 0x31 },
|
|
+ { 0x5401b, 0x4d66 },
|
|
+ { 0x5401c, 0x4d00 },
|
|
+ { 0x5401e, 0x16 },
|
|
+ { 0x5401f, 0x2dd4 },
|
|
+ { 0x54020, 0x31 },
|
|
+ { 0x54021, 0x4d66 },
|
|
+ { 0x54022, 0x4d00 },
|
|
+ { 0x54024, 0x16 },
|
|
+ { 0x5402b, 0x1000 },
|
|
+ { 0x5402c, 0x1 },
|
|
+ { 0x54032, 0xd400 },
|
|
+ { 0x54033, 0x312d },
|
|
+ { 0x54034, 0x6600 },
|
|
+ { 0x54035, 0x4d },
|
|
+ { 0x54036, 0x4d },
|
|
+ { 0x54037, 0x1600 },
|
|
+ { 0x54038, 0xd400 },
|
|
+ { 0x54039, 0x312d },
|
|
+ { 0x5403a, 0x6600 },
|
|
+ { 0x5403b, 0x4d },
|
|
+ { 0x5403c, 0x4d },
|
|
+ { 0x5403d, 0x1600 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+
|
|
+/* P1 message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr_fsp1_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54002, 0x101 },
|
|
+ { 0x54003, 0x190 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x2228 },
|
|
+ { 0x54006, 0x11 },
|
|
+ { 0x54008, 0x121f },
|
|
+ { 0x54009, 0xc8 },
|
|
+ { 0x5400b, 0x2 },
|
|
+ { 0x5400d, 0x100 },
|
|
+ { 0x54012, 0x110 },
|
|
+ { 0x54019, 0x84 },
|
|
+ { 0x5401a, 0x31 },
|
|
+ { 0x5401b, 0x4d66 },
|
|
+ { 0x5401c, 0x4d00 },
|
|
+ { 0x5401e, 0x16 },
|
|
+ { 0x5401f, 0x84 },
|
|
+ { 0x54020, 0x31 },
|
|
+ { 0x54021, 0x4d66 },
|
|
+ { 0x54022, 0x4d00 },
|
|
+ { 0x54024, 0x16 },
|
|
+ { 0x5402b, 0x1000 },
|
|
+ { 0x5402c, 0x1 },
|
|
+ { 0x54032, 0x8400 },
|
|
+ { 0x54033, 0x3100 },
|
|
+ { 0x54034, 0x6600 },
|
|
+ { 0x54035, 0x4d },
|
|
+ { 0x54036, 0x4d },
|
|
+ { 0x54037, 0x1600 },
|
|
+ { 0x54038, 0x8400 },
|
|
+ { 0x54039, 0x3100 },
|
|
+ { 0x5403a, 0x6600 },
|
|
+ { 0x5403b, 0x4d },
|
|
+ { 0x5403c, 0x4d },
|
|
+ { 0x5403d, 0x1600 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+
|
|
+/* P2 message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr_fsp2_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54002, 0x102 },
|
|
+ { 0x54003, 0x64 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x2228 },
|
|
+ { 0x54006, 0x11 },
|
|
+ { 0x54008, 0x121f },
|
|
+ { 0x54009, 0xc8 },
|
|
+ { 0x5400b, 0x2 },
|
|
+ { 0x5400d, 0x100 },
|
|
+ { 0x54012, 0x110 },
|
|
+ { 0x54019, 0x84 },
|
|
+ { 0x5401a, 0x31 },
|
|
+ { 0x5401b, 0x4d66 },
|
|
+ { 0x5401c, 0x4d00 },
|
|
+ { 0x5401e, 0x16 },
|
|
+ { 0x5401f, 0x84 },
|
|
+ { 0x54020, 0x31 },
|
|
+ { 0x54021, 0x4d66 },
|
|
+ { 0x54022, 0x4d00 },
|
|
+ { 0x54024, 0x16 },
|
|
+ { 0x5402b, 0x1000 },
|
|
+ { 0x5402c, 0x1 },
|
|
+ { 0x54032, 0x8400 },
|
|
+ { 0x54033, 0x3100 },
|
|
+ { 0x54034, 0x6600 },
|
|
+ { 0x54035, 0x4d },
|
|
+ { 0x54036, 0x4d },
|
|
+ { 0x54037, 0x1600 },
|
|
+ { 0x54038, 0x8400 },
|
|
+ { 0x54039, 0x3100 },
|
|
+ { 0x5403a, 0x6600 },
|
|
+ { 0x5403b, 0x4d },
|
|
+ { 0x5403c, 0x4d },
|
|
+ { 0x5403d, 0x1600 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+
|
|
+/* P0 2D message block paremeter for training firmware */
|
|
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
|
|
+ { 0xd0000, 0x0 },
|
|
+ { 0x54003, 0xbb8 },
|
|
+ { 0x54004, 0x2 },
|
|
+ { 0x54005, 0x2228 },
|
|
+ { 0x54006, 0x11 },
|
|
+ { 0x54008, 0x61 },
|
|
+ { 0x54009, 0xc8 },
|
|
+ { 0x5400b, 0x2 },
|
|
+ { 0x5400f, 0x100 },
|
|
+ { 0x54010, 0x1f7f },
|
|
+ { 0x54012, 0x110 },
|
|
+ { 0x54019, 0x2dd4 },
|
|
+ { 0x5401a, 0x31 },
|
|
+ { 0x5401b, 0x4d66 },
|
|
+ { 0x5401c, 0x4d00 },
|
|
+ { 0x5401e, 0x16 },
|
|
+ { 0x5401f, 0x2dd4 },
|
|
+ { 0x54020, 0x31 },
|
|
+ { 0x54021, 0x4d66 },
|
|
+ { 0x54022, 0x4d00 },
|
|
+ { 0x54024, 0x16 },
|
|
+ { 0x5402b, 0x1000 },
|
|
+ { 0x5402c, 0x1 },
|
|
+ { 0x54032, 0xd400 },
|
|
+ { 0x54033, 0x312d },
|
|
+ { 0x54034, 0x6600 },
|
|
+ { 0x54035, 0x4d },
|
|
+ { 0x54036, 0x4d },
|
|
+ { 0x54037, 0x1600 },
|
|
+ { 0x54038, 0xd400 },
|
|
+ { 0x54039, 0x312d },
|
|
+ { 0x5403a, 0x6600 },
|
|
+ { 0x5403b, 0x4d },
|
|
+ { 0x5403c, 0x4d },
|
|
+ { 0x5403d, 0x1600 },
|
|
+ { 0xd0000, 0x1 },
|
|
+};
|
|
+
|
|
+/* DRAM PHY init engine image */
|
|
+struct dram_cfg_param ddr_phy_pie[] = {
|
|
+ { 0xd0000, 0x0 },
|
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+ { 0x90000, 0x10 },
|
|
+ { 0x90001, 0x400 },
|
|
+ { 0x90002, 0x10e },
|
|
+ { 0x90003, 0x0 },
|
|
+ { 0x90004, 0x0 },
|
|
+ { 0x90005, 0x8 },
|
|
+ { 0x90029, 0xb },
|
|
+ { 0x9002a, 0x480 },
|
|
+ { 0x9002b, 0x109 },
|
|
+ { 0x9002c, 0x8 },
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|
+ { 0x9002d, 0x448 },
|
|
+ { 0x9002e, 0x139 },
|
|
+ { 0x9002f, 0x8 },
|
|
+ { 0x90030, 0x478 },
|
|
+ { 0x90031, 0x109 },
|
|
+ { 0x90032, 0x0 },
|
|
+ { 0x90033, 0xe8 },
|
|
+ { 0x90034, 0x109 },
|
|
+ { 0x90035, 0x2 },
|
|
+ { 0x90036, 0x10 },
|
|
+ { 0x90037, 0x139 },
|
|
+ { 0x90038, 0xf },
|
|
+ { 0x90039, 0x7c0 },
|
|
+ { 0x9003a, 0x139 },
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|
+ { 0x9003b, 0x44 },
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|
+ { 0x9003c, 0x630 },
|
|
+ { 0x9003d, 0x159 },
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|
+ { 0x9003e, 0x14f },
|
|
+ { 0x9003f, 0x630 },
|
|
+ { 0x90040, 0x159 },
|
|
+ { 0x90041, 0x47 },
|
|
+ { 0x90042, 0x630 },
|
|
+ { 0x90043, 0x149 },
|
|
+ { 0x90044, 0x4f },
|
|
+ { 0x90045, 0x630 },
|
|
+ { 0x90046, 0x179 },
|
|
+ { 0x90047, 0x8 },
|
|
+ { 0x90048, 0xe0 },
|
|
+ { 0x90049, 0x109 },
|
|
+ { 0x9004a, 0x0 },
|
|
+ { 0x9004b, 0x7c8 },
|
|
+ { 0x9004c, 0x109 },
|
|
+ { 0x9004d, 0x0 },
|
|
+ { 0x9004e, 0x1 },
|
|
+ { 0x9004f, 0x8 },
|
|
+ { 0x90050, 0x0 },
|
|
+ { 0x90051, 0x45a },
|
|
+ { 0x90052, 0x9 },
|
|
+ { 0x90053, 0x0 },
|
|
+ { 0x90054, 0x448 },
|
|
+ { 0x90055, 0x109 },
|
|
+ { 0x90056, 0x40 },
|
|
+ { 0x90057, 0x630 },
|
|
+ { 0x90058, 0x179 },
|
|
+ { 0x90059, 0x1 },
|
|
+ { 0x9005a, 0x618 },
|
|
+ { 0x9005b, 0x109 },
|
|
+ { 0x9005c, 0x40c0 },
|
|
+ { 0x9005d, 0x630 },
|
|
+ { 0x9005e, 0x149 },
|
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+ { 0x9005f, 0x8 },
|
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+ { 0x90060, 0x4 },
|
|
+ { 0x90061, 0x48 },
|
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+ { 0x90062, 0x4040 },
|
|
+ { 0x90063, 0x630 },
|
|
+ { 0x90064, 0x149 },
|
|
+ { 0x90065, 0x0 },
|
|
+ { 0x90066, 0x4 },
|
|
+ { 0x90067, 0x48 },
|
|
+ { 0x90068, 0x40 },
|
|
+ { 0x90069, 0x630 },
|
|
+ { 0x9006a, 0x149 },
|
|
+ { 0x9006b, 0x10 },
|
|
+ { 0x9006c, 0x4 },
|
|
+ { 0x9006d, 0x18 },
|
|
+ { 0x9006e, 0x0 },
|
|
+ { 0x9006f, 0x4 },
|
|
+ { 0x90070, 0x78 },
|
|
+ { 0x90071, 0x549 },
|
|
+ { 0x90072, 0x630 },
|
|
+ { 0x90073, 0x159 },
|
|
+ { 0x90074, 0xd49 },
|
|
+ { 0x90075, 0x630 },
|
|
+ { 0x90076, 0x159 },
|
|
+ { 0x90077, 0x94a },
|
|
+ { 0x90078, 0x630 },
|
|
+ { 0x90079, 0x159 },
|
|
+ { 0x9007a, 0x441 },
|
|
+ { 0x9007b, 0x630 },
|
|
+ { 0x9007c, 0x149 },
|
|
+ { 0x9007d, 0x42 },
|
|
+ { 0x9007e, 0x630 },
|
|
+ { 0x9007f, 0x149 },
|
|
+ { 0x90080, 0x1 },
|
|
+ { 0x90081, 0x630 },
|
|
+ { 0x90082, 0x149 },
|
|
+ { 0x90083, 0x0 },
|
|
+ { 0x90084, 0xe0 },
|
|
+ { 0x90085, 0x109 },
|
|
+ { 0x90086, 0xa },
|
|
+ { 0x90087, 0x10 },
|
|
+ { 0x90088, 0x109 },
|
|
+ { 0x90089, 0x9 },
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|
+ { 0x9008a, 0x3c0 },
|
|
+ { 0x9008b, 0x149 },
|
|
+ { 0x9008c, 0x9 },
|
|
+ { 0x9008d, 0x3c0 },
|
|
+ { 0x9008e, 0x159 },
|
|
+ { 0x9008f, 0x18 },
|
|
+ { 0x90090, 0x10 },
|
|
+ { 0x90091, 0x109 },
|
|
+ { 0x90092, 0x0 },
|
|
+ { 0x90093, 0x3c0 },
|
|
+ { 0x90094, 0x109 },
|
|
+ { 0x90095, 0x18 },
|
|
+ { 0x90096, 0x4 },
|
|
+ { 0x90097, 0x48 },
|
|
+ { 0x90098, 0x18 },
|
|
+ { 0x90099, 0x4 },
|
|
+ { 0x9009a, 0x58 },
|
|
+ { 0x9009b, 0xa },
|
|
+ { 0x9009c, 0x10 },
|
|
+ { 0x9009d, 0x109 },
|
|
+ { 0x9009e, 0x2 },
|
|
+ { 0x9009f, 0x10 },
|
|
+ { 0x900a0, 0x109 },
|
|
+ { 0x900a1, 0x5 },
|
|
+ { 0x900a2, 0x7c0 },
|
|
+ { 0x900a3, 0x109 },
|
|
+ { 0x900a4, 0x10 },
|
|
+ { 0x900a5, 0x10 },
|
|
+ { 0x900a6, 0x109 },
|
|
+ { 0x40000, 0x811 },
|
|
+ { 0x40020, 0x880 },
|
|
+ { 0x40040, 0x0 },
|
|
+ { 0x40060, 0x0 },
|
|
+ { 0x40001, 0x4008 },
|
|
+ { 0x40021, 0x83 },
|
|
+ { 0x40041, 0x4f },
|
|
+ { 0x40061, 0x0 },
|
|
+ { 0x40002, 0x4040 },
|
|
+ { 0x40022, 0x83 },
|
|
+ { 0x40042, 0x51 },
|
|
+ { 0x40062, 0x0 },
|
|
+ { 0x40003, 0x811 },
|
|
+ { 0x40023, 0x880 },
|
|
+ { 0x40043, 0x0 },
|
|
+ { 0x40063, 0x0 },
|
|
+ { 0x40004, 0x720 },
|
|
+ { 0x40024, 0xf },
|
|
+ { 0x40044, 0x1740 },
|
|
+ { 0x40064, 0x0 },
|
|
+ { 0x40005, 0x16 },
|
|
+ { 0x40025, 0x83 },
|
|
+ { 0x40045, 0x4b },
|
|
+ { 0x40065, 0x0 },
|
|
+ { 0x40006, 0x716 },
|
|
+ { 0x40026, 0xf },
|
|
+ { 0x40046, 0x2001 },
|
|
+ { 0x40066, 0x0 },
|
|
+ { 0x40007, 0x716 },
|
|
+ { 0x40027, 0xf },
|
|
+ { 0x40047, 0x2800 },
|
|
+ { 0x40067, 0x0 },
|
|
+ { 0x40008, 0x716 },
|
|
+ { 0x40028, 0xf },
|
|
+ { 0x40048, 0xf00 },
|
|
+ { 0x40068, 0x0 },
|
|
+ { 0x40009, 0x720 },
|
|
+ { 0x40029, 0xf },
|
|
+ { 0x40049, 0x1400 },
|
|
+ { 0x40069, 0x0 },
|
|
+ { 0x4000a, 0xe08 },
|
|
+ { 0x4002a, 0xc15 },
|
|
+ { 0x4004a, 0x0 },
|
|
+ { 0x4006a, 0x0 },
|
|
+ { 0x4000b, 0x623 },
|
|
+ { 0x4002b, 0x15 },
|
|
+ { 0x4004b, 0x0 },
|
|
+ { 0x4006b, 0x0 },
|
|
+ { 0x4000c, 0x4028 },
|
|
+ { 0x4002c, 0x80 },
|
|
+ { 0x4004c, 0x0 },
|
|
+ { 0x4006c, 0x0 },
|
|
+ { 0x4000d, 0xe08 },
|
|
+ { 0x4002d, 0xc1a },
|
|
+ { 0x4004d, 0x0 },
|
|
+ { 0x4006d, 0x0 },
|
|
+ { 0x4000e, 0x623 },
|
|
+ { 0x4002e, 0x1a },
|
|
+ { 0x4004e, 0x0 },
|
|
+ { 0x4006e, 0x0 },
|
|
+ { 0x4000f, 0x4040 },
|
|
+ { 0x4002f, 0x80 },
|
|
+ { 0x4004f, 0x0 },
|
|
+ { 0x4006f, 0x0 },
|
|
+ { 0x40010, 0x2604 },
|
|
+ { 0x40030, 0x15 },
|
|
+ { 0x40050, 0x0 },
|
|
+ { 0x40070, 0x0 },
|
|
+ { 0x40011, 0x708 },
|
|
+ { 0x40031, 0x5 },
|
|
+ { 0x40051, 0x0 },
|
|
+ { 0x40071, 0x2002 },
|
|
+ { 0x40012, 0x8 },
|
|
+ { 0x40032, 0x80 },
|
|
+ { 0x40052, 0x0 },
|
|
+ { 0x40072, 0x0 },
|
|
+ { 0x40013, 0x2604 },
|
|
+ { 0x40033, 0x1a },
|
|
+ { 0x40053, 0x0 },
|
|
+ { 0x40073, 0x0 },
|
|
+ { 0x40014, 0x708 },
|
|
+ { 0x40034, 0xa },
|
|
+ { 0x40054, 0x0 },
|
|
+ { 0x40074, 0x2002 },
|
|
+ { 0x40015, 0x4040 },
|
|
+ { 0x40035, 0x80 },
|
|
+ { 0x40055, 0x0 },
|
|
+ { 0x40075, 0x0 },
|
|
+ { 0x40016, 0x60a },
|
|
+ { 0x40036, 0x15 },
|
|
+ { 0x40056, 0x1200 },
|
|
+ { 0x40076, 0x0 },
|
|
+ { 0x40017, 0x61a },
|
|
+ { 0x40037, 0x15 },
|
|
+ { 0x40057, 0x1300 },
|
|
+ { 0x40077, 0x0 },
|
|
+ { 0x40018, 0x60a },
|
|
+ { 0x40038, 0x1a },
|
|
+ { 0x40058, 0x1200 },
|
|
+ { 0x40078, 0x0 },
|
|
+ { 0x40019, 0x642 },
|
|
+ { 0x40039, 0x1a },
|
|
+ { 0x40059, 0x1300 },
|
|
+ { 0x40079, 0x0 },
|
|
+ { 0x4001a, 0x4808 },
|
|
+ { 0x4003a, 0x880 },
|
|
+ { 0x4005a, 0x0 },
|
|
+ { 0x4007a, 0x0 },
|
|
+ { 0x900a7, 0x0 },
|
|
+ { 0x900a8, 0x790 },
|
|
+ { 0x900a9, 0x11a },
|
|
+ { 0x900aa, 0x8 },
|
|
+ { 0x900ab, 0x7aa },
|
|
+ { 0x900ac, 0x2a },
|
|
+ { 0x900ad, 0x10 },
|
|
+ { 0x900ae, 0x7b2 },
|
|
+ { 0x900af, 0x2a },
|
|
+ { 0x900b0, 0x0 },
|
|
+ { 0x900b1, 0x7c8 },
|
|
+ { 0x900b2, 0x109 },
|
|
+ { 0x900b3, 0x10 },
|
|
+ { 0x900b4, 0x2a8 },
|
|
+ { 0x900b5, 0x129 },
|
|
+ { 0x900b6, 0x8 },
|
|
+ { 0x900b7, 0x370 },
|
|
+ { 0x900b8, 0x129 },
|
|
+ { 0x900b9, 0xa },
|
|
+ { 0x900ba, 0x3c8 },
|
|
+ { 0x900bb, 0x1a9 },
|
|
+ { 0x900bc, 0xc },
|
|
+ { 0x900bd, 0x408 },
|
|
+ { 0x900be, 0x199 },
|
|
+ { 0x900bf, 0x14 },
|
|
+ { 0x900c0, 0x790 },
|
|
+ { 0x900c1, 0x11a },
|
|
+ { 0x900c2, 0x8 },
|
|
+ { 0x900c3, 0x4 },
|
|
+ { 0x900c4, 0x18 },
|
|
+ { 0x900c5, 0xe },
|
|
+ { 0x900c6, 0x408 },
|
|
+ { 0x900c7, 0x199 },
|
|
+ { 0x900c8, 0x8 },
|
|
+ { 0x900c9, 0x8568 },
|
|
+ { 0x900ca, 0x108 },
|
|
+ { 0x900cb, 0x18 },
|
|
+ { 0x900cc, 0x790 },
|
|
+ { 0x900cd, 0x16a },
|
|
+ { 0x900ce, 0x8 },
|
|
+ { 0x900cf, 0x1d8 },
|
|
+ { 0x900d0, 0x169 },
|
|
+ { 0x900d1, 0x10 },
|
|
+ { 0x900d2, 0x8558 },
|
|
+ { 0x900d3, 0x168 },
|
|
+ { 0x900d4, 0x70 },
|
|
+ { 0x900d5, 0x788 },
|
|
+ { 0x900d6, 0x16a },
|
|
+ { 0x900d7, 0x1ff8 },
|
|
+ { 0x900d8, 0x85a8 },
|
|
+ { 0x900d9, 0x1e8 },
|
|
+ { 0x900da, 0x50 },
|
|
+ { 0x900db, 0x798 },
|
|
+ { 0x900dc, 0x16a },
|
|
+ { 0x900dd, 0x60 },
|
|
+ { 0x900de, 0x7a0 },
|
|
+ { 0x900df, 0x16a },
|
|
+ { 0x900e0, 0x8 },
|
|
+ { 0x900e1, 0x8310 },
|
|
+ { 0x900e2, 0x168 },
|
|
+ { 0x900e3, 0x8 },
|
|
+ { 0x900e4, 0xa310 },
|
|
+ { 0x900e5, 0x168 },
|
|
+ { 0x900e6, 0xa },
|
|
+ { 0x900e7, 0x408 },
|
|
+ { 0x900e8, 0x169 },
|
|
+ { 0x900e9, 0x6e },
|
|
+ { 0x900ea, 0x0 },
|
|
+ { 0x900eb, 0x68 },
|
|
+ { 0x900ec, 0x0 },
|
|
+ { 0x900ed, 0x408 },
|
|
+ { 0x900ee, 0x169 },
|
|
+ { 0x900ef, 0x0 },
|
|
+ { 0x900f0, 0x8310 },
|
|
+ { 0x900f1, 0x168 },
|
|
+ { 0x900f2, 0x0 },
|
|
+ { 0x900f3, 0xa310 },
|
|
+ { 0x900f4, 0x168 },
|
|
+ { 0x900f5, 0x1ff8 },
|
|
+ { 0x900f6, 0x85a8 },
|
|
+ { 0x900f7, 0x1e8 },
|
|
+ { 0x900f8, 0x68 },
|
|
+ { 0x900f9, 0x798 },
|
|
+ { 0x900fa, 0x16a },
|
|
+ { 0x900fb, 0x78 },
|
|
+ { 0x900fc, 0x7a0 },
|
|
+ { 0x900fd, 0x16a },
|
|
+ { 0x900fe, 0x68 },
|
|
+ { 0x900ff, 0x790 },
|
|
+ { 0x90100, 0x16a },
|
|
+ { 0x90101, 0x8 },
|
|
+ { 0x90102, 0x8b10 },
|
|
+ { 0x90103, 0x168 },
|
|
+ { 0x90104, 0x8 },
|
|
+ { 0x90105, 0xab10 },
|
|
+ { 0x90106, 0x168 },
|
|
+ { 0x90107, 0xa },
|
|
+ { 0x90108, 0x408 },
|
|
+ { 0x90109, 0x169 },
|
|
+ { 0x9010a, 0x58 },
|
|
+ { 0x9010b, 0x0 },
|
|
+ { 0x9010c, 0x68 },
|
|
+ { 0x9010d, 0x0 },
|
|
+ { 0x9010e, 0x408 },
|
|
+ { 0x9010f, 0x169 },
|
|
+ { 0x90110, 0x0 },
|
|
+ { 0x90111, 0x8b10 },
|
|
+ { 0x90112, 0x168 },
|
|
+ { 0x90113, 0x0 },
|
|
+ { 0x90114, 0xab10 },
|
|
+ { 0x90115, 0x168 },
|
|
+ { 0x90116, 0x0 },
|
|
+ { 0x90117, 0x1d8 },
|
|
+ { 0x90118, 0x169 },
|
|
+ { 0x90119, 0x80 },
|
|
+ { 0x9011a, 0x790 },
|
|
+ { 0x9011b, 0x16a },
|
|
+ { 0x9011c, 0x18 },
|
|
+ { 0x9011d, 0x7aa },
|
|
+ { 0x9011e, 0x6a },
|
|
+ { 0x9011f, 0xa },
|
|
+ { 0x90120, 0x0 },
|
|
+ { 0x90121, 0x1e9 },
|
|
+ { 0x90122, 0x8 },
|
|
+ { 0x90123, 0x8080 },
|
|
+ { 0x90124, 0x108 },
|
|
+ { 0x90125, 0xf },
|
|
+ { 0x90126, 0x408 },
|
|
+ { 0x90127, 0x169 },
|
|
+ { 0x90128, 0xc },
|
|
+ { 0x90129, 0x0 },
|
|
+ { 0x9012a, 0x68 },
|
|
+ { 0x9012b, 0x9 },
|
|
+ { 0x9012c, 0x0 },
|
|
+ { 0x9012d, 0x1a9 },
|
|
+ { 0x9012e, 0x0 },
|
|
+ { 0x9012f, 0x408 },
|
|
+ { 0x90130, 0x169 },
|
|
+ { 0x90131, 0x0 },
|
|
+ { 0x90132, 0x8080 },
|
|
+ { 0x90133, 0x108 },
|
|
+ { 0x90134, 0x8 },
|
|
+ { 0x90135, 0x7aa },
|
|
+ { 0x90136, 0x6a },
|
|
+ { 0x90137, 0x0 },
|
|
+ { 0x90138, 0x8568 },
|
|
+ { 0x90139, 0x108 },
|
|
+ { 0x9013a, 0xb7 },
|
|
+ { 0x9013b, 0x790 },
|
|
+ { 0x9013c, 0x16a },
|
|
+ { 0x9013d, 0x1f },
|
|
+ { 0x9013e, 0x0 },
|
|
+ { 0x9013f, 0x68 },
|
|
+ { 0x90140, 0x8 },
|
|
+ { 0x90141, 0x8558 },
|
|
+ { 0x90142, 0x168 },
|
|
+ { 0x90143, 0xf },
|
|
+ { 0x90144, 0x408 },
|
|
+ { 0x90145, 0x169 },
|
|
+ { 0x90146, 0xc },
|
|
+ { 0x90147, 0x0 },
|
|
+ { 0x90148, 0x68 },
|
|
+ { 0x90149, 0x0 },
|
|
+ { 0x9014a, 0x408 },
|
|
+ { 0x9014b, 0x169 },
|
|
+ { 0x9014c, 0x0 },
|
|
+ { 0x9014d, 0x8558 },
|
|
+ { 0x9014e, 0x168 },
|
|
+ { 0x9014f, 0x8 },
|
|
+ { 0x90150, 0x3c8 },
|
|
+ { 0x90151, 0x1a9 },
|
|
+ { 0x90152, 0x3 },
|
|
+ { 0x90153, 0x370 },
|
|
+ { 0x90154, 0x129 },
|
|
+ { 0x90155, 0x20 },
|
|
+ { 0x90156, 0x2aa },
|
|
+ { 0x90157, 0x9 },
|
|
+ { 0x90158, 0x0 },
|
|
+ { 0x90159, 0x400 },
|
|
+ { 0x9015a, 0x10e },
|
|
+ { 0x9015b, 0x8 },
|
|
+ { 0x9015c, 0xe8 },
|
|
+ { 0x9015d, 0x109 },
|
|
+ { 0x9015e, 0x0 },
|
|
+ { 0x9015f, 0x8140 },
|
|
+ { 0x90160, 0x10c },
|
|
+ { 0x90161, 0x10 },
|
|
+ { 0x90162, 0x8138 },
|
|
+ { 0x90163, 0x10c },
|
|
+ { 0x90164, 0x8 },
|
|
+ { 0x90165, 0x7c8 },
|
|
+ { 0x90166, 0x101 },
|
|
+ { 0x90167, 0x8 },
|
|
+ { 0x90168, 0x0 },
|
|
+ { 0x90169, 0x8 },
|
|
+ { 0x9016a, 0x8 },
|
|
+ { 0x9016b, 0x448 },
|
|
+ { 0x9016c, 0x109 },
|
|
+ { 0x9016d, 0xf },
|
|
+ { 0x9016e, 0x7c0 },
|
|
+ { 0x9016f, 0x109 },
|
|
+ { 0x90170, 0x0 },
|
|
+ { 0x90171, 0xe8 },
|
|
+ { 0x90172, 0x109 },
|
|
+ { 0x90173, 0x47 },
|
|
+ { 0x90174, 0x630 },
|
|
+ { 0x90175, 0x109 },
|
|
+ { 0x90176, 0x8 },
|
|
+ { 0x90177, 0x618 },
|
|
+ { 0x90178, 0x109 },
|
|
+ { 0x90179, 0x8 },
|
|
+ { 0x9017a, 0xe0 },
|
|
+ { 0x9017b, 0x109 },
|
|
+ { 0x9017c, 0x0 },
|
|
+ { 0x9017d, 0x7c8 },
|
|
+ { 0x9017e, 0x109 },
|
|
+ { 0x9017f, 0x8 },
|
|
+ { 0x90180, 0x8140 },
|
|
+ { 0x90181, 0x10c },
|
|
+ { 0x90182, 0x0 },
|
|
+ { 0x90183, 0x1 },
|
|
+ { 0x90184, 0x8 },
|
|
+ { 0x90185, 0x8 },
|
|
+ { 0x90186, 0x4 },
|
|
+ { 0x90187, 0x8 },
|
|
+ { 0x90188, 0x8 },
|
|
+ { 0x90189, 0x7c8 },
|
|
+ { 0x9018a, 0x101 },
|
|
+ { 0x90006, 0x0 },
|
|
+ { 0x90007, 0x0 },
|
|
+ { 0x90008, 0x8 },
|
|
+ { 0x90009, 0x0 },
|
|
+ { 0x9000a, 0x0 },
|
|
+ { 0x9000b, 0x0 },
|
|
+ { 0xd00e7, 0x400 },
|
|
+ { 0x90017, 0x0 },
|
|
+ { 0x9001f, 0x2a },
|
|
+ { 0x90026, 0x6a },
|
|
+ { 0x400d0, 0x0 },
|
|
+ { 0x400d1, 0x101 },
|
|
+ { 0x400d2, 0x105 },
|
|
+ { 0x400d3, 0x107 },
|
|
+ { 0x400d4, 0x10f },
|
|
+ { 0x400d5, 0x202 },
|
|
+ { 0x400d6, 0x20a },
|
|
+ { 0x400d7, 0x20b },
|
|
+ { 0x2003a, 0x2 },
|
|
+ { 0x2000b, 0x5d },
|
|
+ { 0x2000c, 0xbb },
|
|
+ { 0x2000d, 0x753 },
|
|
+ { 0x2000e, 0x2c },
|
|
+ { 0x12000b, 0xc },
|
|
+ { 0x12000c, 0x19 },
|
|
+ { 0x12000d, 0xfa },
|
|
+ { 0x12000e, 0x10 },
|
|
+ { 0x22000b, 0x3 },
|
|
+ { 0x22000c, 0x6 },
|
|
+ { 0x22000d, 0x3e },
|
|
+ { 0x22000e, 0x10 },
|
|
+ { 0x9000c, 0x0 },
|
|
+ { 0x9000d, 0x173 },
|
|
+ { 0x9000e, 0x60 },
|
|
+ { 0x9000f, 0x6110 },
|
|
+ { 0x90010, 0x2152 },
|
|
+ { 0x90011, 0xdfbd },
|
|
+ { 0x90012, 0x60 },
|
|
+ { 0x90013, 0x6152 },
|
|
+ { 0x20010, 0x5a },
|
|
+ { 0x20011, 0x3 },
|
|
+ { 0x120010, 0x5a },
|
|
+ { 0x120011, 0x3 },
|
|
+ { 0x220010, 0x5a },
|
|
+ { 0x220011, 0x3 },
|
|
+ { 0x40080, 0xe0 },
|
|
+ { 0x40081, 0x12 },
|
|
+ { 0x40082, 0xe0 },
|
|
+ { 0x40083, 0x12 },
|
|
+ { 0x40084, 0xe0 },
|
|
+ { 0x40085, 0x12 },
|
|
+ { 0x140080, 0xe0 },
|
|
+ { 0x140081, 0x12 },
|
|
+ { 0x140082, 0xe0 },
|
|
+ { 0x140083, 0x12 },
|
|
+ { 0x140084, 0xe0 },
|
|
+ { 0x140085, 0x12 },
|
|
+ { 0x240080, 0xe0 },
|
|
+ { 0x240081, 0x12 },
|
|
+ { 0x240082, 0xe0 },
|
|
+ { 0x240083, 0x12 },
|
|
+ { 0x240084, 0xe0 },
|
|
+ { 0x240085, 0x12 },
|
|
+ { 0x400fd, 0xf },
|
|
+ { 0x10011, 0x1 },
|
|
+ { 0x10012, 0x1 },
|
|
+ { 0x10013, 0x180 },
|
|
+ { 0x10018, 0x1 },
|
|
+ { 0x10002, 0x6209 },
|
|
+ { 0x100b2, 0x1 },
|
|
+ { 0x101b4, 0x1 },
|
|
+ { 0x102b4, 0x1 },
|
|
+ { 0x103b4, 0x1 },
|
|
+ { 0x104b4, 0x1 },
|
|
+ { 0x105b4, 0x1 },
|
|
+ { 0x106b4, 0x1 },
|
|
+ { 0x107b4, 0x1 },
|
|
+ { 0x108b4, 0x1 },
|
|
+ { 0x11011, 0x1 },
|
|
+ { 0x11012, 0x1 },
|
|
+ { 0x11013, 0x180 },
|
|
+ { 0x11018, 0x1 },
|
|
+ { 0x11002, 0x6209 },
|
|
+ { 0x110b2, 0x1 },
|
|
+ { 0x111b4, 0x1 },
|
|
+ { 0x112b4, 0x1 },
|
|
+ { 0x113b4, 0x1 },
|
|
+ { 0x114b4, 0x1 },
|
|
+ { 0x115b4, 0x1 },
|
|
+ { 0x116b4, 0x1 },
|
|
+ { 0x117b4, 0x1 },
|
|
+ { 0x118b4, 0x1 },
|
|
+ { 0x12011, 0x1 },
|
|
+ { 0x12012, 0x1 },
|
|
+ { 0x12013, 0x180 },
|
|
+ { 0x12018, 0x1 },
|
|
+ { 0x12002, 0x6209 },
|
|
+ { 0x120b2, 0x1 },
|
|
+ { 0x121b4, 0x1 },
|
|
+ { 0x122b4, 0x1 },
|
|
+ { 0x123b4, 0x1 },
|
|
+ { 0x124b4, 0x1 },
|
|
+ { 0x125b4, 0x1 },
|
|
+ { 0x126b4, 0x1 },
|
|
+ { 0x127b4, 0x1 },
|
|
+ { 0x128b4, 0x1 },
|
|
+ { 0x13011, 0x1 },
|
|
+ { 0x13012, 0x1 },
|
|
+ { 0x13013, 0x180 },
|
|
+ { 0x13018, 0x1 },
|
|
+ { 0x13002, 0x6209 },
|
|
+ { 0x130b2, 0x1 },
|
|
+ { 0x131b4, 0x1 },
|
|
+ { 0x132b4, 0x1 },
|
|
+ { 0x133b4, 0x1 },
|
|
+ { 0x134b4, 0x1 },
|
|
+ { 0x135b4, 0x1 },
|
|
+ { 0x136b4, 0x1 },
|
|
+ { 0x137b4, 0x1 },
|
|
+ { 0x138b4, 0x1 },
|
|
+ { 0x2003a, 0x2 },
|
|
+ { 0xc0080, 0x2 },
|
|
+ { 0xd0000, 0x1 }
|
|
+};
|
|
+
|
|
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
|
+ {
|
|
+ /* P0 3000mts 1D */
|
|
+ .drate = 3000,
|
|
+ .fw_type = FW_1D_IMAGE,
|
|
+ .fsp_cfg = ddr_fsp0_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
|
|
+ },
|
|
+ {
|
|
+ /* P1 400mts 1D */
|
|
+ .drate = 400,
|
|
+ .fw_type = FW_1D_IMAGE,
|
|
+ .fsp_cfg = ddr_fsp1_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
|
|
+ },
|
|
+ {
|
|
+ /* P2 100mts 1D */
|
|
+ .drate = 100,
|
|
+ .fw_type = FW_1D_IMAGE,
|
|
+ .fsp_cfg = ddr_fsp2_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
|
|
+ },
|
|
+ {
|
|
+ /* P0 3000mts 2D */
|
|
+ .drate = 3000,
|
|
+ .fw_type = FW_2D_IMAGE,
|
|
+ .fsp_cfg = ddr_fsp0_2d_cfg,
|
|
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
|
+ },
|
|
+};
|
|
+
|
|
+/* ddr timing config params */
|
|
+struct dram_timing_info dram_timing = {
|
|
+ .ddrc_cfg = ddr_ddrc_cfg,
|
|
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
|
|
+ .ddrphy_cfg = ddr_ddrphy_cfg,
|
|
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
|
|
+ .fsp_msg = ddr_dram_fsp_msg,
|
|
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
|
|
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
|
|
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
|
|
+ .ddrphy_pie = ddr_phy_pie,
|
|
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
|
|
+ .fsp_table = { 3000, 400, 100, },
|
|
+};
|
|
Index: u-boot-imx/board/tiesse/tgr/spl.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/board/tiesse/tgr/spl.c
|
|
@@ -0,0 +1,307 @@
|
|
+/*
|
|
+ * Copyright 2018-2019 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <spl.h>
|
|
+#include <asm/io.h>
|
|
+#include <errno.h>
|
|
+#include <asm/io.h>
|
|
+#include <asm/mach-imx/iomux-v3.h>
|
|
+#include <asm/arch/imx8mm_pins.h>
|
|
+#include <asm/arch/sys_proto.h>
|
|
+#include <power/pmic.h>
|
|
+#include <power/pca9450.h>
|
|
+#include <asm/arch/clock.h>
|
|
+#include <asm/mach-imx/gpio.h>
|
|
+#include <asm/mach-imx/mxc_i2c.h>
|
|
+#include <fsl_esdhc.h>
|
|
+#include <mmc.h>
|
|
+#include <asm/arch/imx8m_ddr.h>
|
|
+
|
|
+DECLARE_GLOBAL_DATA_PTR;
|
|
+
|
|
+void spl_dram_init(void)
|
|
+{
|
|
+ ddr_init(&dram_timing);
|
|
+}
|
|
+
|
|
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
|
|
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
|
+struct i2c_pads_info i2c_pad_info1 = {
|
|
+ .scl = {
|
|
+ .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
|
|
+ .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
|
|
+ .gp = IMX_GPIO_NR(5, 14),
|
|
+ },
|
|
+ .sda = {
|
|
+ .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
|
|
+ .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
|
|
+ .gp = IMX_GPIO_NR(5, 15),
|
|
+ },
|
|
+};
|
|
+
|
|
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
|
|
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
|
|
+
|
|
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
|
|
+ PAD_CTL_FSEL2)
|
|
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
|
|
+
|
|
+static iomux_v3_cfg_t const usdhc3_pads[] = {
|
|
+ IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+};
|
|
+
|
|
+static iomux_v3_cfg_t const usdhc2_pads[] = {
|
|
+ IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
+ IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
|
+};
|
|
+
|
|
+/*
|
|
+ * The evk board uses DAT3 to detect CD card plugin,
|
|
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
|
|
+ */
|
|
+static iomux_v3_cfg_t const usdhc2_cd_pad =
|
|
+ IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
|
|
+
|
|
+static iomux_v3_cfg_t const usdhc2_dat3_pad =
|
|
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
|
|
+ MUX_PAD_CTRL(USDHC_PAD_CTRL);
|
|
+
|
|
+
|
|
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
|
+ {USDHC2_BASE_ADDR, 0, 1},
|
|
+ {USDHC3_BASE_ADDR, 0, 1},
|
|
+};
|
|
+
|
|
+int board_mmc_init(bd_t *bis)
|
|
+{
|
|
+ int i, ret;
|
|
+ /*
|
|
+ * According to the board_mmc_init() the following map is done:
|
|
+ * (U-Boot device node) (Physical Port)
|
|
+ * mmc0 USDHC1
|
|
+ * mmc1 USDHC2
|
|
+ */
|
|
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
+ switch (i) {
|
|
+ case 0:
|
|
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
+ imx_iomux_v3_setup_multiple_pads(
|
|
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
|
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
|
|
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
|
+ udelay(500);
|
|
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
|
+ break;
|
|
+ case 1:
|
|
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
+ imx_iomux_v3_setup_multiple_pads(
|
|
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
|
+ break;
|
|
+ default:
|
|
+ printf("Warning: you configured more USDHC controllers"
|
|
+ "(%d) than supported by the board\n", i + 1);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int board_mmc_getcd(struct mmc *mmc)
|
|
+{
|
|
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
+ int ret = 0;
|
|
+
|
|
+ switch (cfg->esdhc_base) {
|
|
+ case USDHC3_BASE_ADDR:
|
|
+ ret = 1;
|
|
+ break;
|
|
+ case USDHC2_BASE_ADDR:
|
|
+ imx_iomux_v3_setup_pad(usdhc2_cd_pad);
|
|
+ gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
|
|
+ gpio_direction_input(USDHC2_CD_GPIO);
|
|
+
|
|
+ /*
|
|
+ * Since it is the DAT3 pin, this pin is pulled to
|
|
+ * low voltage if no card
|
|
+ */
|
|
+ ret = gpio_get_value(USDHC2_CD_GPIO);
|
|
+
|
|
+ imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ return 1;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_POWER
|
|
+#define I2C_PMIC 0
|
|
+int power_init_board(void)
|
|
+{
|
|
+ struct pmic *p;
|
|
+ int ret;
|
|
+
|
|
+ ret = power_pca9450b_init(I2C_PMIC);
|
|
+ if (ret)
|
|
+ printf("power init failed");
|
|
+
|
|
+ p = pmic_get("PCA9450");
|
|
+ pmic_probe(p);
|
|
+
|
|
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
|
|
+ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
|
|
+
|
|
+ /* Buck 1 DVS control through PMIC_STBY_REQ */
|
|
+ pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
|
|
+
|
|
+ /* decrease RESET key long push time from the default 10s to 10ms */
|
|
+ /* Ton_Deb of PCA9450 is 20ms and don't change */
|
|
+
|
|
+ /* increase VDD_SOC to typical value 0.85v before first DRAM access */
|
|
+ /* pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); */
|
|
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
|
|
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x10);
|
|
+
|
|
+ /* increase VDD_DRAM to 0.975v for 3Ghz DDR -> 0.95V instead of 0.975V, */
|
|
+ /* because PCA9450 Buck3 can set 0.95V */
|
|
+ /* Also, set B3_ENMODE=2 (ON by PMIC_ON_REQ=H & PMIC_STBY_REQ=L) */
|
|
+ pmic_reg_write(p, PCA9450_BUCK3OUT_DVS0, 0x1C);
|
|
+ pmic_reg_write(p, PCA9450_BUCK3CTRL, 0x4A);
|
|
+
|
|
+ /* set VDD_SNVS_0V8 from default 0.85V */
|
|
+ pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0);
|
|
+
|
|
+#ifndef CONFIG_IMX8M_LPDDR4
|
|
+ /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
|
|
+ pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
|
|
+#endif
|
|
+ /* set WDOG_B_CFG to 10b=Cold Reset, except LDO1/2 */
|
|
+ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+void spl_board_init(void)
|
|
+{
|
|
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
|
|
+ /* Serial download mode */
|
|
+ if (is_usb_boot()) {
|
|
+ puts("Back to ROM, SDP\n");
|
|
+ restore_boot_params();
|
|
+ }
|
|
+#endif
|
|
+ puts("Normal Boot\n");
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_SPL_LOAD_FIT
|
|
+int board_fit_config_name_match(const char *name)
|
|
+{
|
|
+ /* Just empty function now - can't decide what to choose */
|
|
+ debug("%s: %s\n", __func__, name);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+static iomux_v3_cfg_t btn_pads[] = {
|
|
+ IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 | MUX_PAD_CTRL(PAD_CTL_HYS),
|
|
+};
|
|
+
|
|
+#define RST_BTN IMX_GPIO_NR(4, 9)
|
|
+static void rst_btn_init(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(btn_pads, ARRAY_SIZE(btn_pads));
|
|
+ gpio_request(RST_BTN, "rst_btn");
|
|
+ gpio_direction_input(RST_BTN);
|
|
+}
|
|
+
|
|
+static iomux_v3_cfg_t led_pads[] = {
|
|
+ IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
+ IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
+};
|
|
+
|
|
+#define LED_MODEM IMX_GPIO_NR(4, 7)
|
|
+#define LED_PWR IMX_GPIO_NR(4, 8)
|
|
+static void leds_init(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
|
|
+ gpio_request(LED_MODEM, "led_modem");
|
|
+ gpio_direction_output(LED_MODEM, 0);
|
|
+ gpio_request(LED_PWR, "led_pwr");
|
|
+ gpio_direction_output(LED_PWR, 1);
|
|
+}
|
|
+
|
|
+static iomux_v3_cfg_t modem_pads[] = {
|
|
+ IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
+};
|
|
+
|
|
+#define MODEM_PWR IMX_GPIO_NR(4, 3)
|
|
+static void modem_pwr_init(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(modem_pads, ARRAY_SIZE(modem_pads));
|
|
+ gpio_request(MODEM_PWR, "modem_pwr");
|
|
+ gpio_direction_output(MODEM_PWR, 0);
|
|
+}
|
|
+
|
|
+void board_init_f(ulong dummy)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ /* Clear global data */
|
|
+ memset((void *)gd, 0, sizeof(gd_t));
|
|
+
|
|
+ leds_init();
|
|
+
|
|
+ arch_cpu_init();
|
|
+
|
|
+ board_early_init_f();
|
|
+
|
|
+ timer_init();
|
|
+
|
|
+ preloader_console_init();
|
|
+
|
|
+ /* Clear the BSS. */
|
|
+ memset(__bss_start, 0, __bss_end - __bss_start);
|
|
+
|
|
+ ret = spl_init();
|
|
+ if (ret) {
|
|
+ debug("spl_init() failed: %d\n", ret);
|
|
+ hang();
|
|
+ }
|
|
+
|
|
+ enable_tzc380();
|
|
+
|
|
+ /* Adjust pmic voltage to 1.0V for 800M */
|
|
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
+
|
|
+ power_init_board();
|
|
+
|
|
+ /* DDR initialization */
|
|
+ spl_dram_init();
|
|
+
|
|
+ rst_btn_init();
|
|
+
|
|
+ board_init_r(NULL, 0);
|
|
+}
|
|
Index: u-boot-imx/board/tiesse/tgr/tgr.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/board/tiesse/tgr/tgr.c
|
|
@@ -0,0 +1,290 @@
|
|
+/*
|
|
+ * Copyright 2018 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <malloc.h>
|
|
+#include <errno.h>
|
|
+#include <asm/io.h>
|
|
+#include <miiphy.h>
|
|
+#include <netdev.h>
|
|
+#include <asm/mach-imx/iomux-v3.h>
|
|
+#include <asm-generic/gpio.h>
|
|
+#include <fsl_esdhc.h>
|
|
+#include <mmc.h>
|
|
+#include <asm/arch/imx8mm_pins.h>
|
|
+#include <asm/arch/sys_proto.h>
|
|
+#include <asm/mach-imx/gpio.h>
|
|
+#include <asm/mach-imx/mxc_i2c.h>
|
|
+#include <asm/arch/clock.h>
|
|
+#include <spl.h>
|
|
+#include <asm/mach-imx/dma.h>
|
|
+#include <power/pmic.h>
|
|
+#include <usb.h>
|
|
+#include <sec_mipi_dsim.h>
|
|
+#include <imx_mipi_dsi_bridge.h>
|
|
+#include <mipi_dsi_panel.h>
|
|
+#include <asm/mach-imx/video.h>
|
|
+
|
|
+DECLARE_GLOBAL_DATA_PTR;
|
|
+
|
|
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
|
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
|
+
|
|
+static iomux_v3_cfg_t const uart_pads[] = {
|
|
+ IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
+ IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
+};
|
|
+
|
|
+static iomux_v3_cfg_t const wdog_pads[] = {
|
|
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_FSL_FSPI
|
|
+#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
|
|
+static iomux_v3_cfg_t const qspi_pads[] = {
|
|
+ IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL | PAD_CTL_PE | PAD_CTL_PUE),
|
|
+ IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
|
+
|
|
+ IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
|
+};
|
|
+
|
|
+int board_qspi_init(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
|
|
+
|
|
+ set_clk_qspi();
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_MXC_SPI
|
|
+#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
|
|
+static iomux_v3_cfg_t const ecspi1_pads[] = {
|
|
+ IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
+};
|
|
+
|
|
+static iomux_v3_cfg_t const ecspi2_pads[] = {
|
|
+ IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
|
+ IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
+};
|
|
+
|
|
+static void setup_spi(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
|
|
+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
|
|
+ gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS");
|
|
+ gpio_request(IMX_GPIO_NR(5, 13), "ECSPI2 CS");
|
|
+}
|
|
+
|
|
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
|
+{
|
|
+ if (bus == 0)
|
|
+ return IMX_GPIO_NR(5, 9);
|
|
+ else
|
|
+ return IMX_GPIO_NR(5, 13);
|
|
+}
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_NAND_MXS
|
|
+#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
|
|
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
|
|
+static iomux_v3_cfg_t const gpmi_pads[] = {
|
|
+ IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
|
|
+ IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+ IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
+};
|
|
+
|
|
+static void setup_gpmi_nand(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
|
|
+}
|
|
+#endif
|
|
+
|
|
+#define MODEM_PWR IMX_GPIO_NR(4, 3)
|
|
+int board_early_init_f(void)
|
|
+{
|
|
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
+
|
|
+ set_wdog_reset(wdog);
|
|
+
|
|
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
|
+
|
|
+#ifdef CONFIG_NAND_MXS
|
|
+ setup_gpmi_nand(); /* SPL will call the board_early_init_f */
|
|
+#endif
|
|
+
|
|
+ gpio_request(MODEM_PWR, "modem_pwr");
|
|
+ gpio_direction_output(MODEM_PWR, 0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_BOARD_POSTCLK_INIT
|
|
+int board_postclk_init(void)
|
|
+{
|
|
+ /* TODO */
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+int dram_init(void)
|
|
+{
|
|
+ /* rom_pointer[1] contains the size of TEE occupies */
|
|
+ if (rom_pointer[1])
|
|
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
|
|
+ else
|
|
+ gd->ram_size = PHYS_SDRAM_SIZE;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_OF_BOARD_SETUP
|
|
+int ft_board_setup(void *blob, bd_t *bd)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_FEC_MXC
|
|
+#define FEC_RST_PAD IMX_GPIO_NR(4, 17)
|
|
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
|
|
+ IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
+};
|
|
+
|
|
+static void setup_iomux_fec(void)
|
|
+{
|
|
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
|
|
+ ARRAY_SIZE(fec1_rst_pads));
|
|
+
|
|
+ gpio_request(FEC_RST_PAD, "fec1_rst");
|
|
+ gpio_direction_output(FEC_RST_PAD, 0);
|
|
+ udelay(10000);
|
|
+ gpio_direction_output(FEC_RST_PAD, 1);
|
|
+}
|
|
+
|
|
+static int setup_fec(void)
|
|
+{
|
|
+ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
|
+ = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
|
+
|
|
+ setup_iomux_fec();
|
|
+
|
|
+ /* Use 50M anatop REF_CLK1 for ENET1, not from external */
|
|
+ setbits_le32(&iomuxc_gpr_regs->gpr[1],
|
|
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
|
|
+
|
|
+ return set_clk_enet(ENET_50MHZ);
|
|
+}
|
|
+
|
|
+int board_phy_config(struct phy_device *phydev)
|
|
+{
|
|
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
|
+
|
|
+ if (phydev->drv->config)
|
|
+ phydev->drv->config(phydev);
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+
|
|
+int board_init(void)
|
|
+{
|
|
+#ifdef CONFIG_MXC_SPI
|
|
+ setup_spi();
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_FEC_MXC
|
|
+ setup_fec();
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_FSL_FSPI
|
|
+ board_qspi_init();
|
|
+#endif
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int board_mmc_get_env_dev(int devno)
|
|
+{
|
|
+ return devno - 1;
|
|
+}
|
|
+
|
|
+int mmc_map_to_kernel_blk(int devno)
|
|
+{
|
|
+ return devno + 1;
|
|
+}
|
|
+
|
|
+static int check_mmc_autodetect(void)
|
|
+{
|
|
+ char *autodetect_str = env_get("mmcautodetect");
|
|
+
|
|
+ if ((autodetect_str != NULL) &&
|
|
+ (strcmp(autodetect_str, "yes") == 0)) {
|
|
+ return 1;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void board_late_mmc_env_init(void)
|
|
+{
|
|
+ char cmd[32];
|
|
+ char mmcblk[32];
|
|
+ u32 dev_no = mmc_get_env_dev();
|
|
+
|
|
+ if (!check_mmc_autodetect())
|
|
+ return;
|
|
+
|
|
+ env_set_ulong("mmcdev", dev_no);
|
|
+
|
|
+ /* Set mmcblk env */
|
|
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
|
|
+ mmc_map_to_kernel_blk(dev_no));
|
|
+ env_set("mmcroot", mmcblk);
|
|
+
|
|
+ sprintf(cmd, "mmc dev %d", dev_no);
|
|
+ run_command(cmd, 0);
|
|
+}
|
|
+
|
|
+int board_late_init(void)
|
|
+{
|
|
+#ifdef CONFIG_ENV_IS_IN_MMC
|
|
+ board_late_mmc_env_init();
|
|
+#endif
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_FSL_FASTBOOT
|
|
+#ifdef CONFIG_ANDROID_RECOVERY
|
|
+int is_recovery_key_pressing(void)
|
|
+{
|
|
+ return 0; /*TODO*/
|
|
+}
|
|
+#endif /*CONFIG_ANDROID_RECOVERY*/
|
|
+#endif /*CONFIG_FSL_FASTBOOT*/
|
|
Index: u-boot-imx/include/configs/tgr.h
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/include/configs/tgr.h
|
|
@@ -0,0 +1,357 @@
|
|
+/*
|
|
+ * Copyright 2018 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#ifndef __IMX8MM_TGR_H
|
|
+#define __IMX8MM_TGR_H
|
|
+
|
|
+#include <linux/sizes.h>
|
|
+#include <asm/arch/imx-regs.h>
|
|
+
|
|
+#include "imx_env.h"
|
|
+
|
|
+#ifdef CONFIG_SECURE_BOOT
|
|
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
|
|
+#endif
|
|
+
|
|
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
|
|
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
|
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
|
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
|
|
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
|
+#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
|
+
|
|
+#ifdef CONFIG_SPL_BUILD
|
|
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
|
|
+#define CONFIG_SPL_WATCHDOG_SUPPORT
|
|
+#define CONFIG_SPL_POWER_SUPPORT
|
|
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
|
+#define CONFIG_SPL_I2C_SUPPORT
|
|
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
|
+#define CONFIG_SPL_STACK 0x91fff0
|
|
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
|
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
|
+#define CONFIG_SPL_SERIAL_SUPPORT
|
|
+#define CONFIG_SPL_GPIO_SUPPORT
|
|
+#define CONFIG_SPL_BSS_START_ADDR 0x00910000
|
|
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
|
|
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
|
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
|
|
+#define CONFIG_SYS_ICACHE_OFF
|
|
+#define CONFIG_SYS_DCACHE_OFF
|
|
+
|
|
+#define CONFIG_MALLOC_F_ADDR 0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
|
+
|
|
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
|
|
+
|
|
+#undef CONFIG_DM_MMC
|
|
+#undef CONFIG_DM_PMIC
|
|
+#undef CONFIG_DM_PMIC_PFUZE100
|
|
+
|
|
+#define CONFIG_POWER
|
|
+#define CONFIG_POWER_I2C
|
|
+#define CONFIG_POWER_PCA9450
|
|
+
|
|
+#define CONFIG_SYS_I2C
|
|
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
|
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
|
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
|
+
|
|
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
+
|
|
+#if defined(CONFIG_NAND_BOOT)
|
|
+#define CONFIG_SPL_NAND_SUPPORT
|
|
+#define CONFIG_SPL_DMA_SUPPORT
|
|
+#define CONFIG_SPL_NAND_MXS
|
|
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
|
|
+
|
|
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
|
|
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
|
|
+ (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
|
|
+#endif
|
|
+
|
|
+#endif
|
|
+
|
|
+#define CONFIG_CMD_READ
|
|
+#define CONFIG_SERIAL_TAG
|
|
+#define CONFIG_FASTBOOT_USB_DEV 0
|
|
+
|
|
+#define CONFIG_REMAKE_ELF
|
|
+
|
|
+#define CONFIG_BOARD_EARLY_INIT_F
|
|
+#define CONFIG_BOARD_POSTCLK_INIT
|
|
+#define CONFIG_BOARD_LATE_INIT
|
|
+
|
|
+/* Flat Device Tree Definitions */
|
|
+#define CONFIG_OF_BOARD_SETUP
|
|
+
|
|
+#undef CONFIG_CMD_EXPORTENV
|
|
+#undef CONFIG_CMD_IMPORTENV
|
|
+#undef CONFIG_CMD_IMLS
|
|
+
|
|
+#undef CONFIG_CMD_CRC32
|
|
+#undef CONFIG_BOOTM_NETBSD
|
|
+
|
|
+/* ENET Config */
|
|
+/* ENET1 */
|
|
+#if defined(CONFIG_CMD_NET)
|
|
+#define CONFIG_CMD_PING
|
|
+#define CONFIG_CMD_DHCP
|
|
+#define CONFIG_CMD_MII
|
|
+#define CONFIG_MII
|
|
+#define CONFIG_ETHPRIME "FEC"
|
|
+
|
|
+#define CONFIG_FEC_MXC
|
|
+#define CONFIG_FEC_XCV_TYPE RMII
|
|
+#define CONFIG_FEC_MXC_PHYADDR 0x5
|
|
+#define FEC_QUIRK_ENET_MAC
|
|
+#define CONFIG_PHY_MICREL
|
|
+#define CONFIG_PHY_MICREL_KSZ8XXX
|
|
+
|
|
+#define IMX_FEC_BASE 0x30BE0000
|
|
+
|
|
+#define CONFIG_PHYLIB
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * Another approach is add the clocks for inmates into clks_init_on
|
|
+ * in clk-imx8mm.c, then clk_ingore_unused could be removed.
|
|
+ */
|
|
+#define JAILHOUSE_ENV \
|
|
+ "jh_clk= \0 " \
|
|
+ "jh_mmcboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb;" \
|
|
+ "setenv jh_clk clk_ignore_unused; " \
|
|
+ "if run loadimage; then " \
|
|
+ "run mmcboot; " \
|
|
+ "else run jh_netboot; fi; \0" \
|
|
+ "jh_netboot=mw 0x303d0518 0xff; setenv fdt_file fsl-imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused; run netboot; \0 "
|
|
+
|
|
+#ifdef CONFIG_NAND_BOOT
|
|
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
|
|
+#endif
|
|
+
|
|
+#define CONFIG_MFG_ENV_SETTINGS \
|
|
+ CONFIG_MFG_ENV_SETTINGS_DEFAULT \
|
|
+ "initrd_addr=0x43800000\0" \
|
|
+ "initrd_high=0xffffffffffffffff\0" \
|
|
+ "emmc_dev=1\0"\
|
|
+ "sd_dev=0\0" \
|
|
+
|
|
+/* Initial environment variables */
|
|
+#if defined(CONFIG_NAND_BOOT)
|
|
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
+ CONFIG_MFG_ENV_SETTINGS \
|
|
+ "fdt_addr=0x43000000\0" \
|
|
+ "fdt_high=0xffffffffffffffff\0" \
|
|
+ "mtdparts=" MFG_NAND_PARTITION "\0" \
|
|
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
|
|
+ "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=5 " \
|
|
+ "root=ubi0:nandrootfs rootfstype=ubifs " \
|
|
+ MFG_NAND_PARTITION \
|
|
+ "\0" \
|
|
+ "bootcmd=fatload mmc 1:1 ${fdt_addr} fsl-imx8mm-tgr.dtb;"\
|
|
+ "fatload mmc 1:1 ${loadaddr} Image;"\
|
|
+ "booti ${loadaddr} - ${fdt_addr}"
|
|
+
|
|
+#else
|
|
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
+ CONFIG_MFG_ENV_SETTINGS \
|
|
+ JAILHOUSE_ENV \
|
|
+ "script=boot.scr\0" \
|
|
+ "image=Image\0" \
|
|
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
|
|
+ "fdt_addr=0x43000000\0" \
|
|
+ "fdt_high=0xffffffffffffffff\0" \
|
|
+ "boot_fdt=try\0" \
|
|
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
|
+ "initrd_addr=0x43800000\0" \
|
|
+ "initrd_high=0xffffffffffffffff\0" \
|
|
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
|
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
|
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
|
+ "bootargs=console=ttymxc1,115200 root=/dev/mmcblk2p2 rootwait rw\0" \
|
|
+ "mmcautodetect=yes\0"
|
|
+
|
|
+#define CONFIG_BOOTCOMMAND \
|
|
+ "fatload mmc 1:1 ${fdt_addr} fsl-imx8mm-tgr.dtb;" \
|
|
+ "fatload mmc 1:1 ${loadaddr} Image;" \
|
|
+ "booti ${loadaddr} - ${fdt_addr}; "
|
|
+#endif
|
|
+
|
|
+/* Link Definitions */
|
|
+#define CONFIG_LOADADDR 0x40480000
|
|
+
|
|
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
|
+
|
|
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
|
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
|
+#define CONFIG_SYS_INIT_SP_OFFSET \
|
|
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
+#define CONFIG_SYS_INIT_SP_ADDR \
|
|
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
|
+
|
|
+#define CONFIG_ENV_OVERWRITE
|
|
+#if defined(CONFIG_ENV_IS_IN_MMC)
|
|
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
|
|
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
|
+#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
|
|
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
|
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
|
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
|
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
|
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
|
+#elif defined(CONFIG_ENV_IS_IN_NAND)
|
|
+#define CONFIG_ENV_OFFSET (60 << 20)
|
|
+#endif
|
|
+#define CONFIG_ENV_SIZE 0x2000
|
|
+#define CONFIG_SYS_MMC_ENV_DEV 1
|
|
+#define CONFIG_MMCROOT "/dev/mmcblk2p2"
|
|
+
|
|
+/* Size of malloc() pool */
|
|
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
|
|
+
|
|
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
|
+#define PHYS_SDRAM 0x40000000
|
|
+#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
|
|
+#define CONFIG_NR_DRAM_BANKS 1
|
|
+
|
|
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
|
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
|
|
+
|
|
+#define CONFIG_BAUDRATE 115200
|
|
+
|
|
+#define CONFIG_MXC_UART
|
|
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
|
|
+
|
|
+/* Monitor Command Prompt */
|
|
+#undef CONFIG_SYS_PROMPT
|
|
+#define CONFIG_SYS_PROMPT "u-boot=> "
|
|
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
|
+#define CONFIG_SYS_CBSIZE 2048
|
|
+#define CONFIG_SYS_MAXARGS 64
|
|
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
|
+ sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
+
|
|
+#define CONFIG_IMX_BOOTAUX
|
|
+
|
|
+/* USDHC */
|
|
+#define CONFIG_CMD_MMC
|
|
+#define CONFIG_FSL_ESDHC
|
|
+#define CONFIG_FSL_USDHC
|
|
+
|
|
+#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
|
|
+#define CONFIG_SYS_FSL_USDHC_NUM 1
|
|
+#else
|
|
+#define CONFIG_SYS_FSL_USDHC_NUM 2
|
|
+#endif
|
|
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
|
+
|
|
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
|
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
|
+
|
|
+#ifdef CONFIG_FSL_FSPI
|
|
+#define CONFIG_SF_DEFAULT_BUS 0
|
|
+#define CONFIG_SF_DEFAULT_CS 0
|
|
+#define CONFIG_SF_DEFAULT_SPEED 40000000
|
|
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
|
+#define FSL_FSPI_FLASH_SIZE SZ_32M
|
|
+#define FSL_FSPI_FLASH_NUM 1
|
|
+#define FSPI0_BASE_ADDR 0x30bb0000
|
|
+#define FSPI0_AMBA_BASE 0x0
|
|
+#define CONFIG_SPI_FLASH_BAR
|
|
+#define CONFIG_FSPI_QUAD_SUPPORT
|
|
+
|
|
+#define CONFIG_SYS_FSL_FSPI_AHB
|
|
+#endif
|
|
+
|
|
+/* Enable SPI */
|
|
+#ifndef CONFIG_NAND_MXS
|
|
+#ifndef CONFIG_FSL_FSPI
|
|
+#ifdef CONFIG_CMD_SF
|
|
+#define CONFIG_SPI_FLASH
|
|
+#define CONFIG_SPI_FLASH_STMICRO
|
|
+#define CONFIG_MXC_SPI
|
|
+#define CONFIG_SF_DEFAULT_BUS 0
|
|
+#define CONFIG_SF_DEFAULT_SPEED 20000000
|
|
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
|
+#endif
|
|
+#endif
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_CMD_NAND
|
|
+#define CONFIG_NAND_MXS
|
|
+#define CONFIG_CMD_NAND_TRIMFFS
|
|
+
|
|
+/* NAND stuff */
|
|
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
+#define CONFIG_SYS_NAND_BASE 0x20000000
|
|
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
|
+#define CONFIG_SYS_NAND_ONFI_DETECTION
|
|
+
|
|
+/* DMA stuff, needed for GPMI/MXS NAND support */
|
|
+#define CONFIG_APBH_DMA
|
|
+#define CONFIG_APBH_DMA_BURST
|
|
+#define CONFIG_APBH_DMA_BURST8
|
|
+
|
|
+#ifdef CONFIG_CMD_UBI
|
|
+#define CONFIG_MTD_PARTITIONS
|
|
+#define CONFIG_MTD_DEVICE
|
|
+#endif
|
|
+#endif /* CONFIG_CMD_NAND */
|
|
+
|
|
+
|
|
+#define CONFIG_MXC_GPIO
|
|
+
|
|
+#define CONFIG_MXC_OCOTP
|
|
+#define CONFIG_CMD_FUSE
|
|
+
|
|
+#ifndef CONFIG_DM_I2C
|
|
+#define CONFIG_SYS_I2C
|
|
+#endif
|
|
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
|
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
|
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
|
+#define CONFIG_SYS_I2C_SPEED 100000
|
|
+
|
|
+/* USB configs */
|
|
+#ifndef CONFIG_SPL_BUILD
|
|
+#define CONFIG_CMD_USB
|
|
+#define CONFIG_USB_STORAGE
|
|
+#define CONFIG_USBD_HS
|
|
+
|
|
+#define CONFIG_CMD_USB_MASS_STORAGE
|
|
+#define CONFIG_USB_GADGET_MASS_STORAGE
|
|
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
|
+
|
|
+#endif
|
|
+
|
|
+#define CONFIG_USB_GADGET_DUALSPEED
|
|
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
|
+
|
|
+#define CONFIG_CI_UDC
|
|
+
|
|
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
|
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
|
+
|
|
+#ifdef CONFIG_VIDEO
|
|
+#define CONFIG_VIDEO_MXS
|
|
+#define CONFIG_VIDEO_LOGO
|
|
+#define CONFIG_SPLASH_SCREEN
|
|
+#define CONFIG_SPLASH_SCREEN_ALIGN
|
|
+#define CONFIG_CMD_BMP
|
|
+#define CONFIG_BMP_16BPP
|
|
+#define CONFIG_VIDEO_BMP_RLE8
|
|
+#define CONFIG_VIDEO_BMP_LOGO
|
|
+#define CONFIG_IMX_VIDEO_SKIP
|
|
+#define CONFIG_RM67191
|
|
+#endif
|
|
+
|
|
+#define CONFIG_OF_SYSTEM_SETUP
|
|
+
|
|
+#if defined(CONFIG_ANDROID_SUPPORT)
|
|
+#include "imx8mm_evk_android.h"
|
|
+#endif
|
|
+#endif
|
|
Index: u-boot-imx/configs/imx8mm_tgr_defconfig
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/configs/imx8mm_tgr_defconfig
|
|
@@ -0,0 +1,70 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_ARCH_IMX8M=y
|
|
+CONFIG_SYS_TEXT_BASE=0x40200000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|
+CONFIG_TARGET_TGR=y
|
|
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000"
|
|
+CONFIG_FIT=y
|
|
+CONFIG_SPL_LOAD_FIT=y
|
|
+CONFIG_ARCH_MISC_INIT=y
|
|
+CONFIG_SPL=y
|
|
+CONFIG_SPL_BOARD_INIT=y
|
|
+CONFIG_SPL_MMC_SUPPORT=y
|
|
+CONFIG_HUSH_PARSER=y
|
|
+CONFIG_OF_LIBFDT=y
|
|
+CONFIG_FS_FAT=y
|
|
+CONFIG_CMD_EXT2=y
|
|
+CONFIG_CMD_EXT4=y
|
|
+CONFIG_CMD_EXT4_WRITE=y
|
|
+CONFIG_CMD_FAT=y
|
|
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-tgr"
|
|
+CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-tgr"
|
|
+CONFIG_ENV_IS_IN_MMC=y
|
|
+CONFIG_CMD_SF=y
|
|
+CONFIG_CMD_I2C=y
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_CACHE=y
|
|
+CONFIG_CMD_REGULATOR=y
|
|
+CONFIG_CMD_MEMTEST=y
|
|
+CONFIG_OF_CONTROL=y
|
|
+CONFIG_FASTBOOT=y
|
|
+CONFIG_USB_FUNCTION_FASTBOOT=y
|
|
+CONFIG_CMD_FASTBOOT=y
|
|
+CONFIG_ANDROID_BOOT_IMAGE=y
|
|
+CONFIG_FSL_FASTBOOT=y
|
|
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
|
|
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
|
|
+CONFIG_FASTBOOT_FLASH=y
|
|
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
|
|
+
|
|
+CONFIG_DM_GPIO=y
|
|
+CONFIG_DM_I2C=y
|
|
+CONFIG_SYS_I2C_MXC=y
|
|
+CONFIG_DM_MMC=y
|
|
+# CONFIG_DM_PMIC=y
|
|
+CONFIG_EFI_PARTITION=y
|
|
+CONFIG_DM_SPI_FLASH=y
|
|
+CONFIG_SPI_FLASH=y
|
|
+CONFIG_SPI_FLASH_STMICRO=y
|
|
+CONFIG_DM_ETH=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCTRL_IMX8M=y
|
|
+CONFIG_DM_REGULATOR=y
|
|
+CONFIG_DM_REGULATOR_FIXED=y
|
|
+CONFIG_DM_REGULATOR_GPIO=y
|
|
+CONFIG_DM_SPI=y
|
|
+CONFIG_FSL_FSPI=y
|
|
+CONFIG_NXP_TMU=y
|
|
+CONFIG_DM_THERMAL=y
|
|
+CONFIG_USB=y
|
|
+CONFIG_USB_GADGET=y
|
|
+CONFIG_DM_USB=y
|
|
+CONFIG_USB_EHCI_HCD=y
|
|
+
|
|
+CONFIG_SPL_USB_HOST_SUPPORT=y
|
|
+CONFIG_SPL_USB_GADGET_SUPPORT=y
|
|
+CONFIG_SPL_USB_SDP_SUPPORT=y
|
|
+CONFIG_SDP_LOADADDR=0x40400000
|
|
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
|
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
|
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
|
Index: u-boot-imx/drivers/power/pmic/Kconfig
|
|
===================================================================
|
|
--- u-boot-imx.orig/drivers/power/pmic/Kconfig
|
|
+++ u-boot-imx/drivers/power/pmic/Kconfig
|
|
@@ -55,6 +55,13 @@ config DM_PMIC_BD71837
|
|
This config enables implementation of driver-model pmic uclass features
|
|
for PMIC BD71837. The driver implements read/write operations.
|
|
|
|
+config DM_PMIC_PCA9450
|
|
+ bool "Enable Driver Model for PMIC PCA9450"
|
|
+ depends on DM_PMIC
|
|
+ help
|
|
+ This config enables implementation of driver-model pmic uclass features
|
|
+ for PMIC PCA9450. The driver implements read/write operations.
|
|
+
|
|
config DM_PMIC_PFUZE100
|
|
bool "Enable Driver Model for PMIC PFUZE100"
|
|
depends on DM_PMIC
|
|
Index: u-boot-imx/drivers/power/pmic/Makefile
|
|
===================================================================
|
|
--- u-boot-imx.orig/drivers/power/pmic/Makefile
|
|
+++ u-boot-imx/drivers/power/pmic/Makefile
|
|
@@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max776
|
|
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
|
|
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
|
|
obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
|
|
+obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o
|
|
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
|
|
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
|
|
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
|
|
@@ -32,6 +33,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8
|
|
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
|
|
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
|
|
obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o
|
|
+obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
|
|
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
|
|
obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
|
|
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
|
|
Index: u-boot-imx/drivers/power/pmic/pca9450.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/drivers/power/pmic/pca9450.c
|
|
@@ -0,0 +1,92 @@
|
|
+/*
|
|
+ * Copyright 2019 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <fdtdec.h>
|
|
+#include <errno.h>
|
|
+#include <dm.h>
|
|
+#include <i2c.h>
|
|
+#include <power/pmic.h>
|
|
+#include <power/regulator.h>
|
|
+#include <power/pca9450.h>
|
|
+
|
|
+DECLARE_GLOBAL_DATA_PTR;
|
|
+
|
|
+static const struct pmic_child_info pmic_children_info[] = {
|
|
+ /* buck */
|
|
+ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER},
|
|
+ /* ldo */
|
|
+ { .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER},
|
|
+ { },
|
|
+};
|
|
+
|
|
+static int pca9450_reg_count(struct udevice *dev)
|
|
+{
|
|
+ return PCA9450_REG_NUM;
|
|
+}
|
|
+
|
|
+static int pca9450_write(struct udevice *dev, uint reg, const uint8_t *buff,
|
|
+ int len)
|
|
+{
|
|
+ if (dm_i2c_write(dev, reg, buff, len)) {
|
|
+ pr_err("write error to device: %p register: %#x!", dev, reg);
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int pca9450_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
|
|
+{
|
|
+ if (dm_i2c_read(dev, reg, buff, len)) {
|
|
+ pr_err("read error from device: %p register: %#x!", dev, reg);
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int pca9450_bind(struct udevice *dev)
|
|
+{
|
|
+ int children;
|
|
+ ofnode regulators_node;
|
|
+
|
|
+ regulators_node = dev_read_subnode(dev, "regulators");
|
|
+ if (!ofnode_valid(regulators_node)) {
|
|
+ debug("%s: %s regulators subnode not found!", __func__,
|
|
+ dev->name);
|
|
+ return -ENXIO;
|
|
+ }
|
|
+
|
|
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
|
|
+
|
|
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
|
|
+ if (!children)
|
|
+ debug("%s: %s - no child found\n", __func__, dev->name);
|
|
+
|
|
+ /* Always return success for this device */
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct dm_pmic_ops pca9450_ops = {
|
|
+ .reg_count = pca9450_reg_count,
|
|
+ .read = pca9450_read,
|
|
+ .write = pca9450_write,
|
|
+};
|
|
+
|
|
+static const struct udevice_id pca9450_ids[] = {
|
|
+ { .compatible = "nxp,pca9450a", .data = 0x35, },
|
|
+ { .compatible = "nxp,pca9450b", .data = 0x25, },
|
|
+ { }
|
|
+};
|
|
+
|
|
+U_BOOT_DRIVER(pmic_pca9450) = {
|
|
+ .name = "pca9450 pmic",
|
|
+ .id = UCLASS_PMIC,
|
|
+ .of_match = pca9450_ids,
|
|
+ .bind = pca9450_bind,
|
|
+ .ops = &pca9450_ops,
|
|
+};
|
|
Index: u-boot-imx/drivers/power/pmic/pmic_pca9450.c
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/drivers/power/pmic/pmic_pca9450.c
|
|
@@ -0,0 +1,52 @@
|
|
+/*
|
|
+ * Copyright 2019 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <errno.h>
|
|
+#include <i2c.h>
|
|
+#include <power/pmic.h>
|
|
+#include <power/pca9450.h>
|
|
+
|
|
+static const char pca9450_name[] = "PCA9450";
|
|
+int power_pca9450a_init (unsigned char bus) {
|
|
+ struct pmic *p = pmic_alloc();
|
|
+
|
|
+ if (!p) {
|
|
+ printf("%s: POWER allocation error!\n", __func__);
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ p->name = pca9450_name;
|
|
+ p->interface = PMIC_I2C;
|
|
+ p->number_of_regs = PCA9450_REG_NUM;
|
|
+ p->hw.i2c.addr = 0x35;
|
|
+ p->hw.i2c.tx_num = 1;
|
|
+ p->bus = bus;
|
|
+
|
|
+ printf("power_pca9450a_init\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int power_pca9450b_init (unsigned char bus) {
|
|
+ struct pmic *p = pmic_alloc();
|
|
+
|
|
+ if (!p) {
|
|
+ printf("%s: POWER allocation error!\n", __func__);
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ p->name = pca9450_name;
|
|
+ p->interface = PMIC_I2C;
|
|
+ p->number_of_regs = PCA9450_REG_NUM;
|
|
+ p->hw.i2c.addr = 0x25;
|
|
+ p->hw.i2c.tx_num = 1;
|
|
+ p->bus = bus;
|
|
+
|
|
+ printf("power_pca9450b_init\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
Index: u-boot-imx/include/power/pca9450.h
|
|
===================================================================
|
|
--- /dev/null
|
|
+++ u-boot-imx/include/power/pca9450.h
|
|
@@ -0,0 +1,61 @@
|
|
+/*
|
|
+ * Copyright 2019 NXP
|
|
+ *
|
|
+ * SPDX-License-Identifier: GPL-2.0+
|
|
+ */
|
|
+
|
|
+#ifndef PCA9450_H_
|
|
+#define PCA9450_H_
|
|
+
|
|
+#define PCA9450_REGULATOR_DRIVER "pca9450_regulator"
|
|
+
|
|
+enum {
|
|
+ PCA9450_REG_DEV_ID = 0x00,
|
|
+ PCA9450_INT1 = 0x01,
|
|
+ PCA9450_INT1_MSK = 0x02,
|
|
+ PCA9450_STATUS1 = 0x03,
|
|
+ PCA9450_STATUS2 = 0x04,
|
|
+ PCA9450_PWRON_STAT = 0x05,
|
|
+ PCA9450_SW_RST = 0x06,
|
|
+ PCA9450_PWR_CTRL = 0x07,
|
|
+ PCA9450_RESET_CTRL = 0x08,
|
|
+ PCA9450_CONFIG1 = 0x09,
|
|
+ PCA9450_CONFIG2 = 0x0A,
|
|
+ PCA9450_BUCK123_DVS = 0x0C,
|
|
+ PCA9450_BUCK1OUT_LIMIT = 0x0D,
|
|
+ PCA9450_BUCK2OUT_LIMIT = 0x0E,
|
|
+ PCA9450_BUCK3OUT_LIMIT = 0x0F,
|
|
+ PCA9450_BUCK1CTRL = 0x10,
|
|
+ PCA9450_BUCK1OUT_DVS0 = 0x11,
|
|
+ PCA9450_BUCK1OUT_DVS1 = 0x12,
|
|
+ PCA9450_BUCK2CTRL = 0x13,
|
|
+ PCA9450_BUCK2OUT_DVS0 = 0x14,
|
|
+ PCA9450_BUCK2OUT_DVS1 = 0x15,
|
|
+ PCA9450_BUCK3CTRL = 0x16,
|
|
+ PCA9450_BUCK3OUT_DVS0 = 0x17,
|
|
+ PCA9450_BUCK3OUT_DVS1 = 0x18,
|
|
+ PCA9450_BUCK4CTRL = 0x19,
|
|
+ PCA9450_BUCK4OUT = 0x1A,
|
|
+ PCA9450_BUCK5CTRL = 0x1B,
|
|
+ PCA9450_BUCK5OUT = 0x1C,
|
|
+ PCA9450_BUCK6CTRL = 0x1D,
|
|
+ PCA9450_BUCK6OUT = 0x1E,
|
|
+ PCA9450_LDO_AD_CTRL = 0x20,
|
|
+ PCA9450_LDO1CTRL = 0x21,
|
|
+ PCA9450_LDO2CTRL = 0x22,
|
|
+ PCA9450_LDO3CTRL = 0x23,
|
|
+ PCA9450_LDO4CTRL = 0x24,
|
|
+ PCA9450_LDO5CTRL_L = 0x25,
|
|
+ PCA9450_LDO5CTRL_H = 0x26,
|
|
+ PCA9450_LOADSW_CTRL = 0x2A,
|
|
+ PCA9450_VRFLT1_STS = 0x2B,
|
|
+ PCA9450_VRFLT2_STS = 0x2C,
|
|
+ PCA9450_VRFLT1_MASK = 0x2D,
|
|
+ PCA9450_VRFLT2_MASK = 0x2E,
|
|
+ PCA9450_REG_NUM,
|
|
+};
|
|
+
|
|
+int power_pca9450a_init(unsigned char bus);
|
|
+int power_pca9450b_init(unsigned char bus);
|
|
+
|
|
+#endif
|