Merge pull request #148 from filberg/master

Upgrade kernel to 5.4.y LTS

makefile

@@ -13,7 +13,7 @@
 # You should have received a copy of the GNU General Public License
 # along with PrawnOS.  If not, see <https://www.gnu.org/licenses/>.
 
-KVER=5.2.21
+KVER=5.4.23
 ifeq ($(DEBIAN_SUITE),)
 DEBIAN_SUITE=buster
 endif
@@ -92,6 +92,12 @@ filesystem:
 kernel_inject: #Targets an already built .img and swaps the old kernel with the newly compiled kernel
 	scripts/injectKernelIntoFS.sh $(KVER) $(OUTNAME)
 
+.PHONY: kernel_update
+kernel_update:
+	make initramfs
+	make kernel
+	make kernel_inject
+
 .PHONY: injected_image
 injected_image: #makes a copy of the base image with a new injected kernel
 	make kernel

resources/BuildResources/patches-tested/DTS/0008-revert-rockchip-add-startup-delay-to-veyron-panel-regulators.patch

@@ -1,91 +0,0 @@
-commit	f72b90279db4b34aa18c97be826014b611969509	[log] [tgz]
-author	Douglas Anderson <dianders@chromium.org>	Thu Jun 20 18:20:56 2019
-committer	Commit Bot <commit-bot@chromium.org>	Wed Jul 10 18:03:58 2019
-tree	8380fa218796abf5c89be797a6af2de31d5b897c
-parent	46f55c559e7163fbf283c96bfd993d22431aa6fc [diff]
-
-FROMLIST: Revert "ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators"
-
-This reverts commit 1f45e8c6d0161f044d679f242fe7514e2625af4a.
-
-This 100 ms mystery delay is not on downstream kernels and no longer
-seems needed on upstream kernels either [1].  Presumably something in the
-meantime has made things better.  A few possibilities for patches that
-have landed in the meantime that could have made this better are
-commit 3157694d8c7f ("pwm-backlight: Add support for PWM delays
-proprieties."), commit 5fb5caee92ba ("pwm-backlight: Enable/disable
-the PWM before/after LCD enable toggle."), and commit 6d5922dd0d60
-("ARM: dts: rockchip: set PWM delay backlight settings for Veyron")
-
-Let's revert and get our 100 ms back.
-
-[1] https://lkml.kernel.org/r/2226970.BAPq4liE1j@diego
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-(am from https://lore.kernel.org/patchwork/patch/1091867/)
-(also found at https://lkml.kernel.org/r/20190620182056.61552-1-dianders@chromium.org)
-
-BUG=chromium:941638
-TEST=Lots of reboot tests; check eDP comes up
-
-Change-Id: I05638f852b8e278907dda813ca19d1eb81de14e5
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1693736
-Reviewed-by: Sean Paul <seanpaul@chromium.org>
-Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
-index 367db7e..bd97dae 100644
---- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
-
-@@ -25,7 +25,6 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&lcd_enable_h>;
- 		regulator-name = "panel_regulator";
--		startup-delay-us = <100000>;
- 		vin-supply = <&vcc33_sys>;
- 	};
- 
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
-index 983a25f..9c78537e 100644
---- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
-
-@@ -27,7 +27,6 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&lcd_enable_h>;
- 		regulator-name = "panel_regulator";
--		startup-delay-us = <100000>;
- 		vin-supply = <&vcc33_sys>;
- 	};
- 
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
-index 62bb12b..5a9bd39 100644
---- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
-
-@@ -34,7 +34,6 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&lcd_enable_h>;
- 		regulator-name = "panel_regulator";
--		startup-delay-us = <100000>;
- 		vin-supply = <&vcc33_sys>;
- 	};
- 
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-index aea10b6..cb37543 100644
---- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-
-@@ -25,7 +25,6 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&lcd_enable_h>;
- 		regulator-name = "panel_regulator";
--		startup-delay-us = <100000>;
- 		vin-supply = <&vcc33_sys>;
- 	};
- 

resources/BuildResources/patches-tested/DTS/5.x-dts/0028-ARM-dts-rockchip-fix-PWM-clock-found-on-RK3288-Socs.patch

@@ -1,57 +0,0 @@
-From 6773af2684b7bc1b7b2d9ef874599cccaba2559e Mon Sep 17 00:00:00 2001
-From: Caesar Wang <caesar.wang@rock-chips.com>
-Date: Tue, 9 Apr 2019 13:47:07 -0700
-Subject: [PATCH 28/54] ARM: dts: rockchip: fix PWM clock found on RK3288 Socs
-
-We use the new PWM IP on RK3288, but the PWM's clock indeed incorrect.
-
-Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index aa017abf4f42..171231a0cd9b 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -682,7 +682,7 @@
- 		#pwm-cells = <3>;
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pwm0_pin>;
--		clocks = <&cru PCLK_PWM>;
-+		clocks = <&cru PCLK_RKPWM>;
- 		clock-names = "pwm";
- 		status = "disabled";
- 	};
-@@ -693,7 +693,7 @@
- 		#pwm-cells = <3>;
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pwm1_pin>;
--		clocks = <&cru PCLK_PWM>;
-+		clocks = <&cru PCLK_RKPWM>;
- 		clock-names = "pwm";
- 		status = "disabled";
- 	};
-@@ -704,7 +704,7 @@
- 		#pwm-cells = <3>;
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pwm2_pin>;
--		clocks = <&cru PCLK_PWM>;
-+		clocks = <&cru PCLK_RKPWM>;
- 		clock-names = "pwm";
- 		status = "disabled";
- 	};
-@@ -715,7 +715,7 @@
- 		#pwm-cells = <2>;
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pwm3_pin>;
--		clocks = <&cru PCLK_PWM>;
-+		clocks = <&cru PCLK_RKPWM>;
- 		clock-names = "pwm";
- 		status = "disabled";
- 	};
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0029-ARM-dts-rockchip-Remove-bogus-i2s_clk_out-from-rk328.patch

@@ -1,42 +0,0 @@
-From d190bfaaa2a1575e7998d8487ed26cdf9e74b42b Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Fri, 3 May 2019 16:48:14 -0700
-Subject: [PATCH 29/54] ARM: dts: rockchip: Remove bogus 'i2s_clk_out' from
- rk3288-veyron-mickey
-
-The rk3288-veyron-mickey device tree overrides the default "i2s" clock
-settings to add the clock for "i2s_clk_out".
-
-That clock is only present in the bindings downstream Chrome OS 3.14
-tree.  Upstream the i2s port bindings doesn't specify that as a
-possible clock.
-
-Let's remove it.
-
-NOTE: for other rk3288-veyron devices this clock is consumed by
-'maxim,max98090'.  Presumably if this clock is needed for mickey it'll
-need to be consumed by something similar.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron-mickey.dts | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
-index e852594417b5..f9c4ece3c0d3 100644
---- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
-@@ -142,8 +142,6 @@
- 
- &i2s {
- 	status = "okay";
--	clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
--	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
- };
- 
- &rk808 {
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0032-ARM-dts-rockchip-raise-CPU-trip-point-temperature-fo.patch

@@ -1,66 +0,0 @@
-From 83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775 Mon Sep 17 00:00:00 2001
-From: Matthias Kaehlcke <mka@chromium.org>
-Date: Thu, 16 May 2019 09:29:40 -0700
-Subject: [PATCH 32/54] ARM: dts: rockchip: raise CPU trip point temperature
- for veyron to 100 degC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This value matches what is used by the downstream Chrome OS 3.14
-kernel, the 'official' kernel for veyron devices. Keep the temperature
-for 'speedy' at 90°C, as in the downstream kernel.
-
-Increase the temperature for a hardware shutdown to 125°C, which
-matches the downstream configuration and gives the system a chance
-to shut down orderly at the criticial trip point.
-
-Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++
- arch/arm/boot/dts/rk3288-veyron.dtsi       | 5 +++++
- 2 files changed, 9 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-index 2ac8748a3a0c..b07a07e81551 100644
---- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-@@ -64,6 +64,10 @@
- 	temperature = <70000>;
- };
- 
-+&cpu_crit {
-+	temperature = <90000>;
-+};
-+
- &edp {
- 	/delete-property/pinctrl-names;
- 	/delete-property/pinctrl-0;
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index 1252522392c7..e81f1a0cac83 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -123,6 +123,10 @@
- 	cpu0-supply = <&vdd_cpu>;
- };
- 
-+&cpu_crit {
-+	temperature = <100000>;
-+};
-+
- /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
- &cpu_opp_table {
- 	/delete-node/ opp-312000000;
-@@ -394,6 +398,7 @@
- 
- 	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
- 	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
-+	rockchip,hw-tshut-temp = <125000>;
- };
- 
- &uart0 {
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0033-ARM-dts-rockchip-raise-GPU-trip-point-temperatures-f.patch

@@ -1,58 +0,0 @@
-From 0f637e2565d175eeff664991be9a6d0753d0e484 Mon Sep 17 00:00:00 2001
-From: Matthias Kaehlcke <mka@chromium.org>
-Date: Thu, 16 May 2019 09:29:41 -0700
-Subject: [PATCH 33/54] ARM: dts: rockchip: raise GPU trip point temperatures
- for veyron
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The values match those used by the downstream Chrome OS 3.14
-kernel, the 'official' kernel for veyron devices. Keep the critical
-trip point for speedy at 90°C as in the downstream configuration.
-
-Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 ++++
- arch/arm/boot/dts/rk3288-veyron.dtsi       | 8 ++++++++
- 2 files changed, 12 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-index b07a07e81551..aae37c535444 100644
---- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-@@ -75,6 +75,10 @@
- 	force-hpd;
- };
- 
-+&gpu_crit {
-+	temperature = <90000>;
-+};
-+
- &panel {
- 	power-supply= <&panel_regulator>;
- };
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index e81f1a0cac83..90c8312d01ff 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -166,6 +166,14 @@
- 	status = "okay";
- };
- 
-+&gpu_alert0 {
-+	temperature = <72500>;
-+};
-+
-+&gpu_crit {
-+	temperature = <100000>;
-+};
-+
- &hdmi {
- 	ddc-i2c-bus = <&i2c5>;
- 	status = "okay";
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0038-ARM-dts-rockchip-Add-cooling-cells-entry-for-rk3288-.patch

@@ -1,31 +0,0 @@
-From f6dcbb3ad5ce927adbdcc04bde312387f3b68035 Mon Sep 17 00:00:00 2001
-From: Matthias Kaehlcke <mka@chromium.org>
-Date: Thu, 16 May 2019 10:25:09 -0700
-Subject: [PATCH 38/54] ARM: dts: rockchip: Add #cooling-cells entry for rk3288
- GPU
-
-The Mali GPU of the rk3288 can be used as cooling device, add
-a #cooling-cells entry for it.
-
-Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index 1e5260b556b7..7e9b8c7f6ab7 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -1286,6 +1286,7 @@
- 		interrupt-names = "job", "mmu", "gpu";
- 		clocks = <&cru ACLK_GPU>;
- 		operating-points-v2 = <&gpu_opp_table>;
-+		#cooling-cells = <2>; /* min followed by max */
- 		power-domains = <&power RK3288_PD_GPU>;
- 		status = "disabled";
- 	};
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0039-ARM-dts-rockchip-Use-GPU-as-cooling-device-for-the-G.patch

@@ -1,40 +0,0 @@
-From ae2b6ba865d8bb59493aaf50cb3d19312a6ff5a4 Mon Sep 17 00:00:00 2001
-From: Matthias Kaehlcke <mka@chromium.org>
-Date: Thu, 16 May 2019 10:25:10 -0700
-Subject: [PATCH 39/54] ARM: dts: rockchip: Use GPU as cooling device for the
- GPU thermal zone of the rk3288
-
-Currently the CPUs are used as cooling devices of the rk3288 GPU
-thermal zone. The CPUs are also configured as cooling devices in the
-CPU thermal zone, which indirectly helps with cooling the GPU thermal
-zone, since the CPU and GPU temperatures are correlated on the rk3288.
-
-Configure the ARM Mali Midgard GPU as cooling device for the GPU
-thermal zone instead of the CPUs.
-
-Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288.dtsi | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index 7e9b8c7f6ab7..fd188bb4fd48 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -552,10 +552,7 @@
- 				map0 {
- 					trip = <&gpu_alert0>;
- 					cooling-device =
--						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 				};
- 			};
- 		};
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0040-ARM-dts-rockchip-remove-GPU-500-MHz-OPP-on-rk3288.patch

@@ -1,41 +0,0 @@
-From 75481833c6dbab4c29d15452f6b4337c16f5407b Mon Sep 17 00:00:00 2001
-From: Matthias Kaehlcke <mka@chromium.org>
-Date: Mon, 20 May 2019 15:00:49 -0700
-Subject: [PATCH 40/54] ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288
-
-The NPLL is the only safe way to generate 500 MHz for the GPU. The
-downstream Chrome OS 3.14 kernel ('official' kernel for veyron
-devices) re-purposes NPLL to HDMI and hence disables the OPP for
-the GPU (see https://crrev.com/c/1574579). Disable it here as well
-to keep in sync and avoid problems in case someone decides to
-re-purpose NPLL.
-
-Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-[moved from veyron to general rk3288, as tying up the NPLL for a
- not-that-helpful opp (not really fast but will still generate
- quite a bit of heat) doesn't make so much sense when it will
- keep us from supporting other display modes  in the future]
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288.dtsi | 4 ----
- 1 file changed, 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index fd188bb4fd48..159d91180cee 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -1307,10 +1307,6 @@
- 			opp-hz = /bits/ 64 <400000000>;
- 			opp-microvolt = <1100000>;
- 		};
--		opp-500000000 {
--			opp-hz = /bits/ 64 <500000000>;
--			opp-microvolt = <1200000>;
--		};
- 		opp-600000000 {
- 			opp-hz = /bits/ 64 <600000000>;
- 			opp-microvolt = <1250000>;
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0043-ARM-dts-rockchip-fix-pwm-cells-for-rk3288-s-pwm3.patch

@@ -1,29 +0,0 @@
-From 9dbf05bd8ae5b436b02c9845a350dec11c788a73 Mon Sep 17 00:00:00 2001
-From: John Keeping <john@metanate.com>
-Date: Mon, 3 Jun 2019 15:34:35 +0100
-Subject: [PATCH 43/54] ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3
-
-This is the same as the other PWMs on this SoC and uses 3 cells.
-
-Signed-off-by: John Keeping <john@metanate.com>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index 159d91180cee..766d1cf51a5b 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -710,7 +710,7 @@
- 	pwm3: pwm@ff680030 {
- 		compatible = "rockchip,rk3288-pwm";
- 		reg = <0x0 0xff680030 0x0 0x10>;
--		#pwm-cells = <2>;
-+		#pwm-cells = <3>;
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pwm3_pin>;
- 		clocks = <&cru PCLK_RKPWM>;
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0044-ARM-dts-rockchip-Add-pin-names-for-rk3288-veyron-jaq.patch

@@ -1,637 +0,0 @@
-From d85b2ad35a2ab320b9c0530992ee532f10a6aeb2 Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Fri, 24 May 2019 16:33:09 -0700
-Subject: [PATCH 44/54] ARM: dts: rockchip: Add pin names for rk3288-veyron
- jaq, mickey, speedy
-
-This is like commit 0ca87bd5baa6 ("ARM: dts: rockchip: Add pin names
-for rk3288-veyron-jerry") and commit ca3516b32cd9 ("ARM: dts:
-rockchip: Add pin names for rk3288-veyron-minnie") but for 3 more
-veyron boards.
-
-A few notes:
-- While there is most certainly duplication between all the veyron
-  boards, it still feels like it is sane to just have each board have
-  a full list of its pin names.  The format of "gpio-line-names" does
-  not lend itself to one-off overriding and besides it seems sane to
-  more fully match schematic names.  Also note that the extra
-  duplication here is only in source code and is unlikely to ever
-  change (since these boards are shipped).  Duplication in the .dtb
-  files is unavoidable.
-- veyron-jaq and veyron-mighty are very closely related and so I have
-  shared a single list for them both with comments on how they are
-  different.  This is just a typo fix on one of the boards, a possible
-  missing signal on one of the boards (or perhaps I was never given
-  the most recent schematics?) and dealing with the fact that one of
-  the two boards has full sized SD.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron-jaq.dts    | 207 +++++++++++++++++++++++++++++
- arch/arm/boot/dts/rk3288-veyron-mickey.dts | 151 +++++++++++++++++++++
- arch/arm/boot/dts/rk3288-veyron-speedy.dts | 207 +++++++++++++++++++++++++++++
- 3 files changed, 565 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
-index e248f55ee8d2..fcd119168cb6 100644
---- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
-@@ -135,6 +135,213 @@
- 	pinctrl-0 = <&vcc50_hdmi_en>;
- };
- 
-+&gpio0 {
-+	gpio-line-names = "PMIC_SLEEP_AP",
-+			  "DDRIO_PWROFF",
-+			  "DDRIO_RETEN",
-+			  "TS3A227E_INT_L",
-+			  "PMIC_INT_L",
-+			  "PWR_KEY_L",
-+			  "AP_LID_INT_L",
-+			  "EC_IN_RW",
-+
-+			  "AC_PRESENT_AP",
-+			  /*
-+			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
-+			   * it REC_MODE_L.
-+			   */
-+			  "RECOVERY_SW_L",
-+			  "OTP_OUT",
-+			  "HOST1_PWR_EN",
-+			  "USBOTG_PWREN_H",
-+			  "AP_WARM_RESET_H",
-+			  "nFALUT2",
-+			  "I2C0_SDA_PMIC",
-+
-+			  "I2C0_SCL_PMIC",
-+			  "SUSPEND_L",
-+			  "USB_INT";
-+};
-+
-+&gpio2 {
-+	gpio-line-names = "CONFIG0",
-+			  "CONFIG1",
-+			  "CONFIG2",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "CONFIG3",
-+
-+			  "",
-+			  "EMMC_RST_L",
-+			  "",
-+			  "",
-+			  "BL_PWR_EN",
-+			  "AVDD_1V8_DISP_EN";
-+};
-+
-+&gpio3 {
-+	gpio-line-names = "FLASH0_D0",
-+			  "FLASH0_D1",
-+			  "FLASH0_D2",
-+			  "FLASH0_D3",
-+			  "FLASH0_D4",
-+			  "FLASH0_D5",
-+			  "FLASH0_D6",
-+			  "FLASH0_D7",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "FLASH0_CS2/EMMC_CMD",
-+			  "",
-+			  "FLASH0_DQS/EMMC_CLKO";
-+};
-+
-+&gpio4 {
-+	gpio-line-names = "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "UART0_RXD",
-+			  "UART0_TXD",
-+			  "UART0_CTS",
-+			  "UART0_RTS",
-+			  "SDIO0_D0",
-+			  "SDIO0_D1",
-+			  "SDIO0_D2",
-+			  "SDIO0_D3",
-+
-+			  "SDIO0_CMD",
-+			  "SDIO0_CLK",
-+			  "BT_DEV_WAKE",	/* Maybe missing from mighty? */
-+			  "",
-+			  "WIFI_ENABLE_H",
-+			  "BT_ENABLE_L",
-+			  "WIFI_HOST_WAKE",
-+			  "BT_HOST_WAKE";
-+};
-+
-+&gpio5 {
-+	gpio-line-names = "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "SPI0_CLK",
-+			  "SPI0_CS0",
-+			  "SPI0_TXD",
-+			  "SPI0_RXD",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "VCC50_HDMI_EN";
-+};
-+
-+&gpio6 {
-+	gpio-line-names = "I2S0_SCLK",
-+			  "I2S0_LRCK_RX",
-+			  "I2S0_LRCK_TX",
-+			  "I2S0_SDI",
-+			  "I2S0_SDO0",
-+			  "HP_DET_H",
-+			  "ALS_INT",
-+			  "INT_CODEC",
-+
-+			  "I2S0_CLK",
-+			  "I2C2_SDA",
-+			  "I2C2_SCL",
-+			  "MICDET",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "SDMMC_D0",
-+			  "SDMMC_D1",
-+			  "SDMMC_D2",
-+			  "SDMMC_D3",
-+			  "SDMMC_CLK",
-+			  "SDMMC_CMD";
-+};
-+
-+&gpio7 {
-+	gpio-line-names = "LCDC_BL",
-+			  "PWM_LOG",
-+			  "BL_EN",
-+			  "TRACKPAD_INT",
-+			  "TPM_INT_H",
-+			  "SDMMC_DET_L",
-+			  /*
-+			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
-+			   * it FW_WP_AP.
-+			   */
-+			  "AP_FLASH_WP_L",
-+			  "EC_INT",
-+
-+			  "CPU_NMI",
-+			  "DVSOK",
-+			  "SDMMC_WP",		/* mighty only */
-+			  "EDP_HPD",
-+			  "DVS1",
-+			  "nFALUT1",		/* nFAULT1 on jaq */
-+			  "LCD_EN",
-+			  "DVS2",
-+
-+			  "VCC5V_GOOD_H",
-+			  "I2C4_SDA_TP",
-+			  "I2C4_SCL_TP",
-+			  "I2C5_SDA_HDMI",
-+			  "I2C5_SCL_HDMI",
-+			  "5V_DRV",
-+			  "UART2_RXD",
-+			  "UART2_TXD";
-+};
-+
-+&gpio8 {
-+	gpio-line-names = "RAM_ID0",
-+			  "RAM_ID1",
-+			  "RAM_ID2",
-+			  "RAM_ID3",
-+			  "I2C1_SDA_TPM",
-+			  "I2C1_SCL_TPM",
-+			  "SPI2_CLK",
-+			  "SPI2_CS0",
-+
-+			  "SPI2_RXD",
-+			  "SPI2_TXD";
-+};
-+
- &pinctrl {
- 	backlight {
- 		bl_pwr_en: bl_pwr_en {
-diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
-index 945e80801292..aa352d40c991 100644
---- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
-@@ -252,6 +252,157 @@
- 	};
- };
- 
-+&gpio0 {
-+	gpio-line-names = "PMIC_SLEEP_AP",
-+			  "",
-+			  "",
-+			  "",
-+			  "PMIC_INT_L",
-+			  "POWER_BUTTON_L",
-+			  "",
-+			  "",
-+
-+			  "",
-+			  /*
-+			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
-+			   * it REC_MODE_L.
-+			   */
-+			  "RECOVERY_SW_L",
-+			  "OT_RESET",
-+			  "",
-+			  "",
-+			  "AP_WARM_RESET_H",
-+			  "",
-+			  "I2C0_SDA_PMIC",
-+
-+			  "I2C0_SCL_PMIC",
-+			  "",
-+			  "nFALUT";
-+};
-+
-+&gpio2 {
-+	gpio-line-names = "CONFIG0",
-+			  "CONFIG1",
-+			  "CONFIG2",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "CONFIG3",
-+
-+			  "",
-+			  "EMMC_RST_L";
-+};
-+
-+&gpio3 {
-+	gpio-line-names = "FLASH0_D0",
-+			  "FLASH0_D1",
-+			  "FLASH0_D2",
-+			  "FLASH0_D3",
-+			  "FLASH0_D4",
-+			  "FLASH0_D5",
-+			  "FLASH0_D6",
-+			  "FLASH0_D7",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "FLASH0_CS2/EMMC_CMD",
-+			  "",
-+			  "FLASH0_DQS/EMMC_CLKO";
-+};
-+
-+&gpio4 {
-+	gpio-line-names = "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "UART0_RXD",
-+			  "UART0_TXD",
-+			  "UART0_CTS_L",
-+			  "UART0_RTS_L",
-+			  "SDIO0_D0",
-+			  "SDIO0_D1",
-+			  "SDIO0_D2",
-+			  "SDIO0_D3",
-+
-+			  "SDIO0_CMD",
-+			  "SDIO0_CLK",
-+			  "BT_DEV_WAKE",
-+			  "",
-+			  "WIFI_ENABLE_H",
-+			  "BT_ENABLE_L",
-+			  "WIFI_HOST_WAKE",
-+			  "BT_HOST_WAKE";
-+};
-+
-+&gpio7 {
-+	gpio-line-names = "",
-+			  "PWM_LOG",
-+			  "",
-+			  "",
-+			  "TPM_INT_H",
-+			  "SDMMC_DET_L",
-+			  /*
-+			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
-+			   * it FW_WP_AP.
-+			   */
-+			  "AP_FLASH_WP_L",
-+			  "",
-+
-+			  "CPU_NMI",
-+			  "DVSOK",
-+			  "HDMI_WAKE",
-+			  "POWER_HDMI_ON",
-+			  "DVS1",
-+			  "",
-+			  "",
-+			  "DVS2",
-+
-+			  "HDMI_CEC",
-+			  "",
-+			  "",
-+			  "I2C5_SDA_HDMI",
-+			  "I2C5_SCL_HDMI",
-+			  "",
-+			  "UART2_RXD",
-+			  "UART2_TXD";
-+};
-+
-+&gpio8 {
-+	gpio-line-names = "RAM_ID0",
-+			  "RAM_ID1",
-+			  "RAM_ID2",
-+			  "RAM_ID3",
-+			  "I2C1_SDA_TPM",
-+			  "I2C1_SCL_TPM",
-+			  "SPI2_CLK",
-+			  "SPI2_CS0",
-+
-+			  "SPI2_RXD",
-+			  "SPI2_TXD";
-+};
-+
- &pinctrl {
- 	hdmi {
- 		power_hdmi_on: power-hdmi-on {
-diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-index 9a87017347ea..9b140db04456 100644
---- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
-@@ -113,6 +113,213 @@
- 	pinctrl-0 = <&vcc50_hdmi_en>;
- };
- 
-+&gpio0 {
-+	gpio-line-names = "PMIC_SLEEP_AP",
-+			  "DDRIO_PWROFF",
-+			  "DDRIO_RETEN",
-+			  "TS3A227E_INT_L",
-+			  "PMIC_INT_L",
-+			  "PWR_KEY_L",
-+			  "AP_LID_INT_L",
-+			  "EC_IN_RW",
-+
-+			  "AC_PRESENT_AP",
-+			  /*
-+			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
-+			   * it REC_MODE_L.
-+			   */
-+			  "RECOVERY_SW_L",
-+			  "OTP_OUT",
-+			  "HOST1_PWR_EN",
-+			  "USBOTG_PWREN_H",
-+			  "AP_WARM_RESET_H",
-+			  "nFALUT2",
-+			  "I2C0_SDA_PMIC",
-+
-+			  "I2C0_SCL_PMIC",
-+			  "SUSPEND_L",
-+			  "USB_INT";
-+};
-+
-+&gpio2 {
-+	gpio-line-names = "CONFIG0",
-+			  "CONFIG1",
-+			  "CONFIG2",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "CONFIG3",
-+
-+			  "PWRLIMIT#_CPU",
-+			  "EMMC_RST_L",
-+			  "",
-+			  "",
-+			  "BL_PWR_EN",
-+			  "AVDD_1V8_DISP_EN";
-+};
-+
-+&gpio3 {
-+	gpio-line-names = "FLASH0_D0",
-+			  "FLASH0_D1",
-+			  "FLASH0_D2",
-+			  "FLASH0_D3",
-+			  "FLASH0_D4",
-+			  "FLASH0_D5",
-+			  "FLASH0_D6",
-+			  "FLASH0_D7",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "FLASH0_CS2/EMMC_CMD",
-+			  "",
-+			  "FLASH0_DQS/EMMC_CLKO";
-+};
-+
-+&gpio4 {
-+	gpio-line-names = "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "UART0_RXD",
-+			  "UART0_TXD",
-+			  "UART0_CTS",
-+			  "UART0_RTS",
-+			  "SDIO0_D0",
-+			  "SDIO0_D1",
-+			  "SDIO0_D2",
-+			  "SDIO0_D3",
-+
-+			  "SDIO0_CMD",
-+			  "SDIO0_CLK",
-+			  "BT_DEV_WAKE",
-+			  "",
-+			  "WIFI_ENABLE_H",
-+			  "BT_ENABLE_L",
-+			  "WIFI_HOST_WAKE",
-+			  "BT_HOST_WAKE";
-+};
-+
-+&gpio5 {
-+	gpio-line-names = "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+			  "SPI0_CLK",
-+			  "SPI0_CS0",
-+			  "SPI0_TXD",
-+			  "SPI0_RXD",
-+
-+			  "",
-+			  "",
-+			  "",
-+			  "VCC50_HDMI_EN";
-+};
-+
-+&gpio6 {
-+	gpio-line-names = "I2S0_SCLK",
-+			  "I2S0_LRCK_RX",
-+			  "I2S0_LRCK_TX",
-+			  "I2S0_SDI",
-+			  "I2S0_SDO0",
-+			  "HP_DET_H",
-+			  "ALS_INT",		/* not connected */
-+			  "INT_CODEC",
-+
-+			  "I2S0_CLK",
-+			  "I2C2_SDA",
-+			  "I2C2_SCL",
-+			  "MICDET",
-+			  "",
-+			  "",
-+			  "",
-+			  "",
-+
-+			  "SDMMC_D0",
-+			  "SDMMC_D1",
-+			  "SDMMC_D2",
-+			  "SDMMC_D3",
-+			  "SDMMC_CLK",
-+			  "SDMMC_CMD";
-+};
-+
-+&gpio7 {
-+	gpio-line-names = "LCDC_BL",
-+			  "PWM_LOG",
-+			  "BL_EN",
-+			  "TRACKPAD_INT",
-+			  "TPM_INT_H",
-+			  "SDMMC_DET_L",
-+			  /*
-+			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
-+			   * it FW_WP_AP.
-+			   */
-+			  "AP_FLASH_WP_L",
-+			  "EC_INT",
-+
-+			  "CPU_NMI",
-+			  "DVS_OK",
-+			  "",
-+			  "EDP_HOTPLUG",
-+			  "DVS1",
-+			  "nFALUT1",
-+			  "LCD_EN",
-+			  "DVS2",
-+
-+			  "VCC5V_GOOD_H",
-+			  "I2C4_SDA_TP",
-+			  "I2C4_SCL_TP",
-+			  "I2C5_SDA_HDMI",
-+			  "I2C5_SCL_HDMI",
-+			  "5V_DRV",
-+			  "UART2_RXD",
-+			  "UART2_TXD";
-+};
-+
-+&gpio8 {
-+	gpio-line-names = "RAM_ID0",
-+			  "RAM_ID1",
-+			  "RAM_ID2",
-+			  "RAM_ID3",
-+			  "I2C1_SDA_TPM",
-+			  "I2C1_SCL_TPM",
-+			  "SPI2_CLK",
-+			  "SPI2_CS0",
-+
-+			  "SPI2_RXD",
-+			  "SPI2_TXD";
-+};
-+
- &pinctrl {
- 	backlight {
- 		bl_pwr_en: bl_pwr_en {
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0045-ARM-dts-rockchip-Switch-to-builtin-HDMI-DDC-bus-on-r.patch

@@ -1,52 +0,0 @@
-From bf09924f21767e6bb7cb3aae48c48c2c2ab8261a Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Thu, 2 May 2019 15:53:34 -0700
-Subject: [PATCH 45/54] ARM: dts: rockchip: Switch to builtin HDMI DDC bus on
- rk3288-veyron
-
-Downstream Chrome OS kernels use the builtin DDC bus from dw_hdmi on
-veyron.  This is the only way to get them to negotiate HDCP.
-
-Although HDCP isn't currently all supported upstream, it still seems
-like it makes sense to use dw_hdmi's builtin I2C.  Maybe eventually we
-can get HDCP negotiation working.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Sean Paul <sean@poorly.run>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron.dtsi | 11 ++---------
- 1 file changed, 2 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index 90c8312d01ff..99e2771d4d31 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -175,7 +175,8 @@
- };
- 
- &hdmi {
--	ddc-i2c-bus = <&i2c5>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&hdmi_ddc>;
- 	status = "okay";
- };
- 
-@@ -346,14 +347,6 @@
- 	i2c-scl-rising-time-ns = <300>;		/* 225ns measured */
- };
- 
--&i2c5 {
--	status = "okay";
--
--	clock-frequency = <100000>;
--	i2c-scl-falling-time-ns = <300>;
--	i2c-scl-rising-time-ns = <1000>;
--};
--
- &io_domains {
- 	status = "okay";
- 
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0046-ARM-dts-rockchip-Add-unwedge-pinctrl-entries-for-dw_.patch

@@ -1,47 +0,0 @@
-From c077d9d717dc481a6a95f9ef2562ef6bda74fbdf Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Thu, 2 May 2019 15:53:35 -0700
-Subject: [PATCH 46/54] ARM: dts: rockchip: Add unwedge pinctrl entries for
- dw_hdmi on rk3288
-
-This adds the "unwedge" pinctrl entries introduced by a recent dw_hdmi
-change that can unwedge the dw_hdmi i2c bus in some cases.  It's
-expected that any boards using this would add:
-
-  pinctrl-names = "default", "unwedge";
-  pinctrl-0 = <&hdmi_ddc>;
-  pinctrl-1 = <&hdmi_ddc_unwedge>;
-
-Note that this isn't added by default because some boards may choose
-to mux i2c5 for their DDC bus (if that is more tested for them).
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Sean Paul <sean@poorly.run>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index 766d1cf51a5b..cc893e154fe5 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -1547,6 +1547,15 @@
- 				rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
- 						<7 RK_PC4 2 &pcfg_pull_none>;
- 			};
-+
-+			hdmi_ddc_unwedge: hdmi-ddc-unwedge {
-+				rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
-+						<7 RK_PC4 2 &pcfg_pull_none>;
-+			};
-+		};
-+
-+		pcfg_output_low: pcfg-output-low {
-+			output-low;
- 		};
- 
- 		pcfg_pull_up: pcfg-pull-up {
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0048-ARM-dts-rockchip-Split-GPIO-keys-for-veyron-into-mul.patch

@@ -1,155 +0,0 @@
-From b8925b7c2f867df6ce3e20deb4b3e2b9b32b20ff Mon Sep 17 00:00:00 2001
-From: Matthias Kaehlcke <mka@chromium.org>
-Date: Wed, 5 Jun 2019 13:43:19 -0700
-Subject: [PATCH 48/54] ARM: dts: rockchip: Split GPIO keys for veyron into
- multiple devices
-
-With a single device DT overrides can become messy, especially when
-keys are added or removed. Multiple devices also allow to
-enable/disable wakeup per key/group.
-
-Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
-[used actual switch+event constants in new lid-switch entry]
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 27 ++++++++++--------
- arch/arm/boot/dts/rk3288-veyron-minnie.dts      | 38 +++++++++++++------------
- arch/arm/boot/dts/rk3288-veyron-pinky.dts       |  2 +-
- arch/arm/boot/dts/rk3288-veyron.dtsi            |  4 +--
- 4 files changed, 38 insertions(+), 33 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-index fbef34578100..5727017f34b2 100644
---- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-@@ -70,6 +70,21 @@
- 		pinctrl-0 = <&ac_present_ap>;
- 	};
- 
-+	lid_switch: lid-switch {
-+		compatible = "gpio-keys";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&ap_lid_int_l>;
-+
-+		lid {
-+			label = "Lid";
-+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
-+			wakeup-source;
-+			linux,code = <SW_LID>;
-+			linux,input-type = <EV_SW>;
-+			debounce-interval = <1>;
-+		};
-+	};
-+
- 	panel: panel {
- 		compatible ="innolux,n116bge", "simple-panel";
- 		status = "okay";
-@@ -149,18 +164,6 @@
- 	status = "okay";
- };
- 
--&gpio_keys {
--	pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;
--	lid {
--		label = "Lid";
--		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
--		wakeup-source;
--		linux,code = <0>; /* SW_LID */
--		linux,input-type = <5>; /* EV_SW */
--		debounce-interval = <1>;
--	};
--};
--
- &pwm0 {
- 	status = "okay";
- };
-diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
-index a65099b4aef1..b2cc70a08554 100644
---- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
-@@ -48,6 +48,26 @@
- 		regulator-boot-on;
- 		vin-supply = <&vcc18_wl>;
- 	};
-+
-+	volume_buttons: volume-buttons {
-+		compatible = "gpio-keys";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&volum_down_l &volum_up_l>;
-+
-+		volum_down {
-+			label = "Volum_down";
-+			gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_VOLUMEDOWN>;
-+			debounce-interval = <100>;
-+		};
-+
-+		volum_up {
-+			label = "Volum_up";
-+			gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
-+			linux,code = <KEY_VOLUMEUP>;
-+			debounce-interval = <100>;
-+		};
-+	};
- };
- 
- &backlight {
-@@ -90,24 +110,6 @@
- 	pwm-off-delay-ms = <200>;
- };
- 
--&gpio_keys {
--	pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>;
--
--	volum_down {
--		label = "Volum_down";
--		gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
--		linux,code = <KEY_VOLUMEDOWN>;
--		debounce-interval = <100>;
--	};
--
--	volum_up {
--		label = "Volum_up";
--		gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
--		linux,code = <KEY_VOLUMEUP>;
--		debounce-interval = <100>;
--	};
--};
--
- &i2c_tunnel {
- 	battery: bq27500@55 {
- 		compatible = "ti,bq27500";
-diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
-index 9645be7b3d8c..9b6f4d9b03b6 100644
---- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
-+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
-@@ -35,7 +35,7 @@
- 	force-hpd;
- };
- 
--&gpio_keys {
-+&lid_switch {
- 	pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
- 
- 	power {
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index c574844a6bb2..3257ca90f0e8 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -23,11 +23,11 @@
- 		reg = <0x0 0x0 0x0 0x80000000>;
- 	};
- 
--	gpio_keys: gpio-keys {
-+	power_button: power-button {
- 		compatible = "gpio-keys";
--
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&pwr_key_l>;
-+
- 		power {
- 			label = "Power";
- 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0050-ARM-dts-rockchip-Allow-wakeup-from-rk3288-veyron-s-d.patch

@@ -1,48 +0,0 @@
-From 1d390437f605db28596ad4c4bfeca2fed052c025 Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Mon, 20 May 2019 10:56:05 -0700
-Subject: [PATCH 50/54] ARM: dts: rockchip: Allow wakeup from rk3288-veyron's
- dwc2 USB ports
-
-We want to be able to wake from USB if a device is plugged in that
-wants remote wakeup.  Enable it on both dwc2 controllers.
-
-NOTE: this is added specifically to veyron and not to rk3288 in
-general since it's not known whether all rk3288 boards are designed to
-support USB wakeup.  It is plausible that some boards could shut down
-important rails in S3.
-
-Also note that currently wakeup doesn't seem to happen unless you use
-the "deep" suspend mode (where SDRAM is turned off).  Presumably the
-shallow suspend mode is gating some sort of clock that's important but
-I couldn't easily figure out how to get it working.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
----
- arch/arm/boot/dts/rk3288-veyron.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index 1252522392c7..1d8bfed7830c 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -424,6 +424,7 @@
- 
- &usb_host1 {
- 	status = "okay";
-+	snps,need-phy-for-wake;
- };
- 
- &usb_otg {
-@@ -432,6 +433,7 @@
- 	assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
- 	assigned-clock-parents = <&usbphy0>;
- 	dr_mode = "host";
-+	snps,need-phy-for-wake;
- };
- 
- &vopb {
--- 
-2.11.0
-

resources/BuildResources/patches-tested/DTS/5.x-dts/0051-ARM-dts-rockchip-Configure-BT_DEV_WAKE-in-on-rk3288-.patch

@@ -1,95 +0,0 @@
-From 4db11c378ab1e170c3a197ea3719ffe54cd06637 Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Wed, 19 Jun 2019 11:34:25 -0700
-Subject: [PATCH 51/54] ARM: dts: rockchip: Configure BT_DEV_WAKE in on
- rk3288-veyron
-
-This is the other half of the hacky solution from commit f497ab6b4bb8
-("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on
-veyron").  Specifically the LPM driver that the Broadcom Bluetooth
-expects to have (but is missing in mainline) has two halves of the
-equation: BT_HOST_WAKE and BT_DEV_WAKE.  The BT_HOST_WAKE (which was
-handled in the previous commit) is the one that lets the Bluetooth
-wake the system up.  The BT_DEV_WAKE (this patch) tells the Bluetooth
-that it's OK to go into a low power mode.  That means we were burning
-a bit of extra power in S3 without this patch.  Measurements are a bit
-noisy, but it appears to be a few mA worth of difference.
-
-NOTE: Though these pins don't do much on systems with Marvell
-Bluetooth, downstream kernels set it on all veyron boards so we'll do
-the same.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi |  2 ++
- arch/arm/boot/dts/rk3288-veyron.dtsi            | 20 ++++++++++++++++++++
- 2 files changed, 22 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-index 5727017f34b2..1cadb522fd0d 100644
---- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-@@ -237,6 +237,7 @@
- 
- 		/* Wake only */
- 		&suspend_l_wake
-+		&bt_dev_wake_awake
- 	>;
- 	pinctrl-1 = <
- 		/* Common for sleep and wake, but no owners */
-@@ -246,6 +247,7 @@
- 
- 		/* Sleep only */
- 		&suspend_l_sleep
-+		&bt_dev_wake_sleep
- 	>;
- 
- 	backlight {
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index e2635ad574e7..53d2f2452868 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -485,12 +485,18 @@
- 		&ddr0_retention
- 		&ddrio_pwroff
- 		&global_pwroff
-+
-+		/* Wake only */
-+		&bt_dev_wake_awake
- 	>;
- 	pinctrl-1 = <
- 		/* Common for sleep and wake, but no owners */
- 		&ddr0_retention
- 		&ddrio_pwroff
- 		&global_pwroff
-+
-+		/* Sleep only */
-+		&bt_dev_wake_sleep
- 	>;
- 
- 	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
-@@ -596,6 +602,20 @@
- 		sdio0_clk: sdio0-clk {
- 			rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
- 		};
-+
-+		/*
-+		 * These pins are only present on very new veyron boards; on
-+		 * older boards bt_dev_wake is simply always high.  Note that
-+		 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
-+		 * to map this pin everywhere
-+		 */
-+		bt_dev_wake_sleep: bt-dev-wake-sleep {
-+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
-+		};
-+
-+		bt_dev_wake_awake: bt-dev-wake-awake {
-+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
-+		};
- 	};
- 
- 	tpm {
--- 
-2.11.0
-

resources/BuildResources/patches-tested/kernel/5.x-dwc2/0044-usb-remove-redundant-default-n-from-Kconfig-s.patch

@@ -1,50 +0,0 @@
-From d991f855cb4f84c638e2016818259720ceed4191 Mon Sep 17 00:00:00 2001
-From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
-Date: Mon, 20 May 2019 16:14:33 +0200
-Subject: [PATCH 44/53] usb: remove redundant 'default n' from Kconfig-s
-
-'default n' is the default value for any bool or tristate Kconfig
-setting so there is no need to write it explicitly.
-
-Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
-is not set' for visible symbols") the Kconfig behavior is the same
-regardless of 'default n' being present or not:
-
-    ...
-    One side effect of (and the main motivation for) this change is making
-    the following two definitions behave exactly the same:
-
-        config FOO
-                bool
-
-        config FOO
-                bool
-                default n
-
-    With this change, neither of these will generate a
-    '# CONFIG_FOO is not set' line (assuming FOO isn't selected/implied).
-    That might make it clearer to people that a bare 'default n' is
-    redundant.
-    ...
-
-Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/dwc2/Kconfig | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig
-index 68d095ae2865..16e1aa304edc 100644
---- a/drivers/usb/dwc2/Kconfig
-+++ b/drivers/usb/dwc2/Kconfig
-@@ -58,7 +58,6 @@ config USB_DWC2_PCI
- 	tristate "DWC2 PCI"
- 	depends on USB_PCI
- 	depends on USB_GADGET || !USB_GADGET
--	default n
- 	select NOP_USB_XCEIV
- 	help
- 	  The Designware USB2.0 PCI interface module for controllers
--- 
-2.11.0
-

resources/BuildResources/patches-tested/kernel/5.x-dwc2/0051-USB-dwc2-Don-t-turn-off-the-usbphy-in-suspend-if-wak.patch

@@ -1,164 +0,0 @@
-From c846b03ff767149d75d4d8dca6d3d4945a21074a Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Mon, 20 May 2019 10:56:04 -0700
-Subject: [PATCH 51/53] USB: dwc2: Don't turn off the usbphy in suspend if
- wakeup is enabled
-
-If the 'snps,need-phy-for-wake' is set in the device tree then:
-
-- We know that we can wakeup, so call device_set_wakeup_capable().
-  The USB core will use this knowledge to enable wakeup by default.
-- We know that we should keep the PHY on during suspend if something
-  on our root hub needs remote wakeup.  This requires the patch (USB:
-  Export usb_wakeup_enabled_descendants()).  Note that we don't keep
-  the PHY on at suspend time if it's not needed because it would be a
-  power draw.
-
-If we later find some users of dwc2 that can support wakeup without
-keeping the PHY on we may want to add a way to call
-device_set_wakeup_capable() without keeping the PHY on at suspend
-time.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Chris Zhong <zyw@rock-chips.com>
-Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
----
- drivers/usb/dwc2/core.h     |  8 ++++++++
- drivers/usb/dwc2/hcd.c      | 19 +++++++++++++++++++
- drivers/usb/dwc2/platform.c | 23 ++++++++++++++++++++---
- 3 files changed, 47 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
-index 152ac41dfb2d..d08d070a0fb6 100644
---- a/drivers/usb/dwc2/core.h
-+++ b/drivers/usb/dwc2/core.h
-@@ -861,6 +861,9 @@ struct dwc2_hregs_backup {
-  * @hibernated:		True if core is hibernated
-  * @reset_phy_on_wake:	Quirk saying that we should assert PHY reset on a
-  *			remote wakeup.
-+ * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
-+ * @need_phy_for_wake:	Quirk saying that we should keep the PHY on at
-+ *			suspend if we need USB to wake us up.
-  * @frame_number:       Frame number read from the core. For both device
-  *			and host modes. The value ranges are from 0
-  *			to HFNUM_MAX_FRNUM.
-@@ -1049,6 +1052,8 @@ struct dwc2_hsotg {
- 	unsigned int ll_hw_enabled:1;
- 	unsigned int hibernated:1;
- 	unsigned int reset_phy_on_wake:1;
-+	unsigned int need_phy_for_wake:1;
-+	unsigned int phy_off_for_suspend:1;
- 	u16 frame_number;
- 
- 	struct phy *phy;
-@@ -1438,6 +1443,7 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
- int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
- int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
- 			       int rem_wakeup, int reset);
-+bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
- static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
- { schedule_work(&hsotg->phy_reset_work); }
- #else
-@@ -1463,6 +1469,8 @@ static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
- static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
- 					     int rem_wakeup, int reset)
- { return 0; }
-+static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
-+{ return false; }
- static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
- 
- #endif
-diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
-index 2192a2873c7c..4c78a390c958 100644
---- a/drivers/usb/dwc2/hcd.c
-+++ b/drivers/usb/dwc2/hcd.c
-@@ -5587,3 +5587,22 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
- 	dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
- 	return ret;
- }
-+
-+bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
-+{
-+	struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub;
-+
-+	/* If the controller isn't allowed to wakeup then we can power off. */
-+	if (!device_may_wakeup(dwc2->dev))
-+		return true;
-+
-+	/*
-+	 * We don't want to power off the PHY if something under the
-+	 * root hub has wakeup enabled.
-+	 */
-+	if (usb_wakeup_enabled_descendants(root_hub))
-+		return false;
-+
-+	/* No reason to keep the PHY powered, so allow poweroff */
-+	return true;
-+}
-diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
-index d10a7f8daec3..3e6c3c8a32ff 100644
---- a/drivers/usb/dwc2/platform.c
-+++ b/drivers/usb/dwc2/platform.c
-@@ -447,6 +447,10 @@ static int dwc2_driver_probe(struct platform_device *dev)
- 	if (retval)
- 		goto error;
- 
-+	hsotg->need_phy_for_wake =
-+		of_property_read_bool(dev->dev.of_node,
-+				      "snps,need-phy-for-wake");
-+
- 	/*
- 	 * Reset before dwc2_get_hwparams() then it could get power-on real
- 	 * reset value form registers.
-@@ -478,6 +482,14 @@ static int dwc2_driver_probe(struct platform_device *dev)
- 		hsotg->gadget_enabled = 1;
- 	}
- 
-+	/*
-+	 * If we need PHY for wakeup we must be wakeup capable.
-+	 * When we have a device that can wake without the PHY we
-+	 * can adjust this condition.
-+	 */
-+	if (hsotg->need_phy_for_wake)
-+		device_set_wakeup_capable(&dev->dev, true);
-+
- 	hsotg->reset_phy_on_wake =
- 		of_property_read_bool(dev->dev.of_node,
- 				      "snps,reset-phy-on-wake");
-@@ -516,13 +528,17 @@ static int dwc2_driver_probe(struct platform_device *dev)
- static int __maybe_unused dwc2_suspend(struct device *dev)
- {
- 	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
-+	bool is_device_mode = dwc2_is_device_mode(dwc2);
- 	int ret = 0;
- 
--	if (dwc2_is_device_mode(dwc2))
-+	if (is_device_mode)
- 		dwc2_hsotg_suspend(dwc2);
- 
--	if (dwc2->ll_hw_enabled)
-+	if (dwc2->ll_hw_enabled &&
-+	    (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
- 		ret = __dwc2_lowlevel_hw_disable(dwc2);
-+		dwc2->phy_off_for_suspend = true;
-+	}
- 
- 	return ret;
- }
-@@ -532,11 +548,12 @@ static int __maybe_unused dwc2_resume(struct device *dev)
- 	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
- 	int ret = 0;
- 
--	if (dwc2->ll_hw_enabled) {
-+	if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
- 		ret = __dwc2_lowlevel_hw_enable(dwc2);
- 		if (ret)
- 			return ret;
- 	}
-+	dwc2->phy_off_for_suspend = false;
- 
- 	if (dwc2_is_device_mode(dwc2))
- 		ret = dwc2_hsotg_resume(dwc2);
--- 
-2.11.0
-

resources/BuildResources/patches-tested/kernel/5.x-dwc2/0052-Revert-usb-dwc2-host-Setting-qtd-to-NULL-after-freei.patch

@@ -1,53 +0,0 @@
-From ad408a1596b45868e38d0504f2ec1d5fb06f17d4 Mon Sep 17 00:00:00 2001
-From: Guenter Roeck <linux@roeck-us.net>
-Date: Wed, 29 May 2019 13:54:43 -0700
-Subject: [PATCH 52/53] Revert "usb: dwc2: host: Setting qtd to NULL after
- freeing it"
-
-This reverts commit b0d659022e5c96ee5c4bd62d22d3da2d66de306b.
-
-The reverted commit does nothing but adding two unnecessary lines
-of code.  It sets a local variable to NULL in two functions, but
-that variable is not used anywhere in the rest of those functions.
-This is just confusing, so let's remove it.
-
-Cc: Vardan Mikayelyan <mvardan@synopsys.com>
-Cc: John Youn <johnyoun@synopsys.com>
-Cc: Douglas Anderson <dianders@chromiun.org>
-Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
-Acked-by: Minas Harutyunyan <hminas@synopsys.com>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
----
- drivers/usb/dwc2/hcd.c | 1 -
- drivers/usb/dwc2/hcd.h | 1 -
- 2 files changed, 2 deletions(-)
-
-diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
-index 4c78a390c958..ee144ff8af5b 100644
---- a/drivers/usb/dwc2/hcd.c
-+++ b/drivers/usb/dwc2/hcd.c
-@@ -4685,7 +4685,6 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
- 	spin_unlock_irqrestore(&hsotg->lock, flags);
- 	urb->hcpriv = NULL;
- 	kfree(qtd);
--	qtd = NULL;
- fail1:
- 	if (qh_allocated) {
- 		struct dwc2_qtd *qtd2, *qtd2_tmp;
-diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h
-index ce6445a06588..8ca6d12a6f57 100644
---- a/drivers/usb/dwc2/hcd.h
-+++ b/drivers/usb/dwc2/hcd.h
-@@ -582,7 +582,6 @@ static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
- {
- 	list_del(&qtd->qtd_list_entry);
- 	kfree(qtd);
--	qtd = NULL;
- }
- 
- /* Descriptor DMA support functions */
--- 
-2.11.0
-

resources/BuildResources/patches-tested/kernel/use-clk_hw_get_rate-in-MMC-phase-calculation.patch

@@ -1,36 +0,0 @@
-From: Douglas Anderson <dianders@chromium.org>
-Date: Tue, 07 May 2019 13:49:58 -0700 (PDT)
-
-When calculating the MMC phase we can just use clk_hw_get_rate()
-instead of clk_get_rate().  This avoids recalculating the rate.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
----
-
- drivers/clk/rockchip/clk-mmc-phase.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
-index 026a26bb702d..07526f64dbfd 100644
---- a/drivers/clk/rockchip/clk-mmc-phase.c
-+++ b/drivers/clk/rockchip/clk-mmc-phase.c
-@@ -55,7 +55,7 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
- static int rockchip_mmc_get_phase(struct clk_hw *hw)
- {
- 	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
--	unsigned long rate = clk_get_rate(hw->clk);
-+	unsigned long rate = clk_hw_get_rate(hw);
- 	u32 raw_value;
- 	u16 degrees;
- 	u32 delay_num = 0;
-@@ -86,7 +86,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
- static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
- {
- 	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
--	unsigned long rate = clk_get_rate(hw->clk);
-+	unsigned long rate = clk_hw_get_rate(hw);
- 	u8 nineties, remainder;
- 	u8 delay_num;
- 	u32 raw_value;
-

scripts/buildKernel.sh

@@ -56,14 +56,13 @@ make clean
 make mrproper
 #Apply the usb and mmc patches if unapplied
 [ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/kernel/5.x-dwc2/*.patch; do echo $i; patch -p1 < $i; done
-[ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/DTS/5.x-dts/*.patch; do echo $i; patch -p1 < $i; done
 [ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/DTS/*.patch; do echo $i; patch -p1 < $i; done
 [ "$FRESH" = true ] && for i in $RESOURCES/patches-tested/kernel/*.patch; do echo $i; patch -p1 < $i; done
 
 #copy in the initramfs and kernel config
 cp $ROOT_DIR/build/PrawnOS-initramfs.cpio.gz .
 cp $RESOURCES/config .config
-make -j `grep ^processor /proc/cpuinfo  | wc -l`  CROSS_COMPILE=arm-none-eabi- ARCH=arm zImage modules dtbs
+make -j $((`nproc` +1))  CROSS_COMPILE=arm-none-eabi- ARCH=arm zImage modules dtbs
 [ ! -h kernel.its ] && ln -s $RESOURCES/kernel.its .
 mkimage -D "-I dts -O dtb -p 2048" -f kernel.its vmlinux.uimg
 dd if=/dev/zero of=bootloader.bin bs=512 count=1