First TGR commit, added firmwares, linux config and kernel patches

2020-09-08 15:14:18 +02:00 · 2020-09-08 15:14:18 +02:00 · 21a1899371
commit 21a1899371
parent 359704c87d
12 changed files with 3718 additions and 0 deletions
--- a/build-apu.sh
+++ b/build-apu.sh
@ -0,0 +1,66 @@
+#!/usr/bin/env bash
+
+# for dependencies
+# apt install -t build-essential libncurses-dev bison flex libssl-dev libelf-dev
+
+#if [ $# -ne 3 ]
+#  then
+#    echo "No arguments supplied"
+#fi
+
+#flag1=$1
+#flag2=$2
+#flag3=$3
+
+flag1="cc{prima_flag}"
+flag2="cc{seconda_flag}"
+flag3="cc{terza_flag}"
+password=`hexdump -n 32 -e '4/4 "%08X"' /dev/urandom`
+
+echo "[+] Starting build script..."
+mkdir -p target/overlay/var/www/html
+
+echo "[+] Cloning buildroot"
+git clone https://github.com/buildroot/buildroot.git target/buildroot
+
+echo "[+] Adding customization files"
+cp -R buildroot/* target/buildroot # copy buildroot configs
+sed -i "s/###ROOTPASSWORD###/$password/g" target/buildroot/configs/pcengines_apu2_defconfig
+cp -R conf/* target/overlay # copy target system config files
+cp -R webpanel/* target/overlay/var/www/html # copy the webpanel
+cp -R update/update.sh target/overlay #copy the update script and certificate
+
+echo "[+] Writing flags"
+sed -i "s/##FLAG1##/$flag1/g" target/overlay/var/www/html/includes/config.php
+echo $flag2 > target/overlay/flag
+chmod 444 target/overlay/flag
+mkdir target/overlay/root
+chmod 700 target/overlay/root
+echo $flag3 > target/overlay/root/flag
+chmod 400 target/overlay/root/flag
+
+echo "[+] Building the keygen"
+mkdir -p target/overlay/usr/sbin
+gcc -o target/overlay/usr/sbin/cfgbin keygen/keygen.c -static -lm
+strip target/overlay/usr/sbin/cfgbin
+
+echo "[+] Generating Update Key"
+mkdir -p target/keys
+openssl genrsa -out target/keys/signingkey.pem 2048
+openssl rsa -in target/keys/signingkey.pem -outform PEM -pubout -out target/keys/signingpub.pem
+cp target/keys/signingpub.pem target/overlay/pub.pem
+
+echo "[+] Generating Monitoring SSH Key"
+ssh-keygen -t ecdsa -f target/keys/sshkey -q -N ""
+mkdir -p target/overlay/root/.ssh
+cp target/keys/sshkey target/overlay/root/.ssh/authorized_keys
+chmod -R 600 target/overlay/root/.ssh/
+
+echo "[+] Saving the root password"
+echo $password > target/keys/rootpassword
+
+echo "[+] Building the image"
+N=`grep -c '^processor' /proc/cpuinfo`
+cd target/buildroot
+make pcengines_apu2_defconfig
+make -j$N
--- a/build-tgr.sh
+++ b/build-tgr.sh
@ -0,0 +1,66 @@
+#!/usr/bin/env bash
+
+# for dependencies
+# apt install -t build-essential libncurses-dev bison flex libssl-dev libelf-dev
+
+#if [ $# -ne 3 ]
+#  then
+#    echo "No arguments supplied"
+#fi
+
+#flag1=$1
+#flag2=$2
+#flag3=$3
+
+flag1="cc{prima_flag}"
+flag2="cc{seconda_flag}"
+flag3="cc{terza_flag}"
+password=`hexdump -n 32 -e '4/4 "%08X"' /dev/urandom`
+
+echo "[+] Starting build script..."
+mkdir -p target/overlay/var/www/html
+
+echo "[+] Cloning buildroot"
+git clone https://github.com/buildroot/buildroot.git target/buildroot
+
+echo "[+] Adding customization files"
+cp -R buildroot/* target/buildroot # copy buildroot configs
+sed -i "s/###ROOTPASSWORD###/$password/g" target/buildroot/configs/pcengines_apu2_defconfig
+cp -R conf/* target/overlay # copy target system config files
+cp -R webpanel/* target/overlay/var/www/html # copy the webpanel
+cp -R update/update.sh target/overlay #copy the update script and certificate
+
+echo "[+] Writing flags"
+sed -i "s/##FLAG1##/$flag1/g" target/overlay/var/www/html/includes/config.php
+echo $flag2 > target/overlay/flag
+chmod 444 target/overlay/flag
+mkdir target/overlay/root
+chmod 700 target/overlay/root
+echo $flag3 > target/overlay/root/flag
+chmod 400 target/overlay/root/flag
+
+echo "[+] Building the keygen"
+mkdir -p target/overlay/usr/sbin
+gcc -o target/overlay/usr/sbin/cfgbin keygen/keygen.c -static -lm
+strip target/overlay/usr/sbin/cfgbin
+
+echo "[+] Generating Update Key"
+mkdir -p target/keys
+openssl genrsa -out target/keys/signingkey.pem 2048
+openssl rsa -in target/keys/signingkey.pem -outform PEM -pubout -out target/keys/signingpub.pem
+cp target/keys/signingpub.pem target/overlay/pub.pem
+
+echo "[+] Generating Monitoring SSH Key"
+ssh-keygen -t ecdsa -f target/keys/sshkey -q -N ""
+mkdir -p target/overlay/root/.ssh
+cp target/keys/sshkey target/overlay/root/.ssh/authorized_keys
+chmod -R 600 target/overlay/root/.ssh/
+
+echo "[+] Saving the root password"
+echo $password > target/keys/rootpassword
+
+echo "[+] Building the image"
+N=`grep -c '^processor' /proc/cpuinfo`
+cd target/buildroot
+make pcengines_apu2_defconfig
+make -j$N
--- a/buildroot/board/tiesse/tgr/kernel-patches/1000-imx8mm-Add-imx8mm-tgr-device-tree.patch
+++ b/buildroot/board/tiesse/tgr/kernel-patches/1000-imx8mm-Add-imx8mm-tgr-device-tree.patch
@ -0,0 +1,671 @@
+diff --git arch/arm64/boot/dts/freescale/Makefile arch/arm64/boot/dts/freescale/Makefile
+index da7ede2f5744..2a0a0f56b9a8 100644
+--- arch/arm64/boot/dts/freescale/Makefile
+++ arch/arm64/boot/dts/freescale/Makefile
+@@ -116,7 +116,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \
+ 				 fsl-imx8mq-evk-inmate.dtb \
+ 				 fsl-imx8mq-evk-dp.dtb \
+ 				 fsl-imx8mq-evk-edp.dtb
+-dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \
+dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-tgr.dtb \
+				 fsl-imx8mm-evk.dtb \
+ 				 fsl-imx8mm-evk-ak4497.dtb \
+ 				 fsl-imx8mm-evk-m4.dtb \
+ 				 fsl-imx8mm-evk-ak5558.dtb \
+diff --git arch/arm64/boot/dts/freescale/fsl-imx8mm-tgr.dts arch/arm64/boot/dts/freescale/fsl-imx8mm-tgr.dts
+new file mode 100755
+index 000000000000..411de1c8c620
+--- /dev/null
+++ arch/arm64/boot/dts/freescale/fsl-imx8mm-tgr.dts
+@@ -0,0 +1,629 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8mm.dtsi"
+
+/ {
+	model = "Tiesse tgr";
+	compatible = "fsl,imx8mm-tgr", "fsl,imx8mm";
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		pwr {
+			label = "pwr";
+			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		lte {
+			label = "lte";
+			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		ble {
+			label = "ble";
+			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		wifi {
+			label = "wifi";
+			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		wan {
+			label = "wan";
+			gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_hub_pwr_on: reg_hub_pwr_on {
+			compatible = "regulator-fixed";
+			regulator-name = "hub_pwr_on";
+			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			status = "okay";
+		};
+
+		reg_modem_pwr_on: reg_modem_pwr_on {
+			compatible = "regulator-fixed";
+			regulator-name = "modem_pwr_on";
+			gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
+			status = "okay";
+		};
+	};
+};
+
+&memory {
+	reg = <0x0 0x40000000 0 0x40000000>;
+};
+
+&linux_cma {
+	size = <0 0x14000000>;
+	alloc-ranges = <0 0x40000000 0 0x30000000>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+	imx8mm-evk {
+
+		pinctrl_hog: hoggrp {
+                        fsl,pins = <
+				/*PCIE WIFI*/
+				MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x10 /* WIFI_EN_PCIE */
+				MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x10 /* PCIE_RESET */
+				MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x10 /* BLE WAKE */
+				MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x10 /* BLE ENABLE */
+
+				/* USB */
+				MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x80 /* OC HUB USB */
+				MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x10 /* USB PWR */
+				MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x80 /* OC USB */
+				MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x10 /* RST HUB */
+
+				/* SDIO WIFI */
+				MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x10 /* SDIO WIFI ENABLE */
+
+				/* MODEM */
+				MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x10 /* MODEM ON/OFF */
+				MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x10 /* MODEM RST */
+				MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x10 /* SIM SELECT */
+				MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x10 /* CMD_POWER */
+                        >;
+                };
+
+		pinctrl_fec1_gpio: fec1grpgpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17	0x10
+				MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x80
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3
+				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
+				MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK      0x4000001f
+				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
+				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
+				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x92
+				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
+				MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER	0x56
+				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x91
+			>;
+		};
+
+		pinctrl_gpio_led: gpioledgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x10
+				MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x10
+				MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x10
+				MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x10
+				MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x10
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_pcie0: pcie0grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19
+			>;
+		};
+
+		pinctrl_pmic: pmicirq {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
+				MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x10
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
+				MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
+				MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
+				MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
+				MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+				MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
+				MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
+				MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x140
+				MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
+			>;
+		};
+
+		pinctrl_usdhc1_gpio: usdhc1grpgpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
+				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
+				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
+				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
+				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
+				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
+				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
+				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
+				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
+				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
+				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
+				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
+				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
+				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
+				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
+				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+				MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc3_gpio: usdhc3grpgpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x10
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+			>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pca9450@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450";
+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		gpo {
+			nxp,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
+		};
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9450,pmic-buck2-uses-i2c-dvs;
+			pca9450,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck3_reg: regulator@2 {
+				reg = <2>;
+				regulator-compatible = "buck3";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+        usb2422@2c {
+                compatible = "microchip,usb2422";
+                reg = <0x2c>;
+                reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+        };
+};
+
+
+&mu {
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_fec1_gpio>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	phy-reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+
+	assigned-clocks = <&clk IMX8MM_CLK_ENET_REF_SRC>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>;
+	assigned-clock-rates = <50000000>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0x5>;
+                        clocks = <&clk IMX8MM_CLK_ENET_REF_SRC>;
+                        clock-names = "rmii-ref";
+		};
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	disable-gpio = <&gpio4 14 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 15 GPIO_ACTIVE_LOW>;
+	ext_osc = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "host";
+	vbus-supply = <&reg_hub_pwr_on>;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	vbus-supply = <&reg_modem_pwr_on>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+	bus-width = <4>;
+	pm-ignore-notify;
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&A53_0 {
+	arm-supply = <&buck2_reg>;
+};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
+index e200219ea8bb..333c9fbaf07f 100644
+--- arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
+++ arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi
+@@ -65,7 +65,7 @@
+ 		};
+ 	};
+ 
+-	memory@40000000 {
+	memory: memory@40000000 {
+ 		device_type = "memory";
+ 		reg = <0x0 0x40000000 0 0x80000000>;
+ 	};
+@@ -76,7 +76,7 @@
+ 		ranges;
+ 
+ 		/* global autoconfigured region for contiguous allocations */
+-		linux,cma {
+		linux_cma: linux,cma {
+ 			compatible = "shared-dma-pool";
+ 			reusable;
+ 			size = <0 0x28000000>;
--- a/buildroot/board/tiesse/tgr/kernel-patches/1001-imx8mm-Add-Microchip-USB2422-support.patch
+++ b/buildroot/board/tiesse/tgr/kernel-patches/1001-imx8mm-Add-Microchip-USB2422-support.patch
@ -0,0 +1,34 @@
+diff --git drivers/usb/misc/usb251xb.c drivers/usb/misc/usb251xb.c
+index 135c91c434bf..a1ca97c07266 100644
+--- drivers/usb/misc/usb251xb.c
+++ drivers/usb/misc/usb251xb.c
+@@ -155,6 +155,11 @@ struct usb251xb_data {
+ 	char product_str[USB251XB_STRING_BUFSIZE / 2]; /* ASCII string */
+ };
+ 
+static const struct usb251xb_data usb2422_data = {
+	.product_id = 0x2422,
+	.product_str = "USB2422",
+};
+
+ static const struct usb251xb_data usb2512b_data = {
+ 	.product_id = 0x2512,
+ 	.product_str = "USB2512B",
+@@ -492,6 +497,9 @@ static int usb251xb_get_ofdata(struct usb251xb *hub,
+ 
+ static const struct of_device_id usb251xb_of_match[] = {
+ 	{
+		.compatible = "microchip,usb2422",
+		.data = &usb2422_data,
+	}, {
+ 		.compatible = "microchip,usb2512b",
+ 		.data = &usb2512b_data,
+ 	}, {
+@@ -567,6 +575,7 @@ static int usb251xb_i2c_probe(struct i2c_client *i2c,
+ }
+ 
+ static const struct i2c_device_id usb251xb_id[] = {
+	{ "usb2422", 0 },
+ 	{ "usb2512b", 0 },
+ 	{ "usb2512bi", 0 },
+ 	{ "usb2513b", 0 },
--- a/buildroot/board/tiesse/tgr/kernel-patches/1002-imx8mm-Add-PCA9450-PMIC-support.patch
+++ b/buildroot/board/tiesse/tgr/kernel-patches/1002-imx8mm-Add-PCA9450-PMIC-support.patch
--- a/buildroot/board/tiesse/tgr/linux.config
+++ b/buildroot/board/tiesse/tgr/linux.config
@ -0,0 +1,871 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_BCM2835=y
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_LG1K=y
+CONFIG_ARCH_HISI=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MESON=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SEATTLE=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A7795=y
+CONFIG_ARCH_R8A7796=y
+CONFIG_ARCH_STRATIX10=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_SPRD=y
+CONFIG_ARCH_THUNDER=y
+CONFIG_ARCH_THUNDER2=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_XGENE=y
+CONFIG_ARCH_ZX=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_ARCH_FSL_IMX8QM=y
+CONFIG_ARCH_FSL_IMX8QP=y
+CONFIG_ARCH_FSL_IMX8QXP=y
+CONFIG_ARCH_FSL_IMX8MQ=y
+CONFIG_ARCH_FSL_IMX8MM=y
+CONFIG_PCI=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCI_IOV=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_PCI_IMX6=y
+CONFIG_PCI_HISI=y
+CONFIG_PCIE_KIRIN=y
+CONFIG_PCI_AARDVARK=y
+CONFIG_PCIE_RCAR=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCIE_ROCKCHIP=m
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_NUMA=y
+CONFIG_PREEMPT=y
+CONFIG_KSM=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_CMA=y
+CONFIG_SECCOMP=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_XEN=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_COMPAT=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
+CONFIG_ARM_IMX8_CPUFREQ=y
+CONFIG_ARM_IMX8MQ_CPUFREQ=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_RR=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_LLC2=y
+CONFIG_BPF_JIT=y
+CONFIG_CAN=y
+CONFIG_CAN_FLEXCAN=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+# CONFIG_BT_HS is not set
+# CONFIG_BT_LE is not set
+CONFIG_BT_LEDS=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIVHCI=y
+CONFIG_CFG80211=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_DEVELOPER_WARNINGS=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211_DEBUG=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+CONFIG_MAC80211_MESSAGE_TRACING=y
+CONFIG_MAC80211_DEBUG_MENU=y
+CONFIG_MAC80211_NOINLINE=y
+CONFIG_MAC80211_VERBOSE_DEBUG=y
+CONFIG_MAC80211_MLME_DEBUG=y
+CONFIG_MAC80211_STA_DEBUG=y
+CONFIG_MAC80211_HT_DEBUG=y
+CONFIG_MAC80211_OCB_DEBUG=y
+CONFIG_MAC80211_IBSS_DEBUG=y
+CONFIG_MAC80211_PS_DEBUG=y
+CONFIG_MAC80211_MPL_DEBUG=y
+CONFIG_MAC80211_MPATH_DEBUG=y
+CONFIG_MAC80211_MHWMP_DEBUG=y
+CONFIG_MAC80211_MESH_SYNC_DEBUG=y
+CONFIG_MAC80211_MESH_CSA_DEBUG=y
+CONFIG_MAC80211_MESH_PS_DEBUG=y
+CONFIG_MAC80211_TDLS_DEBUG=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=320
+CONFIG_ARM_CCI400_PMU=y
+CONFIG_ARM_CCI5xx_PMU=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_RAM=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SLRAM=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_SPI_FSL_FLEXSPI=y
+CONFIG_MTD_UBI=y
+CONFIG_OF_OVERLAY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_XEN_BLKDEV_BACKEND=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=m
+CONFIG_SENSORS_FXOS8700=y
+CONFIG_SENSORS_FXAS2100X=y
+CONFIG_SRAM=y
+CONFIG_EEPROM_AT25=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_HISI_SAS=y
+CONFIG_SCSI_HISI_SAS_PCI=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_SATA_SIL24=y
+CONFIG_SATA_RCAR=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_VXLAN=m
+CONFIG_TUN=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_AMD_XGBE=y
+CONFIG_NET_XGENE=y
+CONFIG_MACB=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
+CONFIG_IGBVF=y
+CONFIG_MVNETA=y
+CONFIG_MVPP2=y
+CONFIG_SKY2=y
+CONFIG_QCOM_EMAC=m
+CONFIG_RAVB=y
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+CONFIG_STMMAC_ETH=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_AT803X_PHY=y
+CONFIG_MARVELL_PHY=m
+CONFIG_MESON_GXL_PHY=m
+CONFIG_MICREL_PHY=y
+CONFIG_NXP_TJA110X_PHY=y
+CONFIG_REALTEK_PHY=m
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_PPP=y
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_HOSTAP=y
+CONFIG_RTL_CARDS=m
+# CONFIG_WLAN_VENDOR_TI is not set
+CONFIG_XEN_NETDEV_BACKEND=m
+CONFIG_IVSHMEM_NET=y
+CONFIG_INPUT_POLLDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX_SC_PWRKEY=y
+CONFIG_KEYBOARD_CROS_EC=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PM8941_PWRKEY=y
+CONFIG_INPUT_HISI_POWERKEY=y
+CONFIG_INPUT_MPL3115=y
+CONFIG_INPUT_ISL29023=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MESON=y
+CONFIG_SERIAL_MESON_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=11
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_BCM2835=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_I2C_MESON=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_PXA=y
+CONFIG_I2C_QUP=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_RPBUS=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_TEGRA=y
+CONFIG_I2C_UNIPHIER_F=y
+CONFIG_I2C_RCAR=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_XEN_I2C_BACKEND=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM2835=m
+CONFIG_SPI_BCM2835AUX=m
+CONFIG_SPI_FSL_LPSPI=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_MESON_SPICC=m
+CONFIG_SPI_MESON_SPIFC=m
+CONFIG_SPI_ORION=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_S3C64XX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SLAVE_TIME=y
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_MAX77620=y
+CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_MSM8916=y
+CONFIG_PINCTRL_MSM8994=y
+CONFIG_PINCTRL_MSM8996=y
+CONFIG_PINCTRL_QDF2XXX=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_RCAR=y
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_XGENE_SB=y
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_MAX77620=y
+CONFIG_POWER_AVS=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_INA2XX=m
+# CONFIG_MXC_MMA8451 is not set
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_IMX8M_THERMAL=y
+CONFIG_IMX8MM_THERMAL=y
+CONFIG_IMX_SC_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_ROCKCHIP_THERMAL=m
+CONFIG_EXYNOS_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_S3C2410_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_IMX8_WDT=y
+CONFIG_MESON_GXBB_WATCHDOG=m
+CONFIG_MESON_WATCHDOG=m
+CONFIG_RENESAS_WDT=y
+CONFIG_UNIPHIER_WATCHDOG=y
+CONFIG_BCM2835_WDT=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_I2C=y
+CONFIG_MFD_CROS_EC_SPI=y
+CONFIG_MFD_EXYNOS_LPASS=m
+CONFIG_MFD_HI6421_PMIC=y
+CONFIG_MFD_HI655X_PMIC=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_BD71837=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_HI6421V530=y
+CONFIG_REGULATOR_HI655X=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_BD71837=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_GPIO_CIR=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_DVB_NET is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MXC_CAPTURE=y
+CONFIG_VIDEO_MX8_CAPTURE=y
+CONFIG_GMSL_MAX9286=y
+CONFIG_VIDEO_MXC_CSI_CAMERA=y
+CONFIG_MXC_MIPI_CSI=y
+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+CONFIG_VIDEO_RENESAS_FCP=m
+CONFIG_VIDEO_RENESAS_VSP1=m
+CONFIG_IMX_DPU_CORE=y
+CONFIG_IMX_DCSS_CORE=y
+CONFIG_IMX_LCDIF_CORE=y
+CONFIG_DRM=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_EXYNOS=m
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DSI=y
+# CONFIG_DRM_EXYNOS_DP is not set
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_MIC=y
+CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_DRM_RCAR_DU=m
+CONFIG_DRM_RCAR_LVDS=y
+CONFIG_DRM_RCAR_VSP=y
+CONFIG_DRM_MSM=m
+CONFIG_DRM_TEGRA=m
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
+CONFIG_DRM_NXP_SEIKO_43WVFIG=y
+CONFIG_DRM_I2C_ADV7511=y
+CONFIG_DRM_ITE_IT6263=y
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
+CONFIG_DRM_IMX_TVE=y
+CONFIG_DRM_IMX_LDB=y
+CONFIG_DRM_IMX_HDMI=y
+CONFIG_DRM_IMX_NWL_DSI=y
+CONFIG_DRM_IMX_SEC_DSIM=y
+CONFIG_DRM_IMX_HDP=y
+CONFIG_IMX_HDP_CEC=y
+CONFIG_DRM_VC4=m
+CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_MXSFB=y
+CONFIG_DRM_MESON=m
+CONFIG_FB_IMX64=y
+CONFIG_FB_IMX64_DEBUG=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_MXC_DISP_FRAMEWORK=y
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_BCM2835_SOC_I2S=m
+CONFIG_SND_SOC_FSL_ACM=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_IMX_AK4458=y
+CONFIG_SND_SOC_IMX_AK5558=y
+CONFIG_SND_SOC_IMX_AK4497=y
+CONFIG_SND_SOC_IMX_WM8960=y
+CONFIG_SND_SOC_IMX_WM8524=y
+CONFIG_SND_SOC_IMX_CS42888=y
+CONFIG_SND_SOC_IMX_WM8962=y
+CONFIG_SND_SOC_IMX_MICFIL=y
+CONFIG_SND_SOC_IMX_RPMSG=y
+CONFIG_SND_SOC_IMX_MQS=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_AMIX=y
+CONFIG_SND_SOC_IMX_CDNHDMI=y
+CONFIG_SND_SOC_IMX_DSP=y
+CONFIG_SND_SOC_SAMSUNG=y
+CONFIG_SND_SOC_RCAR=y
+CONFIG_SND_SOC_AK4613=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_WHITELIST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_EHCI_EXYNOS=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_EXYNOS=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_HCD_TEST_MODE=y
+CONFIG_USB_RENESAS_USBHS=m
+CONFIG_USB_ACM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_ISP1760_HOST_ROLE=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_TEST=m
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_USB_HUB_USB251XB=y
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_QCOM_8X16_PHY=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_FSL_UTP=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_AUDIO=m
+CONFIG_GADGET_UAC1=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_XENON=y
+# CONFIG_MXC_GPU_VIV is not set
+CONFIG_MXC_MLB150=y
+CONFIG_MXC_SIM=y
+CONFIG_MXC_EMVSIM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_RK808=m
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_S3C=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_RTC_DRV_IMX_SC=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BCM2835=m
+CONFIG_FSL_EDMA_V3=y
+CONFIG_IMX_SDMA=y
+CONFIG_K3_DMA=y
+CONFIG_MV_XOR_V2=y
+CONFIG_MXS_DMA=y
+CONFIG_PL330_DMA=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_RCAR_DMAC=y
+CONFIG_UIO=y
+CONFIG_UIO_PCI_GENERIC=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_STAGING=y
+CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
+CONFIG_ION_CMA_HEAP=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_TCPCI=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_CLK_QORIQ=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_IPQ_GCC_8074=y
+CONFIG_MSM_GCC_8916=y
+CONFIG_MSM_GCC_8994=y
+CONFIG_MSM_MMCC_8996=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_CLKSRC_IMX_SYS_CNT=y
+CONFIG_ARM_MHU=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_BCM2835_MBOX=y
+CONFIG_HI6220_MBOX=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_ARCH_MXC_ARM64=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+CONFIG_ARCH_TEGRA_132_SOC=y
+CONFIG_ARCH_TEGRA_210_SOC=y
+CONFIG_ARCH_TEGRA_186_SOC=y
+CONFIG_EXTCON_PTN5150=y
+CONFIG_IIO=y
+CONFIG_EXYNOS_ADC=y
+CONFIG_IMX8QXP_ADC=y
+CONFIG_ROCKCHIP_SARADC=m
+CONFIG_PWM=y
+CONFIG_PWM_BCM2835=m
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_FSL_FTM=y
+CONFIG_PWM_IMX=y
+CONFIG_PWM_MESON=m
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SAMSUNG=y
+CONFIG_PWM_TEGRA=m
+CONFIG_PHY_XGENE=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_HI6220_USB=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_PCIE=m
+CONFIG_PHY_TEGRA_XUSB=y
+CONFIG_QCOM_L2_PMU=y
+CONFIG_QCOM_L3_PMU=y
+CONFIG_IMX8_DDR_PERF=y
+CONFIG_NVMEM_IMX_OCOTP=y
+CONFIG_NVMEM_IMX_SCU_OCOTP=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_ACPI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_OVERLAY_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_HUGETLBFS=y
+CONFIG_EFIVAR_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
+CONFIG_SECURITY=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA512_ARM64=m
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+CONFIG_CRYPTO_CRC32_ARM64_CE=m
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_AES_ARM64_BS=m
+
--- a/buildroot/board/tiesse/tgr/wireless-patches/0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch
+++ b/buildroot/board/tiesse/tgr/wireless-patches/0001-MLK-18491-02-qcacld-2.0-fix-the-overflow-of-bounce-b.patch
@ -0,0 +1,91 @@
+From 16573cbb9c82218f93741a9bc873242c012ac061 Mon Sep 17 00:00:00 2001
+From: Hangtian Zhu <hangtian@qti.qualcomm.com>
+Date: Thu, 14 Jun 2018 11:10:05 +0800
+Subject: [PATCH 22/23] MLK-18491-02 qcacld-2.0: fix the overflow of bounce
+ buffer
+
+Patch a41baa51cbc5("MLK-18491 qcacld-2.0: avoid overflow of bounce buffer")
+is not reasonable to fix overflow of bounce buffer issue.
+
+The patch is released by Qualcomm to fix the issue.
+(Case Number:03515221)
+
+Signed-off-by: Hangtian Zhu <hangtian@qti.qualcomm.com>
+---
+ CORE/SERVICES/HTC/htc.c      |  2 +-
+ CORE/SERVICES/HTC/htc_send.c | 28 ++++++++++++++--------------
+ 2 files changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/CORE/SERVICES/HTC/htc.c b/CORE/SERVICES/HTC/htc.c
+index 1e2450d..09936a0 100644
+--- a/CORE/SERVICES/HTC/htc.c
+++ b/CORE/SERVICES/HTC/htc.c
+@@ -657,7 +657,7 @@ static void ResetEndpointStates(HTC_TARGET *target)
+         INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBufferHoldQueue);
+         pEndpoint->target = target;
+         //pEndpoint->TxCreditFlowEnabled = (A_BOOL)htc_credit_flow;
+-        pEndpoint->TxCreditFlowEnabled = (A_BOOL)0;
+        pEndpoint->TxCreditFlowEnabled = (A_BOOL)1;
+         adf_os_atomic_init(&pEndpoint->TxProcessCount);
+     }
+ }
+diff --git a/CORE/SERVICES/HTC/htc_send.c b/CORE/SERVICES/HTC/htc_send.c
+index 1a3dd28..19d8065 100644
+--- a/CORE/SERVICES/HTC/htc_send.c
+++ b/CORE/SERVICES/HTC/htc_send.c
+@@ -105,12 +105,12 @@ void HTCGetControlEndpointTxHostCredits(HTC_HANDLE HTCHandle, int *credits)
+ 
+ static INLINE void RestoreTxPacket(HTC_TARGET *target, HTC_PACKET *pPacket)
+ {
+    adf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
+     if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) {
+-        adf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
+         adf_nbuf_unmap(target->osdev, netbuf, ADF_OS_DMA_TO_DEVICE);
+-        adf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR));
+         pPacket->PktInfo.AsTx.Flags &= ~HTC_TX_PACKET_FLAG_FIXUP_NETBUF;
+     }
+    adf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR));
+ 
+ }
+ 
+@@ -641,12 +641,11 @@ static A_STATUS HTCIssuePackets(HTC_TARGET       *target,
+              * that is already mapped, or a non-data netbuf that needs to be
+              * mapped.
+              */
+-            if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) {
+-                adf_nbuf_map(
+-                        target->osdev,
+-                        GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket),
+-                        ADF_OS_DMA_TO_DEVICE);
+-            }
+            pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF;
+            adf_nbuf_map(
+                    target->osdev,
+                    GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket),
+                    ADF_OS_DMA_TO_DEVICE);
+         }
+         LOCK_HTC_TX(target);
+             /* store in look up queue to match completions */
+@@ -1261,12 +1260,13 @@ A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
+              * mapped.  This only applies to non-data frames, since data frames
+              * were already mapped as they entered into the driver.
+              */
+-            adf_nbuf_map(
+-                    target->osdev,
+-                    GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket),
+-                    ADF_OS_DMA_TO_DEVICE);
+-
+-	pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF;
+            if(!IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
+	        pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF;
+                adf_nbuf_map(
+                        target->osdev,
+                        GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket),
+                        ADF_OS_DMA_TO_DEVICE);
+	    }
+     } HTC_PACKET_QUEUE_ITERATE_END;
+ 
+     HTCTrySend(target,pEndpoint,pPktQueue);
+-- 
+1.9.1
+
--- a/firmware/qca6174/bdwlan30.bin
+++ b/firmware/qca6174/bdwlan30.bin
--- a/firmware/qca6174/otp30.bin
+++ b/firmware/qca6174/otp30.bin
--- a/firmware/qca6174/qwlan30.bin
+++ b/firmware/qca6174/qwlan30.bin
--- a/firmware/qca6174/utf30.bin
+++ b/firmware/qca6174/utf30.bin
--- a/firmware/wlan/qca6174/qcom_cfg.ini
+++ b/firmware/wlan/qca6174/qcom_cfg.ini
@ -0,0 +1,403 @@
+# This file allows user to override the factory
+
+# defaults for the WLAN Driver
+
+#Host module debug
+vosTraceEnableHDD=0
+vosTraceEnableWDA=0
+vosTraceEnableWDI=0
+vosTraceEnableSME=0
+vosTraceEnablePE=0
+vosTraceEnableWMA=0
+vosTraceEnableVOSS=0
+gEnableLogp=1
+
+#Prioritize user(hostapd, iw,) specified country
+gCountryCodePriority=1 
+
+#Host logging
+gMulticastHostFwMsgs=0
+
+#packetlog 
+gEnablePacketLog=0
+
+#Enable firmware uart print
+gEnablefwprint=0
+
+#Enable firmware log
+gEnablefwlog=0
+
+# Disable FW log function by default
+gFwDebugLogType=0
+gFwDebugModuleLoglevel=0,0
+
+# Generic
+
+# Phy Mode (auto, b, g, n, etc)
+# Valid values are 0-9, with 0 = Auto, 4 = 11n, 9 = 11ac
+# 1 = 11abg, 2 = 11b, 3 = 11g, 5 = 11g only, 6 = 11n only
+# 7 = 11b only 8 = 11ac only.
+gDot11Mode=0
+
+# VHT Tx/Rx MCS values
+# Valid values are 0,1,2. If commented out, the default value is 0.
+# 0=MCS0-7, 1=MCS0-8, 2=MCS0-9
+gVhtRxMCS=2
+gVhtTxMCS=2
+
+# VHT Tx/Rx MCS values for 2x2
+# Valid values are 0,1,2. If commented out, the default value is 0.
+# 0=MCS0-7, 1=MCS0-8, 2=MCS0-9
+gEnable2x2=1
+gVhtRxMCS2x2=2
+gVhtTxMCS2x2=2
+
+gVhtChannelWidth=2
+
+#Short Guard Interval Enable/disable
+gShortGI20Mhz=1
+gShortGI40Mhz=1
+
+#Channel Bonding
+gChannelBondingMode5GHz=1
+
+# 1=enable STBC; 0=disable STBC
+gEnableRXSTBC=1
+
+# 1=enable tx STBC; 0=disable
+gEnableTXSTBC=1
+
+# 1=enable rx LDPC; 0=disable
+gEnableRXLDPC=1
+
+#If set to 0, MCC is not allowed.
+gEnableMCCMode=1
+
+# Enable or Disable MCC Adaptive Scheduler at the FW
+# 1=Enable (default), 0=Disable
+gEnableMCCAdaptiveScheduler=1
+
+# Enable BMPS or not
+gEnableBmps=1
+
+# Enable IMPS or not
+gEnableImps=1
+
+# Enable/Disable Idle Scan
+gEnableIdleScan=0
+
+#Data Inactivity Timeout when in powersave (in ms)
+gDataInactivityTimeout=200
+
+# Increase sleep duration (seconds) during IMPS
+# 0 implies no periodic wake up from IMPS. Periodic wakeup is
+# unnecessary if Idle Scan is disabled.
+gImpsModSleepTime=0
+
+# Enable suspend or not
+# 1: Enable standby, 2: Enable Deep sleep, 3: Enable Mcast/Bcast Filter
+gEnableSuspend=3
+
+
+#Enable/Disable UAPSD for SoftAP
+gEnableApUapsd=1
+
+# UAPSD service interval for VO,VI, BE, BK traffic
+InfraUapsdVoSrvIntv=0
+InfraUapsdViSrvIntv=0
+InfraUapsdBeSrvIntv=0
+InfraUapsdBkSrvIntv=0
+
+# Flag to allow STA send AddTspec even when ACM is Off
+gAddTSWhenACMIsOff=1
+
+# Beacon filtering frequency (unit in beacon intervals)
+gNthBeaconFilter=50
+
+# Enable WAPI or not
+WAPIIsEnabled=0
+# Flags to filter Mcast abd Bcast RX packets.
+# Value 0: No filtering, 1: Filter all Multicast.
+# 2: Filter all Broadcast. 3: Filter all Mcast abd Bcast
+McastBcastFilter=3
+
+#Flag to enable HostARPOffload feature or not
+hostArpOffload=0
+
+#Flag to enable TCPChkSumOffld feature or not
+gEnableTCPChkSumOffld=0
+
+#Flag to enable HostNSOffload feature or not
+hostNSOffload=1
+gActiveModeOffload=1
+
+#Flag to enable IPChkSumOffld feature or not
+gEnableIPChecksumOffload=0
+
+# 802.11n Protection flag
+gEnableApProt=1
+
+#Enable OBSS protection
+gEnableApOBSSProt=1
+
+# Fixed Rate
+gFixedRate=0
+
+# RTS threshold
+RTSThreshold=192000
+
+# Intra-BSS forward
+gDisableIntraBssFwd=0
+
+# WMM Enable/Disable
+WmmIsEnabled=0
+
+# 802.11d support
+g11dSupportEnabled=1
+
+# 802.11h support
+g11hSupportEnabled=1
+
+# ESE Support and fast transition
+EseEnabled=0
+ImplicitQosIsEnabled=0
+gNeighborScanTimerPeriod=200
+
+gNeighborLookupThreshold=76
+gNeighborReassocThreshold=81
+
+gNeighborScanChannelMinTime=20
+gNeighborScanChannelMaxTime=30
+gMaxNeighborReqTries=3
+
+gEnableFastRoamInConcurrency=1
+
+# CSR Roaming Enable(1) Disable(0)
+gRoamingTime=0
+
+# Roaming Preference
+gRoamPrefer5GHz=1
+gSelect5GHzMargin=20
+
+# Legacy (non-ESE, non-802.11r) Fast Roaming Support
+# To enable, set FastRoamEnabled=1
+# To disable, set FastRoamEnabled=0
+FastRoamEnabled=1
+
+#Check if the AP to which we are roaming is better than current AP in terms of RSSI.
+#Checking is disabled if set to Zero.Otherwise it will use this value as to how better
+#the RSSI of the new/roamable AP should be for roaming
+RoamRssiDiff=3
+
+# If the RSSI of any available candidate is better than currently associated
+# AP by at least gImmediateRoamRssiDiff, then being to roam immediately (without
+# registering for reassoc threshold).
+# NOTE: Value of 0 means that we would register for reassoc threshold.
+gImmediateRoamRssiDiff=10
+
+# To enable, set gRoamIntraBand=1 (Roaming within band)
+# To disable, set gRoamIntraBand=0 (Roaming across band)
+gRoamIntraBand=0
+
+# SAP Country code
+# Default Country Code is 2 bytes, 3rd byte is optional indoor or out door.
+# Example
+#   US Indoor, USI
+#   Korea Outdoor, KRO
+#   Japan without optional byte, JP
+#   France without optional byte, FR
+#gAPCntryCode=US
+
+#Auto Shutdown  Value in seconds. A value of 0 means Auto shutoff is disabled
+gAPAutoShutOff=0
+
+# SAP auto channel selection configuration
+# 0 = disable auto channel selection
+# 1 = enable auto channel selection, channel provided by supplicant will be ignored
+gApAutoChannelSelection=0
+
+#Preferred band (both or 2.4 only or 5 only)
+BandCapability=0
+
+#Beacon Early Termination (1 = enable the BET feature, 0 = disable)
+enableBeaconEarlyTermination=0
+beaconEarlyTerminationWakeInterval=3
+
+#SOFTAP Channel Range selection
+gAPChannelSelectStartChannel=1
+gAPChannelSelectEndChannel=11
+
+#SOFTAP Channel Range selection Operating band
+# 0:2.4GHZ 1: LOW-5GHZ 2:MID-5GHZ 3:HIGH-5GHZ 4: 4.9HZ BAND
+gAPChannelSelectOperatingBand=0
+
+# Listen Energy Detect Mode Configuration
+# Valid values 0-128
+# 128 means disable Energy Detect feature
+# 0-9 are threshold code and 7 is recommended value from system if feature is to be enabled.
+# 10-128 are reserved.
+# The EDET threshold mapping is as follows in 3dB step:
+# 0 = -60 dBm
+# 1 = -63 dBm
+# 2 = -66 dBm
+# ...
+# 7 = -81 dBm
+# 8 = -84 dBm
+# 9 = -87 dBm
+
+# Note: Any of these settings are valid. Setting 0 would yield the highest power saving (in a noisy environment) at the cost of more range. The range impact is approximately #calculated as:
+
+#
+#  Range Loss  (dB)  =  EDET threshold level (dBm) + 97 dBm.
+#
+gEnablePhyAgcListenMode=128
+
+#Enable Keep alive with non-zero period value
+gStaKeepAlivePeriod = 30
+#Say gGoKeepAlivePeriod(5 seconds) and gGoLinkMonitorPeriod(10 seconds).
+#For every 10 seconds DUT send Qos Null frame(i.e., Keep Alive frame if link is idle for last 10 seconds.)
+#For both active and power save clients.
+
+#Power save clients: DUT set TIM bit from 10th second onwards and till client honors TIM bit.
+#If doesn't honor for 5 seconds then DUT remove client.
+
+#Active clients: DUT send Qos Null frame for 10th seconds onwards if it is not success still we try on
+#11th second if not tries on 12th and so on till 15th second. Hence before disconnection DUT will send 5 NULL frames.
+#Hence in any case DUT will detect client got removed in (10+5) seconds. i.e., (gGoKeepAlivePeriod + gGoLinkMonitorPeriod)..
+
+#gGoLinkMonitorPeriod/ gApLinkMonitorPeriod is period where link is idle and it is period
+#where we send NULL frame.
+gApLinkMonitorPeriod = 10
+gGoLinkMonitorPeriod = 10
+
+#gGoKeepAlivePeriod/gApKeepAlivePeriod is time to spend to check whether frame are succeed to send or not.
+#Hence total effective detection time is gGoLinkMonitorPeriod+ gGoKeepAlivePeriod/gApLinkMonitorPeriod+ gApKeepAlivePeriod.
+gGoKeepAlivePeriod = 20
+gApKeepAlivePeriod = 20
+
+#If set will start with active scan after driver load, otherwise will start with
+#passive scan to find out the domain
+gEnableBypass11d=1
+
+#If set to 0, will not scan DFS channels
+gEnableDFSChnlScan=1
+
+# Enable Automatic Tx Power control
+gEnableAutomaticTxPowerControl=1
+
+# 0 for OLPC 1 for CLPC and SCPC
+gEnableCloseLoop=1
+
+# Scan Timing Parameters
+gPassiveMaxChannelTime=110
+gPassiveMinChannelTime=60
+gActiveMaxChannelTime=40
+gActiveMinChannelTime=20
+
+# Enable Active mode offload
+gEnableActiveModeOffload=1
+
+#Enable Scan Results Aging based on timer
+#Timer value is in seconds
+#If Set to 0 it will not enable the feature
+gScanAgingTime=0
+
+#Enable Power saving mechanism Based on Android Framework
+#If set to 0 Driver internally control the Power saving mechanism
+#If set to 1 Android Framwrok control the Power saving mechanism
+isAndroidPsEn=0
+
+#disable LDPC in STA mode if the AP is TXBF capable
+gDisableLDPCWithTxbfAP=0
+
+#Enable thermal mitigation
+gThermalMitigationEnable=1
+gThermalTempMinLevel1=90
+gThermalTempMaxLevel0=110
+gThermalTempMaxLevel1=115
+gThrottlePeriod=100
+
+#List of Country codes for which 11ac needs to be disabled
+#Each country code must be delimited by comma(,)
+gListOfNon11acCountryCode=RU,UA,ZA
+
+#Maxium Channel time in msec
+gMaxMediumTime = 6000
+
+#FlexConnect Power Factor
+#Default is set to 0 (disable)
+gFlexConnectPowerFactor=0
+
+#Disable split scan, the FW will take care of it
+gNumChanCombinedConc=60
+
+#Enable Power Save offload
+gEnablePowerSaveOffload=1
+
+gEnableWoW=1
+
+#Enable or Disable p2p device address administered
+isP2pDeviceAddrAdministrated=0
+
+#Disable scan_pno by default
+gPNOScanSupport=0
+
+#Enable TDLS
+gEnableTDLSSupport=1
+
+# Regulatory Setting; 0=STRICT; 1=CUSTOM
+gRegulatoryChangeCountry=1
+
+# Enable or Disable Rx thread
+# 1=Enable (default), 0=Disable
+gEnableRxThread=0
+
+# Enable or Disable FW self-recovery
+# Currently, It's for USB only.
+# 1=Enable, 0=Disable (default)
+gEnableFwSelfRecovery=0
+gEnableSelfRecovery=0
+gEnableForceTargetAssert=0
+# Enable or Disable SAP suspend
+# 1=Enable (default), 0=Disable
+gEnableSapSuspend=0
+
+# Enable TxBF
+gTxBFEnable=1
+
+# Enable or Disable WOW Pulse feature
+# 1 = Enable, 0 = Disable (default)
+gwow_pulse_support = 0
+
+#P2P Listen offload
+gEnableP2pListenOffload=1
+
+# gEnableSAPAuthOffload: Enable Software AP Authentication Offload feature
+# 1=Enable, 0=Disable (default)
+gEnableSAPAuthOffload=0
+
+# Sifs burst feature configuration
+gEnableSifsBurst=1
+gSoftApMaxPeers=32
+
+gVhtMpduLen=2
+# FW reorder
+gReorderOffloadSupported=1
+# DFS Master Capability
+gEnableDFSMasterCap=1
+
+#Fine tuned TxFlow parameters
+TxFlowLowWaterMark=300
+TxFlowHighWaterMarkOffset=94
+
+# PTA
+gCoexPtaConfigEnable=0
+gCoexPtaConfigParam=0
+gEnableNanSupport=0
+
+#ETSI
+gStaLocalEDCAForETSI=0
+#TxBF in 20MHz
+gEnableTxBFin20MHz=1
+END
+# Note: Configuration parser would not read anything past the END marker